feat(st-clock): don't gate/ungate an oscillator if it is not wired

If the oscillator is not present, the gating will fail.

Change-Id: If9119460a4bcd42053537f1975afe5fe1df05752
Signed-off-by: Gabrie

feat(st-clock): don't gate/ungate an oscillator if it is not wired

If the oscillator is not present, the gating will fail.

Change-Id: If9119460a4bcd42053537f1975afe5fe1df05752
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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feat(st-clock): update with new bindings

Code alignment with MP13 driver.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: Ifb0597721a865f463cf41c5cd7be3ca75a1da80c

feat(stm32mp1): always boot at 650MHz

Switching to higher CPU frequencies requires a dedicated chip version
(STM32MP1xxD or STM32MP1xxF), and increase CPU voltage. To avoid
re-configuring I2C and PM

feat(stm32mp1): always boot at 650MHz

Switching to higher CPU frequencies requires a dedicated chip version
(STM32MP1xxD or STM32MP1xxF), and increase CPU voltage. To avoid
re-configuring I2C and PMIC before and after applying clock tree,
always boot at 650MHz, which is the frequency for nominal voltage.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Id05a3ee17e7dd57e2d64dc06f8f1e7f9cb21e110

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refactor(st-clock): remove LSEDRV_MEDIUM_HIGH for STM32MP13

Remove useless LSEDRV_MEDIUM_HIGH definition in clk-stm32mp13.c.
It's already defined in include/dt-bindings/clock/stm32mp13-clksrc.h.

Si

refactor(st-clock): remove LSEDRV_MEDIUM_HIGH for STM32MP13

Remove useless LSEDRV_MEDIUM_HIGH definition in clk-stm32mp13.c.
It's already defined in include/dt-bindings/clock/stm32mp13-clksrc.h.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Change-Id: Ie3fa4711930f922fa0733ba7c76d72ec9639e9a5

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fix(st-clock): display proper PLL number for STM32MP13

The PLL clk_id does not start at 0, but it is in the enum listing all
clocks. To have a better display of the PLL number, start at PLL1,
by cha

fix(st-clock): display proper PLL number for STM32MP13

The PLL clk_id does not start at 0, but it is in the enum listing all
clocks. To have a better display of the PLL number, start at PLL1,
by changing pll->clk_id in messages with pll->clk_id - _CK_PLL1 + 1.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ic09195ae6fe5f8d3a87e69962425f7c826f3670b

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fix(st-clock): do not reconfigure LSE

If LSE oscillator is already ON, which is the case when returning from
low-power state or if we are on VBAT, it mustn't be reconfigured.

Signed-off-by: Yann Ga

fix(st-clock): do not reconfigure LSE

If LSE oscillator is already ON, which is the case when returning from
low-power state or if we are on VBAT, it mustn't be reconfigured.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: Ie75f2b0b42aeb3d95e2266e1fca811a2f2b3e29f

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refactor(st-clock): remove unused clk function in API

Remove the unused functions in stm32mp clk API:
- stm32mp_stgen_get_counter (change to static, no more exported)
- stm32mp_stgen_restore_counter

refactor(st-clock): remove unused clk function in API

Remove the unused functions in stm32mp clk API:
- stm32mp_stgen_get_counter (change to static, no more exported)
- stm32mp_stgen_restore_counter

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ib6ca72723eac3e133f1ca0dee504ef344c72e0bf

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refactor(st-clock): support deactivated STGEN in stm32mp_stgen_config

Update function stm32mp_stgen_config() to support deactivated STGEN
when frequency is 0, for example on STOP2 exit for STM32MP25

refactor(st-clock): support deactivated STGEN in stm32mp_stgen_config

Update function stm32mp_stgen_config() to support deactivated STGEN
when frequency is 0, for example on STOP2 exit for STM32MP25.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Id371c4602a614bbfa0ecc7ce2d2e0ac5261e1d52

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feat(st-clock): add function to restore generic timer rate

Add a function to restore the CPU generic timer rate from STGEN content.
After wake-up from LPLV-Stop2, STGEN content is not lost, but gene

feat(st-clock): add function to restore generic timer rate

Add a function to restore the CPU generic timer rate from STGEN content.
After wake-up from LPLV-Stop2, STGEN content is not lost, but generic timer
has been reset.

Signed-off-by: Pascal Paillet <p.paillet@st.com>
Change-Id: I6f91dbd051f76383e9ff1d6bb86225d373dbf33a

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fix(rse): include lib-psa to resolve build

Unless platforms include lib/psa into platform specific makefile the
rse_comms throws build error on its own:
CC drivers/arm/rse/rse_comms_protocol.

fix(rse): include lib-psa to resolve build

Unless platforms include lib/psa into platform specific makefile the
rse_comms throws build error on its own:
CC drivers/arm/rse/rse_comms_protocol.c
drivers/arm/rse/rse_comms.c:13:10: fatal error: psa/client.h: No such file or directory
13 | #include <psa/client.h>

So add PLAT_INCLUDES entry to include the lib/psa to rse_comms.mk.

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
Change-Id: I4cbcbbaf20285990239d605f0b3b3dc92bea61e6

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refactor(auth): remove HW_CONFIG reference from BL1 CoT file

Remove the 'HW_CONFIG' reference from the BL1 CoT file, as BL1
does not play any role in loading the hw_config image. This
reference was

refactor(auth): remove HW_CONFIG reference from BL1 CoT file

Remove the 'HW_CONFIG' reference from the BL1 CoT file, as BL1
does not play any role in loading the hw_config image. This
reference was incorrectly added to the BL1 CoT file.

Change-Id: I9c1d9abce65844eaa1f41ab4f98d3c258ab7a8d2
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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fix(nxp-sfp): shift gpio register offsets by 2

These registers are 32-bit registers. When accessing them using
pointers, when should explicitely divide the fixed offsets
GPDIR_REG_OFFSET and GPDAT_R

fix(nxp-sfp): shift gpio register offsets by 2

These registers are 32-bit registers. When accessing them using
pointers, when should explicitely divide the fixed offsets
GPDIR_REG_OFFSET and GPDAT_REG_OFFSET by 4 to land on the correct
address. While set_gpio_bit() did this correctly, clr_gpio_bit() did
not. Even though GPDIR_REG_OFFSET = 0x0, shift it as well for
consistency with GPDAT_REG_OFFSET.

Change-Id: I5b8787d8424f83462ad4bb0f2141370ca28eaf34
Signed-off-by: Antonin Godard <antoningodard@pm.me>

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Merge changes from topic "ar/pmuSaveRestore" into integration

* changes:
feat(tc): add save/restore DSU PMU register support
feat(dsu): save/restore DSU PMU register
feat(plat): add platform A

Merge changes from topic "ar/pmuSaveRestore" into integration

* changes:
feat(tc): add save/restore DSU PMU register support
feat(dsu): save/restore DSU PMU register
feat(plat): add platform API that gets cluster ID

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feat(mbedtls): update config for 3.6.0

Further, remove reliance of mbedtls_md_psa_alg_from_type on
the actual values of the PSA_ALG_... defines.

And work around a prior bug that would try to import

feat(mbedtls): update config for 3.6.0

Further, remove reliance of mbedtls_md_psa_alg_from_type on
the actual values of the PSA_ALG_... defines.

And work around a prior bug that would try to import a
SubjectPublicKeyInfo into a PSA key. Instead, we import the
SubjectPublicKey itself.

Change-Id: Ib345b0bd4f2994f366629ed162d18814fd05aa2b
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

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feat(dsu): save/restore DSU PMU register

Adds driver support to preserve DSU PMU register values over a DSU
power cycle. This driver needs to be enabled by the platforms that
support DSU and also ne

feat(dsu): save/restore DSU PMU register

Adds driver support to preserve DSU PMU register values over a DSU
power cycle. This driver needs to be enabled by the platforms that
support DSU and also need it's PMU registers to be preserved

Change-Id: I7fc68a3d7d99ee369379aa5cd114fffc763fc0d2
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>

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Merge changes from topic "early_console" into integration

* changes:
feat(stm32mp2): use early traces
feat(st-bsec): use early traces
refactor(st): replace STM32MP_EARLY_CONSOLE with EARLY_CON

Merge changes from topic "early_console" into integration

* changes:
feat(stm32mp2): use early traces
feat(st-bsec): use early traces
refactor(st): replace STM32MP_EARLY_CONSOLE with EARLY_CONSOLE
feat(console): introduce EARLY_CONSOLE
feat(bl32): create an sp_min_setup function

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Merge changes from topic "add_s32g274ardb2_support" into integration

* changes:
feat(s32g274a): enable BL31 stage
feat(s32g274a): add S32G274ARDB2 board support
feat(nxp-drivers): add Linflex

Merge changes from topic "add_s32g274ardb2_support" into integration

* changes:
feat(s32g274a): enable BL31 stage
feat(s32g274a): add S32G274ARDB2 board support
feat(nxp-drivers): add Linflex driver

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refactor(cpufeat): add macro to simplify is_feat_xx_present

In this patch, we are trying to introduce the wrapper macro
CREATE_FEATURE_PRESENT to get the following capability and
align it for all th

refactor(cpufeat): add macro to simplify is_feat_xx_present

In this patch, we are trying to introduce the wrapper macro
CREATE_FEATURE_PRESENT to get the following capability and
align it for all the features:

-> is_feat_xx_present(): Does Hardware implement the feature.
-> uniformity in naming the function across multiple features.
-> improved readability

The is_feat_xx_present() is implemented to check if the hardware
implements the feature and does not take into account the
ENABLE_FEAT_XXX flag enabled/disabled in software.

- CREATE_FEATURE_PRESENT(name, idreg, shift, mask, idval)
The wrapper macro reduces the function to a single line and
creates the is_feat_xx_present function that checks the
id register based on the shift and mask values and compares
this against a determined idvalue.

Change-Id: I7b91d2c9c6fbe55f94c693aa1b2c50be54fb9ecc
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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feat(nxp-drivers): add Linflex driver

This is a UART controller found on NXP automotive parts.
For instance: S32V, S32G and S32R.

Change-Id: Iff0dd0c379633ac0651e5db287537c87666b57d2
Signed-off-by:

feat(nxp-drivers): add Linflex driver

This is a UART controller found on NXP automotive parts.
For instance: S32V, S32G and S32R.

Change-Id: Iff0dd0c379633ac0651e5db287537c87666b57d2
Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(st-bsec): use early traces

Replace trace macros with their corresponding EARLY_* macros.
Add some early traces in bsec2 driver.

Change-Id: I65e2feee6e7ba2524fb0a334557aa6e883672765
Signed-off-

feat(st-bsec): use early traces

Replace trace macros with their corresponding EARLY_* macros.
Add some early traces in bsec2 driver.

Change-Id: I65e2feee6e7ba2524fb0a334557aa6e883672765
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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refactor(measured-boot): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>

refactor(measured-boot): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I8c2fcbdf1de1c75f9969d28bc15e0b3500071404

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refactor(rse): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id

refactor(rse): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I9f72ad36ec233d7eaac3ce9e2f2b010130e1fa94

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refactor(measured-boot): rename all 'rss' files to 'rse'

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I3bd987456ad0f5c7a003960dd543efad2ce668a8

refactor(rss): rename all 'rss' files to 'rse'

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I6cfca1d67e246d5079f683241021ed039cc27f74

Merge "feat(rcar3): change CAM setting to improve bus latency of R-Car Gen3" into integration