feat(st-regulator): support regulator_set_voltage for fixed regulator

Always support the regulator_set_voltage operation for the same voltage.
This patch prepares the DDR power configuration when th

feat(st-regulator): support regulator_set_voltage for fixed regulator

Always support the regulator_set_voltage operation for the same voltage.
This patch prepares the DDR power configuration when the power supplies
are fixed.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Idf032b03c6f0c95f997dec3ed8a0d38c54a3de15

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feat(st-regulator): add enable ramp-delay

Permit to override enable ramp-delay value from
the device tree in BL2.

Change-Id: Id8e803b368055a50fbd14d4527917c449b958ad9
Signed-off-by: Pascal Paillet

feat(st-regulator): add enable ramp-delay

Permit to override enable ramp-delay value from
the device tree in BL2.

Change-Id: Id8e803b368055a50fbd14d4527917c449b958ad9
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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Merge changes from topic "mbedtls-config-cleanup" into integration

* changes:
chore(qemu): remove duplicate define
chore(imx): remove duplicate define
chore(arm): remove duplicate defines
ch

Merge changes from topic "mbedtls-config-cleanup" into integration

* changes:
chore(qemu): remove duplicate define
chore(imx): remove duplicate define
chore(arm): remove duplicate defines
chore(mbedtls): remove hash configs

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chore(mbedtls): remove hash configs

After the upgrade to mbedtls 3.6.0, some of these configuation limitations
are no longer present.

Size chages:
build config | executable | Delta
-------------|--

chore(mbedtls): remove hash configs

After the upgrade to mbedtls 3.6.0, some of these configuation limitations
are no longer present.

Size chages:
build config | executable | Delta
-------------|------------|-------
tbb ecdsa | bl1 | -176
-------------|------------|-------
tbb rsa | bl1 | -192
| bl2 | -4096
-------------|------------|-------
drtm | romlib | -576
-------------|------------|-------
spm | romlib | -576
-------------|------------|-------
mb384 | romlib | -1016

Change-Id: I019bc59adc93cf95f6f28ace9579e7bf1e785b62
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

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Merge "fix(rpi3): use correct define for GPIO reg_clr" into integration

Merge changes from topic "stm32mp2_bl2_updates" into integration

* changes:
feat(stm32mp2): load fw-config file
feat(stm32mp2): add fw-config compilation
feat(stm32mp2-fdts): add fw-config fil

Merge changes from topic "stm32mp2_bl2_updates" into integration

* changes:
feat(stm32mp2): load fw-config file
feat(stm32mp2): add fw-config compilation
feat(stm32mp2-fdts): add fw-config files for STM32MP257F-EV1
feat(stm32mp2-fdts): add fw-config file
feat(stm32mp2-fdts): add clock tree for STM32MP257F-EV1
feat(stm32mp2): enable DDR sub-system clock
feat(stm32mp2): add fixed regulators support
feat(stm32mp2): print board info
feat(stm32mp2): display CPU info
feat(stm32mp2): get chip ID
feat(stm32mp2): add BL2 boot first steps
feat(stm32mp2): add defines for the PWR peripheral
feat(stm32mp2-fdts): add SD-card and eMMC support on STM32MP257F-EV1
feat(stm32mp2-fdts): add sdmmc pins definition
feat(stm32mp2-fdts): add sdmmc nodes in SoC DT file
feat(stm32mp2-fdts): add io_policies
feat(stm32mp2-fdts): remove pins-are-numbered

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Merge changes from topic "nxp-drivers/add-linflex-clk" into integration

* changes:
feat(nxp-clk): enable UART clock
feat(nxp-clk): add PERIPH PLL enablement

fix(rpi3): use correct define for GPIO reg_clr

Changed reg_clr to use the base address + RPI3_GPIO_GPCLR,
this corrects the reg_clr address.

Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.

fix(rpi3): use correct define for GPIO reg_clr

Changed reg_clr to use the base address + RPI3_GPIO_GPCLR,
this corrects the reg_clr address.

Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com>
Signed-off-by: Abhi Singh <abhi.singh@arm.com>
Change-Id: I9ca50905efd4c640f143783c5a00676b246a2e26

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feat(nxp-clk): enable UART clock

Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz

feat(nxp-clk): enable UART clock

Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz by changing the clock source from FIRC to
PERIPH PLL PHI3.

Change-Id: I3160dc6860ebf441c9bea8eaf9d8d12de48bd647
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add PERIPH PLL enablement

Peripheral PLL is one of the platform's PLLs, providing a clock for
peripherals such as UART, QSPI, uSDHC, SPI and CAN. Its source can be
either the FIRC or

feat(nxp-clk): add PERIPH PLL enablement

Peripheral PLL is one of the platform's PLLs, providing a clock for
peripherals such as UART, QSPI, uSDHC, SPI and CAN. Its source can be
either the FIRC or FXOSC oscillators. It has eight outputs (PHIs) and
their frequencies can be controlled programmatically using output
dividers. An additional output clocks the PERIPH DFS using the VCO
frequency of the PERIPH PLL.

Change-Id: I637294b2da94f35e95dc1750dad36c129a276bb9
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-drivers): add Linflex flush callback

Implement a flush callback for the Linflex UART driver to avoid cases
where the BL31 stage reinitializes the console while there is ongoing TX
initiated

feat(nxp-drivers): add Linflex flush callback

Implement a flush callback for the Linflex UART driver to avoid cases
where the BL31 stage reinitializes the console while there is ongoing TX
initiated by the BL2.

Change-Id: Ic49852f809198362de1f993474c7c45f1439dc98
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge changes from topic "cot-dt2c" into integration

* changes:
feat(arm): update documentation for cot-dt2c
feat(arm): remove the bl2 static c file
feat(arm): generate tbbr c file CoT dt2c

Merge changes from topic "cot-dt2c" into integration

* changes:
feat(arm): update documentation for cot-dt2c
feat(arm): remove the bl2 static c file
feat(arm): generate tbbr c file CoT dt2c
feat(arm): makefile invoke CoT dt2c
feat(auth): standalone CoT dt2c tool
refactor(auth): separate bl1 and bl2 CoT
refactor(st): align the NV counter naming
refactor(fvp): align the NV counter naming

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fix(gicv3): wait rwp when gicr_ctrl.enablelpis from 1 to 0

Per GIC architecture version 3 and version 4, Where the GICR_CTRL.EnableLPIs
remains programmable:
- Software must observe GICR_CTLR.RWP==0

fix(gicv3): wait rwp when gicr_ctrl.enablelpis from 1 to 0

Per GIC architecture version 3 and version 4, Where the GICR_CTRL.EnableLPIs
remains programmable:
- Software must observe GICR_CTLR.RWP==0 after clearing GICR_CTLR.EnableLPIs
from 1 to 0 before writing GICR_PENDBASER or GICR_PROPBASER, otherwise
behavior is UNPREDICTABLE.
- Software must observe GICR_CTLR.RWP==0 after clearing GICR_CTLR.EnableLPIs
from 1 to 0 before setting GICR_CTLR.EnableLPIs to 1, otherwise behavior is
UNPREDICTABLE.

After changing EnableLPIs from 1 to 0, wait RWP got cleared, otherwise
setting EnableLPIs from 0 to 1 may fail.

Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Tested-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I6aaf96dc9984376de9399d0dac8a8504ba095149

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feat(stm32mp2): enable DDR sub-system clock

Create a DDR helper files, and add a function to enable DDR clocks
in RCC_DDRCPCFGR register.
Call this ddr_sub_system_clk_init() just before clock driver

feat(stm32mp2): enable DDR sub-system clock

Create a DDR helper files, and add a function to enable DDR clocks
in RCC_DDRCPCFGR register.
Call this ddr_sub_system_clk_init() just before clock driver init,
as it needs to be done before enabling DDR PLL clock (PLL2).

Change-Id: I365d6aa034363d0c036ce2d9f944f077ba86e193
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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Merge changes from topic "nxp-s32g2/add-xbar-clk" into integration

* changes:
feat(nxp-clk): enable the XBAR clock
feat(nxp-clk): add dependencies for the XBAR clock
feat(nxp-clk): add CGM0 in

Merge changes from topic "nxp-s32g2/add-xbar-clk" into integration

* changes:
feat(nxp-clk): enable the XBAR clock
feat(nxp-clk): add dependencies for the XBAR clock
feat(nxp-clk): add CGM0 instance
feat(nxp-clk): add DFS module enablement
feat(nxp-clk): add clock objects for ARM DFS
refactor(nxp-clk): organize early clocks in groups

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feat(nxp-clk): enable the XBAR clock

Enable the XBAR clock, which is the primary system clock.

Change-Id: Idaafbb8894472b10e1ed8a35b25967c82106e667
Signed-off-by: Ghennadi Procopciuc <ghennadi.proc

feat(nxp-clk): enable the XBAR clock

Enable the XBAR clock, which is the primary system clock.

Change-Id: Idaafbb8894472b10e1ed8a35b25967c82106e667
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add dependencies for the XBAR clock

Add all clock modules required to enable the XBAR clock, including the
DFS, its output dividers and MC_CGM muxes.

Change-Id: Ib9cf82c0e40b76863637

feat(nxp-clk): add dependencies for the XBAR clock

Add all clock modules required to enable the XBAR clock, including the
DFS, its output dividers and MC_CGM muxes.

Change-Id: Ib9cf82c0e40b76863637ed7602c3a09411d17615
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add CGM0 instance

Introduce the MC_CGM0 instance responsible for XBAR and other peripheral
clocks.

Change-Id: Icf1e9ce6e71e4ff446835d1e7b6522bfb6f2b4b6
Signed-off-by: Ghennadi Procop

feat(nxp-clk): add CGM0 instance

Introduce the MC_CGM0 instance responsible for XBAR and other peripheral
clocks.

Change-Id: Icf1e9ce6e71e4ff446835d1e7b6522bfb6f2b4b6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add DFS module enablement

Implement enable and set_module_rate callbacks for DFS modules.

Change-Id: Ic9d6034ac04adbabd8fc782aea94ce252439f136
Signed-off-by: Ghennadi Procopciuc <ghe

feat(nxp-clk): add DFS module enablement

Implement enable and set_module_rate callbacks for DFS modules.

Change-Id: Ic9d6034ac04adbabd8fc782aea94ce252439f136
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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Merge "fix(gicv3): incorrect impdef power down sequence" into integration

refactor(nxp-clk): organize early clocks in groups

This reduces the length of the s32cc_init_early_clks function and offers
space for more early clocks to be added.

Change-Id: I0d11b97779433a6b15cd

refactor(nxp-clk): organize early clocks in groups

This reduces the length of the s32cc_init_early_clks function and offers
space for more early clocks to be added.

Change-Id: I0d11b97779433a6b15cd76c36aefbb7b92381067
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(arm): remove the bl2 static c file

There is no need for the bl2 static c file for
CCA and Duaroot CoT, remove them from the repo

Change-Id: I251d085034dae0f6b3c6cefdbb129a9e1dd0530b
Signed-off

feat(arm): remove the bl2 static c file

There is no need for the bl2 static c file for
CCA and Duaroot CoT, remove them from the repo

Change-Id: I251d085034dae0f6b3c6cefdbb129a9e1dd0530b
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>

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refactor(auth): separate bl1 and bl2 CoT

Separate the bl1 and bl2 CoT into individual C files for the
upcoming tool, i.e. the CoT device tree-to-source file generator.

Change-Id: I0d24791991b3539c7

refactor(auth): separate bl1 and bl2 CoT

Separate the bl1 and bl2 CoT into individual C files for the
upcoming tool, i.e. the CoT device tree-to-source file generator.

Change-Id: I0d24791991b3539c7aef9a562920dc62fecdc69a
Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>

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Merge changes from topic "enable_a53_clk" into integration

* changes:
feat(nxp-clk): enable the A53 clock
feat(nxp-clk): add ARM PLL ODIV enablement
feat(nxp-clk): add ARM PLL enablement
fea

Merge changes from topic "enable_a53_clk" into integration

* changes:
feat(nxp-clk): enable the A53 clock
feat(nxp-clk): add ARM PLL ODIV enablement
feat(nxp-clk): add ARM PLL enablement
feat(nxp-clk): set rate for clock muxes

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Merge "fix(nxp-sfp): shift gpio register offsets by 2" into integration