Merge changes from topic "jw/gic-lca-support" into integration

* changes:
fix(rdn2): add LCA multichip data for RD-N2-Cfg2
fix(rdv3): add LCA multichip data for RD-V3-Cfg2
feat(gic): add suppo

Merge changes from topic "jw/gic-lca-support" into integration

* changes:
fix(rdn2): add LCA multichip data for RD-N2-Cfg2
fix(rdv3): add LCA multichip data for RD-V3-Cfg2
feat(gic): add support for local chip addressing

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feat(s32g274a): enable sdhc clock

The uSDHC module clock must be enabled to use the SD/eMMC storage from
where the BL2 is expected to load images for the next boot stages.

Change-Id: Ib1cc7d5dda7a4

feat(s32g274a): enable sdhc clock

The uSDHC module clock must be enabled to use the SD/eMMC storage from
where the BL2 is expected to load images for the next boot stages.

Change-Id: Ib1cc7d5dda7a4283a29716f5b3d776048bd5b7ba
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add clock modules for uSDHC

One of the uSDHC module's clock lines is attached to the CGM_MUX 14
divider, which is connected to PERIPH_DFS3. The other one is attached
to XBAR_DIV3.

feat(nxp-clk): add clock modules for uSDHC

One of the uSDHC module's clock lines is attached to the CGM_MUX 14
divider, which is connected to PERIPH_DFS3. The other one is attached
to XBAR_DIV3.

Change-Id: I23f468a3e5f7daa832c0841b55211a048284a7f0
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): get MC_CGM divider's parent

The parent of the MC_CGM divider will always be the MC_CGM mux
identified based on s32cc_cgm_div.parent.

Change-Id: Ie13b16e0ee56f35d61374efbe158f166b9996

feat(nxp-clk): get MC_CGM divider's parent

The parent of the MC_CGM divider will always be the MC_CGM mux
identified based on s32cc_cgm_div.parent.

Change-Id: Ie13b16e0ee56f35d61374efbe158f166b99960b7
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): get MC_CGM divider's rate

The MC_CGM divider's frequency is obtained based on the state of the
settings found in its registers. If the divider is disabled, the
intended rate (s32cc_cg

feat(nxp-clk): get MC_CGM divider's rate

The MC_CGM divider's frequency is obtained based on the state of the
settings found in its registers. If the divider is disabled, the
intended rate (s32cc_cgm_div.freq) will be returned.

Change-Id: I41698990952b530021de26eb51f74aca50176575
Co-developed-by: Florin Buica <florin.buica@nxp.com>
Signed-off-by: Florin Buica <florin.buica@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): set MC_CGM divider's rate

The MC_CGM divider's frequency is saved as part of the object metadata.
No checks are performed on the requested frequency. It will be validated
during the e

feat(nxp-clk): set MC_CGM divider's rate

The MC_CGM divider's frequency is saved as part of the object metadata.
No checks are performed on the requested frequency. It will be validated
during the enablement process.

Change-Id: Ide9c8c64be16a66b66f129735cebfc4d1f1772c5
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): enable MC_CGM dividers

Add the enablement mechanism for the MC_CGM dividers. The division
factor is established by dividing the parent's rate by the rate of the
divider's output.

Cha

feat(nxp-clk): enable MC_CGM dividers

Add the enablement mechanism for the MC_CGM dividers. The division
factor is established by dividing the parent's rate by the rate of the
divider's output.

Change-Id: Iadb84f4f47531a67b0b1509b94e1f2b962631a77
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): get parent for the fixed dividers

Fixed dividers contribute to the Linflex and QSPI clocks.

Change-Id: Idb4e6fe883e117b2bb9260b6eeb6e15d75ce887e
Signed-off-by: Ghennadi Procopciuc <g

feat(nxp-clk): get parent for the fixed dividers

Fixed dividers contribute to the Linflex and QSPI clocks.

Change-Id: Idb4e6fe883e117b2bb9260b6eeb6e15d75ce887e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): set the rate for partition objects

Only the partition block link can set the frequency, while the other two
should not be able to because none of them participate in the clock
generat

feat(nxp-clk): set the rate for partition objects

Only the partition block link can set the frequency, while the other two
should not be able to because none of them participate in the clock
generation. In the first case, the request will be propagated to the
parent object of the partition link.

Change-Id: Ic237972008eb51c62e92f03f657698a8a1ca4b0e
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add clock objects for CGM dividers

The CGM dividers are controllable dividers attached to a CGM mux. Its
divison factor can be controlled through the MC_CGM's registers.

Change-Id: I

feat(nxp-clk): add clock objects for CGM dividers

The CGM dividers are controllable dividers attached to a CGM mux. Its
divison factor can be controlled through the MC_CGM's registers.

Change-Id: Id2786a46c5a1d389ca32a4839c7158949aec3b0a
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add base address for PERIPH_DFS

The PERIPH_DFS module is used to clock the SD and QSPI modules.

Change-Id: I440fd806d71acab641f0003a7f2a5ce720b469c6
Signed-off-by: Ghennadi Procopciu

feat(nxp-clk): add base address for PERIPH_DFS

The PERIPH_DFS module is used to clock the SD and QSPI modules.

Change-Id: I440fd806d71acab641f0003a7f2a5ce720b469c6
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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refactor(rse)!: remove rse_comms_init

The function to use is now rse_mbx_init(), that does the same if
using MHU.

Change-Id: I712712d7d1bcd8c96d26951e176b877afb65209d
Signed-off-by: Yann Gautier <y

refactor(rse)!: remove rse_comms_init

The function to use is now rse_mbx_init(), that does the same if
using MHU.

Change-Id: I712712d7d1bcd8c96d26951e176b877afb65209d
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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refactor(rse): put MHU code in a dedicated file

To be able to use RSE comms without MHU, a first step is to disentangle
the rse_comms.c file with MHU code direct calls. This is done with the
creatio

refactor(rse): put MHU code in a dedicated file

To be able to use RSE comms without MHU, a first step is to disentangle
the rse_comms.c file with MHU code direct calls. This is done with the
creation of a new file rse_comms_mhu.c. New APIs are created to
initialize the mailbox, get max message size and send and receive data.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I75dda77e1886beaa6ced6f92c311617125918cfa

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refactor(arm)!: rename PLAT_MHU_VERSION flag

In order to support a platform without MHU in RSE, update the flag
PLAT_MHU_VERSION. It is renamed PLAT_MHU and can take the following
entries: NO_MHU, M

refactor(arm)!: rename PLAT_MHU_VERSION flag

In order to support a platform without MHU in RSE, update the flag
PLAT_MHU_VERSION. It is renamed PLAT_MHU and can take the following
entries: NO_MHU, MHUv1, MHUv2, MHUv3...

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ia72e590088ce62ba8c9009f341b6135926947bee

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Merge changes I765a7fa0,Ic33f0b6d,I8d1a88c7,I381f96be,I698fa849, ... into integration

* changes:
fix(cpus): clear CPUPWRCTLR_EL1.CORE_PWRDN_EN_BIT on reset
chore(docs): drop the "wfi" from `pwr_

Merge changes I765a7fa0,Ic33f0b6d,I8d1a88c7,I381f96be,I698fa849, ... into integration

* changes:
fix(cpus): clear CPUPWRCTLR_EL1.CORE_PWRDN_EN_BIT on reset
chore(docs): drop the "wfi" from `pwr_domain_pwr_down_wfi`
chore(psci): drop skip_wfi variable
feat(arm): convert arm platforms to expect a wakeup
fix(cpus): avoid SME related loss of context on powerdown
feat(psci): allow cores to wake up from powerdown
refactor: panic after calling psci_power_down_wfi()
refactor(cpus): undo errata mitigations
feat(cpus): add sysreg_bit_toggle

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Merge changes from topic "nxp-clk/add_get_rate" into integration

* changes:
feat(nxp-clk): restore pll output dividers rate
feat(nxp-clk): get pll rate using get_module_rate
feat(nxp-clk): add

Merge changes from topic "nxp-clk/add_get_rate" into integration

* changes:
feat(nxp-clk): restore pll output dividers rate
feat(nxp-clk): get pll rate using get_module_rate
feat(nxp-clk): add get_rate for partition objects
feat(nxp-clk): add get_rate for clock muxes
feat(nxp-clk): add get_rate for s32cc_pll_out_div
feat(nxp-clk): add get_rate for s32cc_fixed_div
feat(nxp-clk): add get_rate for s32cc_dfs_div
feat(nxp-clk): add get_rate for s32cc_dfs
feat(nxp-clk): add get_rate for s32cc_pll
feat(nxp-clk): add get_rate for s32cc_clk
feat(nxp-clk): add a basic get_rate implementation

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feat(arm): convert arm platforms to expect a wakeup

Newer cores in upcoming platforms may refuse to power down. The PSCI
library is already prepared for this so convert platform code to also
allow t

feat(arm): convert arm platforms to expect a wakeup

Newer cores in upcoming platforms may refuse to power down. The PSCI
library is already prepared for this so convert platform code to also
allow this. This is simple - drop the `wfi` + panic and let common code
deal with the fallout. The end result will be the same (sans the
message) except the platform will have fewer responsibilities. The only
exception is for cores being signalled to power off gracefully ahead of
system reset. That path must also be terminal so replace the end with
the same psci_pwrdown_cpu_end() to behave the same as the generic
implementation. It will handle wakeups and panic, hoping that the system
gets reset from under it. The dmb is upgraded to a dsb so no functional
change.

Change-Id: I381f96bec8532bda6ccdac65de57971aac42e7e8
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(psci): allow cores to wake up from powerdown

The simplistic view of a core's powerdown sequence is that power is
atomically cut upon calling `wfi`. However, it turns out that it has
lots to do

feat(psci): allow cores to wake up from powerdown

The simplistic view of a core's powerdown sequence is that power is
atomically cut upon calling `wfi`. However, it turns out that it has
lots to do - it has to talk to the interconnect to exit coherency, clean
caches, check for RAS errors, etc. These take significant amounts of
time and are certainly not atomic. As such there is a significant window
of opportunity for external events to happen. Many of these steps are
not destructive to context, so theoretically, the core can just "give
up" half way (or roll certain actions back) and carry on running. The
point in this sequence after which roll back is not possible is called
the point of no return.

One of these actions is the checking for RAS errors. It is possible for
one to happen during this lengthy sequence, or at least remain
undiscovered until that point. If the core were to continue powerdown
when that happens, there would be no (easy) way to inform anyone about
it. Rejecting the powerdown and letting software handle the error is the
best way to implement this.

Arm cores since at least the a510 have included this exact feature. So
far it hasn't been deemed necessary to account for it in firmware due to
the low likelihood of this happening. However, events like GIC wakeup
requests are much more probable. Older cores will powerdown and
immediately power back up when this happens. Travis and Gelas include a
feature similar to the RAS case above, called powerdown abandon. The
idea is that this will improve the latency to service the interrupt by
saving on work which the core and software need to do.

So far firmware has relied on the `wfi` being the point of no return and
if it doesn't explicitly detect a pending interrupt quite early on, it
will embark onto a sequence that it expects to end with shutdown. To
accommodate for it not being a point of no return, we must undo all of
the system management we did, just like in the warm boot entrypoint.

To achieve that, the pwr_domain_pwr_down_wfi hook must not be terminal.
Most recent platforms do some platform management and finish on the
standard `wfi`, followed by a panic or an endless loop as this is
expected to not return. To make this generic, any platform that wishes
to support wakeups must instead let common code call
`psci_power_down_wfi()` right after. Besides wakeups, this lets common
code handle powerdown errata better as well.

Then, the CPU_OFF case is simple - PSCI does not allow it to return. So
the best that can be done is to attempt the `wfi` a few times (the
choice of 32 is arbitrary) in the hope that the wakeup is transient. If
it isn't, the only choice is to panic, as the system is likely to be in
a bad state, eg. interrupts weren't routed away. The same applies for
SYSTEM_OFF, SYSTEM_RESET, and SYSTEM_RESET2. There the panic won't
matter as the system is going offline one way or another. The RAS case
will be considered in a separate patch.

Now, the CPU_SUSPEND case is more involved. First, to powerdown it must
wipe its context as it is not written on warm boot. But it cannot be
overwritten in case of a wakeup. To avoid the catch 22, save a copy that
will only be used if powerdown fails. That is about 500 bytes on the
stack so it hopefully doesn't tip anyone over any limits. In future that
can be avoided by having a core manage its own context.

Second, when the core wakes up, it must undo anything it did to prepare
for poweroff, which for the cores we care about, is writing
CPUPWRCTLR_EL1.CORE_PWRDN_EN. The least intrusive for the cpu library
way of doing this is to simply call the power off hook again and have
the hook toggle the bit. If in the future there need to be more complex
sequences, their direction can be advised on the value of this bit.

Third, do the actual "resume". Most of the logic is already there for
the retention suspend, so that only needs a small touch up to apply to
the powerdown case as well. The missing bit is the powerdown specific
state management. Luckily, the warmboot entrypoint does exactly that
already too, so steal that and we're done.

All of this is hidden behind a FEAT_PABANDON flag since it has a large
memory and runtime cost that we don't want to burden non pabandon cores
with.

Finally, do some function renaming to better reflect their purpose and
make names a little bit more consistent.

Change-Id: I2405b59300c2e24ce02e266f91b7c51474c1145f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(gicv3): do not assume redistributors are powered down" into integration

feat(gic): add support for local chip addressing

This patch adds support for Local Chip Addressing (LCA). In a multi-chip
system, enablig LCA allows each GIC Distributor to maintain its own
version

feat(gic): add support for local chip addressing

This patch adds support for Local Chip Addressing (LCA). In a multi-chip
system, enablig LCA allows each GIC Distributor to maintain its own
version of routing table. This feature is activated when the
GICD_CFGID.LCA bit is set to 1.

The existing `gic600_multichip_data` data structure did not account for
the LCA feature. To support LCA:
- `rt_owner_base` is replaced by `base_addrs[]`. This is required
because each GICD in the system needs to be configured independently,
and their base addresses must be passed to the driver.
- `chip_addrs` is changed from 1D to 2D array to store the routing table
for each chip's GICD. The entries in `chip_addrs` are configuration
dependent, as the GIC specification does not enforce this.

On a multi-chip platform with chip count N where LCA is enabled by
default, the `gic600_multichip_data` structure should contain all copies
of the routing table (N*N entries). On platforms where LCA is not
supported, only the first sub-array with N entries is required. The
function signature of `gic600_multichip_init` remains unchanged, but if
the LCA feature is enabled, the driver will expect the routing table
configuration in the described format.

Change-Id: I8830c2cf90db6a0cae78e99914cd32c637284a2b
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>

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feat(nxp-clk): restore pll output dividers rate

Reconfiguration of the PLL may be requested while some output dividers
are already enabled. To prevent setting a different frequency for these
enabled

feat(nxp-clk): restore pll output dividers rate

Reconfiguration of the PLL may be requested while some output dividers
are already enabled. To prevent setting a different frequency for these
enabled dividers, the driver will attempt to adjust the division factor
to achieve the initially requested rate.

Change-Id: I7800c05b2f21bbdeda243db865942b647983687d
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): get pll rate using get_module_rate

The DFS can use the get_module_rate instead of assuming its parent
object is a PLL. It also has the advantage that the frequency will be
returned ba

feat(nxp-clk): get pll rate using get_module_rate

The DFS can use the get_module_rate instead of assuming its parent
object is a PLL. It also has the advantage that the frequency will be
returned based on the hardware state of the PLL module.

Change-Id: I3a270cbc92622ae82606382df1301597dc29782a
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for partition objects

The partition-related objects do not participate in clock rate
calculation, except the s32cc_part_block_link_t, whose call is forwarded
to the paren

feat(nxp-clk): add get_rate for partition objects

The partition-related objects do not participate in clock rate
calculation, except the s32cc_part_block_link_t, whose call is forwarded
to the parent object.

Change-Id: Id9e7fa49c3c1fb5b30b4c1b97fc8441bc967578a
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for clock muxes

From the get rate callback perspective, all types of clock muxes should
return the frequency of the selected source, regardless of whether it is
an MC_CGM

feat(nxp-clk): add get_rate for clock muxes

From the get rate callback perspective, all types of clock muxes should
return the frequency of the selected source, regardless of whether it is
an MC_CGM or PLL mux.

Change-Id: I24ae821013b0844e4d62793fde12b53b043a9776
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-clk): add get_rate for s32cc_pll_out_div

The get rate callback is needed for s32cc_pll_out_div to get the A53
cores and DDR rate.

Change-Id: Ife7860c9941e819b612d7948dac9843bdf0c31c4
Signe

feat(nxp-clk): add get_rate for s32cc_pll_out_div

The get rate callback is needed for s32cc_pll_out_div to get the A53
cores and DDR rate.

Change-Id: Ife7860c9941e819b612d7948dac9843bdf0c31c4
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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