feat(gicv5): assign interrupt sources to appropriate security states

Assign the PPI interrupts we commonly have in the device tree to the NS
domain. This is a short-term solution that allows Linux t

feat(gicv5): assign interrupt sources to appropriate security states

Assign the PPI interrupts we commonly have in the device tree to the NS
domain. This is a short-term solution that allows Linux to fully boot.
This is expected to be fully replaced with context management when
adding world switching support as some of these are expected to be
shared between worlds.

Change-Id: I59a7b5a63f878c9a717ef81e977be7133a402f3f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(gicv5): add a barebones GICv5 driver

This is the absolute minimum that's needed to compile an NS-only build
end exit out of EL3. The GIC is not used and/or configured in any way
but all the nec

feat(gicv5): add a barebones GICv5 driver

This is the absolute minimum that's needed to compile an NS-only build
end exit out of EL3. The GIC is not used and/or configured in any way
but all the necessary hooks are populated.

Notably, SCR_EL3.FIQ becomes RES1 as GICv5 behaves in a similar manner
to a GICv3 with FIQ set.

Change-Id: Idae52b9df97f4ca2996b2dcd1e5efc45478a43f2
Co-developed-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(gicv5): add support for building with gicv5

The Generic Interrupt Controller v5 (GICv5) is the next generation of
Arm interrupt controllers. It is a clean slate design and has native
support fo

feat(gicv5): add support for building with gicv5

The Generic Interrupt Controller v5 (GICv5) is the next generation of
Arm interrupt controllers. It is a clean slate design and has native
support for the latest Armv9 features. As such it is entirely backwards
incompatible with GICv3/v4.

This patch adds the necessary boilerplate to select a build with GICv5.
The GIC has always had two parts. BL31 deals directly with the CPU
interface while platform code is responsible for managing the IRI. In v5
this split is formalised and the CPU interface, FEAT_GCIE, may be
implemented on its own. So reflect this split in our code with
ENABLE_FEAT_GCIE which only affects BL31 and the GICv5 IRI lies in the
generic GIC driver.

No actual functionality yet.

Change-Id: I97a0c3ba708877c213e50e7ef148e3412aa2af90
Co-developed-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(nxp-crypto): restricts generating nxp_mkvb via ns-world

Master-key-verification-blob (MKVB) value generated on request from
the secure world, is same to the MKVB value generated on request from

fix(nxp-crypto): restricts generating nxp_mkvb via ns-world

Master-key-verification-blob (MKVB) value generated on request from
the secure world, is same to the MKVB value generated on request from
Normal world. Leading to the leak og MKVB to non-secure world.

Fix to prevent MKVB generation for requests originating from non-secure
world.
- For non-secure world, this SMC is return failure.

Additional fix for bound-check before continuing to generate the MKVB.

Change-Id: I9940b4dfe33289c2d57595a2a08acff29a12c974
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>

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fix(console): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a

fix(console): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
Variable type has been updated from uint8_t to uint32_t to avoid
assigning a value to an object with a narrower essential type.

Change-Id: I2c901eb837a3042b5a097b3c7b516bb6cd813289
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(console): typecast operands to match data type

This corrects the MISRA violation C2012-10.1:
Operands shall not be of an inappropriate essential type.
The condition is explicitly checked against

fix(console): typecast operands to match data type

This corrects the MISRA violation C2012-10.1:
Operands shall not be of an inappropriate essential type.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: Ie78d91f0f79804797648ef996fb208d3ee1698dd
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge changes I6422cd05,Idd01179d,I5c557616,I343a46d6,Id48671ae, ... into integration

* changes:
feat(st-clock): add STM32MP21 and STM32MP23 RCC variants
feat(stm32mp21): add RCC registers file

Merge changes I6422cd05,Idd01179d,I5c557616,I343a46d6,Id48671ae, ... into integration

* changes:
feat(st-clock): add STM32MP21 and STM32MP23 RCC variants
feat(stm32mp21): add RCC registers file
feat(stm32mp21): add clock and reset bindings
refactor(stm32mp2): update display of reset reason
feat(stm32mp25): add RCC register to display all IWDG flags
feat(stm32mp21): add PWR registers file
feat(st): introduce SoC family compilation switch
docs(changelog): add subsections for STM32MP2
docs(stm32mp2): introduce new STM32MP23 family
docs(stm32mp2): introduce new STM32MP21 family

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Merge changes from topic "nxp-mmc/fixes" into integration

* changes:
feat(nxp-mmc): add dynamic mapping
fix(nxp-mmc): wait SDSTB before changing the clock
fix(nxp-mmc): fix the clock rate calc

Merge changes from topic "nxp-mmc/fixes" into integration

* changes:
feat(nxp-mmc): add dynamic mapping
fix(nxp-mmc): wait SDSTB before changing the clock
fix(nxp-mmc): fix the clock rate calculation
fix(nxp-mmc): remove unnecessary delay
feat(nxp-mmc): flush and invalidate buffers
feat(nxp-mmc): add data buffer
refactor(nxp-mmc): check multi block transfer
refactor(nxp-mmc): set MIXCTRL_DTDSEL
refactor(nxp-mmc): populate command transfer type
fix(nxp-mmc): fix clk_rate and bus_width type
fix(nxp-mmc): correct the usage of BIT and GENMASK
docs(changelog): add subsection for uSDHC

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feat(st-clock): add STM32MP21 and STM32MP23 RCC variants

Add specific configurations in clock driver for STM32MP21 and STM32MP23
SoCs.
All changes have been merged in stm32mp2_clk.c file using STM32

feat(st-clock): add STM32MP21 and STM32MP23 RCC variants

Add specific configurations in clock driver for STM32MP21 and STM32MP23
SoCs.
All changes have been merged in stm32mp2_clk.c file using STM32MP21,
STM32MP23 and STM32MP25 flags.
STM32MP23 will use the same RCC clock compatible of STM32MP25 SoC.

Change-Id: I6422cd0553067dc92f80da1ad8ec78cadf2432bb
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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feat(st): introduce SoC family compilation switch

add STM32MP1X and STM3MP2X compilation switch to replace
#if STM32MP21 || STM32MP23 || STM32MP25 for MP2 SoCs and
#if STM32MP13 || STM32MP15 for MP1

feat(st): introduce SoC family compilation switch

add STM32MP1X and STM3MP2X compilation switch to replace
#if STM32MP21 || STM32MP23 || STM32MP25 for MP2 SoCs and
#if STM32MP13 || STM32MP15 for MP1 SoCs.

This will avoid to forget to modify all these files when a new SoC is
introduced.

Change-Id: Ib984b22a19e08af5bc1b62fe2032f10240ec9122
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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fix(mhu): shift by minor revision offset

Fix version check in mhu_v3_x_driver_init swapping
MHU_ARCH_MINOR_REV_MASK by MHU_ARCH_MINOR_REV_OFF as hinted by coverity:

(1) Event result_independent_of_

fix(mhu): shift by minor revision offset

Fix version check in mhu_v3_x_driver_init swapping
MHU_ARCH_MINOR_REV_MASK by MHU_ARCH_MINOR_REV_OFF as hinted by coverity:

(1) Event result_independent_of_operands:
"(aidr & (15U /* 0xfU << 0U */)) >> (15U /* 0xfU << 0U */)" is 0
regardless of the values of its operands. This occurs as the operand
of assignment.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I4307ae0fdc48831dade983a040671730369377ff

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fix(nxp): driver crypto caam

Fix based on code review. Then, it was checked with NXP Flexbuild and
their fix has been imported.

Change-Id: Icae1fb08b07bca5d4f6771e92b48d9e2071da0ee
Signed-off-by: V

fix(nxp): driver crypto caam

Fix based on code review. Then, it was checked with NXP Flexbuild and
their fix has been imported.

Change-Id: Icae1fb08b07bca5d4f6771e92b48d9e2071da0ee
Signed-off-by: Vincent Jardin <vjardin@free.fr>

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fix(st-iwdg): remove num_irq

Remove the unused field num_irq in stm32_iwdg_instance struct.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ifa7ae53d41ac654173b78226e3ed11

fix(st-iwdg): remove num_irq

Remove the unused field num_irq in stm32_iwdg_instance struct.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ifa7ae53d41ac654173b78226e3ed11d812430fa4

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fix(st-drivers): remove useless field in fixed regul

Cleanup useless structure fields in order to
reduce code size.

Change-Id: Ifb1df2d347c3d892d6633b339fa0bae648c87537
Signed-off-by: Pascal Paille

fix(st-drivers): remove useless field in fixed regul

Cleanup useless structure fields in order to
reduce code size.

Change-Id: Ifb1df2d347c3d892d6633b339fa0bae648c87537
Signed-off-by: Pascal Paillet <p.paillet@st.com>

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fix(st-bsec): remove useless defines in BSEC3

Remove some useles defines and structure in BSEC3 driver.

Change-Id: Ieef147948e9beba776a4d10746ffc730e6faff25
Signed-off-by: Yann Gautier <yann.gautie

fix(st-bsec): remove useless defines in BSEC3

Remove some useles defines and structure in BSEC3 driver.

Change-Id: Ieef147948e9beba776a4d10746ffc730e6faff25
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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fix(st-bsec): rename OTPSR field

Update the bit name in BSEC_OTPSR, align with the last ref manual.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I3b270406749f2f80d0d224

fix(st-bsec): rename OTPSR field

Update the bit name in BSEC_OTPSR, align with the last ref manual.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I3b270406749f2f80d0d2242bdf368d98d419d798

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fix(st-crypto): do not set IPRST if BUSY flag is present

An issue appear when a IPRST is set when BUSY flag is still set.
Put the IP reset under condition solve this issue.

Signed-off-by: Maxime Mé

fix(st-crypto): do not set IPRST if BUSY flag is present

An issue appear when a IPRST is set when BUSY flag is still set.
Put the IP reset under condition solve this issue.

Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Ibb096c1a362b8077285812e1ffca749c7fc93a03

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fix(st-ddr): bad refresh update level toggle sequence

wait_refresh_update_done_ack() must toggle RFSHCTL3_REFRESH_UPDATE_LEVEL
bit at each call to follow the recommended procedure.
Fix action and lo

fix(st-ddr): bad refresh update level toggle sequence

wait_refresh_update_done_ack() must toggle RFSHCTL3_REFRESH_UPDATE_LEVEL
bit at each call to follow the recommended procedure.
Fix action and loop condition.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: Iacf1e92a1ddaf2ab10e4f3a873be6ad1d3576e5f

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fix(st-ddr): remove TODO in STM32MP2 driver

Remove useless ddr_get_io_calibration_val service.
Other items are deleted as they're useless on STM32MP2 series.

Signed-off-by: Nicolas Le Bayon <nicola

fix(st-ddr): remove TODO in STM32MP2 driver

Remove useless ddr_get_io_calibration_val service.
Other items are deleted as they're useless on STM32MP2 series.

Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@foss.st.com>
Change-Id: I30bb18f156ff6dc06147987654363472a1e0182d

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feat(nxp-mmc): add dynamic mapping

Dynamically add an MMU entry for the uSDHC controller.

Change-Id: Ifd21fcee79392a1432aa7444aec168105a95a002
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciu

feat(nxp-mmc): add dynamic mapping

Dynamically add an MMU entry for the uSDHC controller.

Change-Id: Ifd21fcee79392a1432aa7444aec168105a95a002
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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fix(nxp-mmc): wait SDSTB before changing the clock

According to the reference manual, the host driver must ensure that the
SDSTB field is high before changing the clock divisor value (SDCLKFS or
DVS

fix(nxp-mmc): wait SDSTB before changing the clock

According to the reference manual, the host driver must ensure that the
SDSTB field is high before changing the clock divisor value (SDCLKFS or
DVS).

Change-Id: I3c89df707a825ccb5e5125b52e2d321b659bbb3f
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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fix(nxp-mmc): fix the clock rate calculation

Based on the reference manual's description of SYS_CTRL.SDCLKFS and
SYS_CTRL.DVS, the clock rate can be adjusted using a two-stage divider.
The value of

fix(nxp-mmc): fix the clock rate calculation

Based on the reference manual's description of SYS_CTRL.SDCLKFS and
SYS_CTRL.DVS, the clock rate can be adjusted using a two-stage divider.
The value of SYS_CTRL.DVS should be set considering the value of
SYS_CTRL.SDCLKFS (pre_div). Consequently, the resulting clock rate is
calculated as input_rate / (SYS_CTRL.SDCLKFS * SYS_CTRL.DVS).

Change-Id: I65a5372b8baf9def97e612ee29f99202c0fdc579
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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fix(nxp-mmc): remove unnecessary delay

There are no references in the reference manual indicating a required
delay after resetting INTSIGEN. Therefore, it is safe to remove this
step.

Change-Id: Ia

fix(nxp-mmc): remove unnecessary delay

There are no references in the reference manual indicating a required
delay after resetting INTSIGEN. Therefore, it is safe to remove this
step.

Change-Id: Ia748cfeb8f4a0f619480ef59451df90f85f69fa8
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-mmc): flush and invalidate buffers

When the uSDHC driver is used with enabled caches on the core setting
the transfer, the caches associated with the memory region used for data
transfer mu

feat(nxp-mmc): flush and invalidate buffers

When the uSDHC driver is used with enabled caches on the core setting
the transfer, the caches associated with the memory region used for data
transfer must be invalidated before reading from the buffer and flushed
before the buffer is passed to the controller.

Change-Id: I8213f120b655146772306ef57ee8204596fb05e9
Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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feat(nxp-mmc): add data buffer

The prepare callback is used to set buffer details for a transfer. The
actual transfer may not occur immediately. Therefore, the details are
saved and applied to the n

feat(nxp-mmc): add data buffer

The prepare callback is used to set buffer details for a transfer. The
actual transfer may not occur immediately. Therefore, the details are
saved and applied to the next data transfer command. This mechanism also
helps distinguish between single and multi-block transfers based on the
transfer size.

Change-Id: I7bcfde0521ad628e5950dfc71482191ac35433d1
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

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