| c6d9fdbc | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp: i2c driver support.
NXP I2C driver support for NXP SoC(s).
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I234b76f9fa1b30dd13aa0870014
nxp: i2c driver support.
NXP I2C driver support for NXP SoC(s).
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I234b76f9fa1b30dd13aa087001411370cc6c8dd0
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|
| d8e97999 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
NXP: Driver for NXP Security Monitor
NXP Security Monitor IP provides hardware anchored
- current security state of the SoC.
- Tamper detect etc.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com
NXP: Driver for NXP Security Monitor
NXP Security Monitor IP provides hardware anchored
- current security state of the SoC.
- Tamper detect etc.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I8ff809fe2f3fd013844ab3d4a8733f53c2b06c81
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|
| 3979c6d9 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
NXP: SFP driver support for NXP SoC
NXP Security Fuse Processor is used to read and write
fuses.
- Fuses once written, are cannot be un-done.
- Used as trust anchor for monotonic counter,
differen
NXP: SFP driver support for NXP SoC
NXP Security Fuse Processor is used to read and write
fuses.
- Fuses once written, are cannot be un-done.
- Used as trust anchor for monotonic counter,
different platform keys etc.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I347e806dd87078150fbbbfc28355bb44d9eacb9c
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|
| 76f735fd | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
NXP: Interconnect API based on ARM CCN-CCI driver
CCN API(s) to be used NXP SoC(s) are added.
These API(s) based on ARM CCN driver
- driver/arm/ccn
CCI API(s) to be used NXP SoC(s) are added.
These
NXP: Interconnect API based on ARM CCN-CCI driver
CCN API(s) to be used NXP SoC(s) are added.
These API(s) based on ARM CCN driver
- driver/arm/ccn
CCI API(s) to be used NXP SoC(s) are added.
These API(s) based on ARM CCI driver
- driver/arm/cci
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I7682c4c9bd42f63542b3ffd3cb6c5d2effe4ae0a
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|
| de0b1012 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
NXP: TZC API to configure ddr region
NXP TZC-400 API(s) to configure ddr regions are based on:
- drivers/arm/tzc
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I524433ff9fafe1170b13e
NXP: TZC API to configure ddr region
NXP TZC-400 API(s) to configure ddr regions are based on:
- drivers/arm/tzc
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I524433ff9fafe1170b13e99b7de01fe957b6d305
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|
| 447a42e7 | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
NXP: Timer API added to enable ARM generic timer
NXP Timer Apis are based on:
- drivers/delay_timer
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I2cbccf4c082a10affee1143390905b9cc9
NXP: Timer API added to enable ARM generic timer
NXP Timer Apis are based on:
- drivers/delay_timer
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I2cbccf4c082a10affee1143390905b9cc99c3382
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|
| 86b1b89f | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp: add dcfg driver
NXP SoC needs Device Configuration driver to
fetch the current SoC configuration.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ie17cca01a8eb9a6f5feebb093756f57
nxp: add dcfg driver
NXP SoC needs Device Configuration driver to
fetch the current SoC configuration.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ie17cca01a8eb9a6f5feebb093756f577692432bf
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|
| 0499215e | 09-Dec-2020 |
Pankaj Gupta <pankaj.gupta@nxp.com> |
nxp:add console driver for nxp platform
NXP SoCs, supports two types of UART controller:
- PL011 - using ARM drivers sources
- 16550 - using TI drivers source
Signed-off-by: Pankaj Gupta <pankaj.gu
nxp:add console driver for nxp platform
NXP SoCs, supports two types of UART controller:
- PL011 - using ARM drivers sources
- 16550 - using TI drivers source
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Iacbcefd2b6e5d96f83fa00ad25b4f63a4c822bb4
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|
| 34c1a1a4 | 15-Feb-2019 |
Yann Gautier <yann.gautier@st.com> |
tzc400: add support for interrupts
A new function tzc400_it_handler() is created to manage TZC400
interrupts. The required helpers to read and clear interrupts are added
as well.
In case DEBUG is en
tzc400: add support for interrupts
A new function tzc400_it_handler() is created to manage TZC400
interrupts. The required helpers to read and clear interrupts are added
as well.
In case DEBUG is enabled, more information about the faulty access
(address, NSAID, type of access) is displayed.
Change-Id: Ie9ab1c199a8f12b2c9472d7120efbdf35711284a
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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|
| 9655a1f5 | 15-Mar-2021 |
Roman Beranek <roman.beranek@prusa3d.com> |
plat/allwinner: do not setup 'disabled' regulators
If a PMIC regulator has its DT node disabled, leave the regulator off.
Change-Id: I895f740328e8f11d485829c3a89a9b9f8e5644be
Signed-off-by: Roman B
plat/allwinner: do not setup 'disabled' regulators
If a PMIC regulator has its DT node disabled, leave the regulator off.
Change-Id: I895f740328e8f11d485829c3a89a9b9f8e5644be
Signed-off-by: Roman Beranek <roman.beranek@prusa3d.com>
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|
| 13f3c516 | 10-Mar-2021 |
deqi.hu <deqi.hu@siengine.com> |
mmc:prevent accessing to the released space in case of wrong usage
1.Since in mmc_init, the most of mmc_device_info passed in are temporary variables.
In order to avoid referencing the released sp
mmc:prevent accessing to the released space in case of wrong usage
1.Since in mmc_init, the most of mmc_device_info passed in are temporary variables.
In order to avoid referencing the released space on the stack when maybe MISUSED,
it`s better to use global variables to store mmc_device_info in mmc.c
2.Delete redundant;
Signed-off-by: deqi.hu@siengine.com
Change-Id: I51ae90e7f878b19b4963508b3f7ec66339015ebc
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|
| 8c8efa86 | 05-Mar-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I76eee5c5,Ie45ab1d8,Iddcb83d3,I4425777d,I5be2837c, ... into integration
* changes:
drivers/gicv3: also shift eSPI register offset in GICD_OFFSET_64()
drivers/gicv3: add debug log f
Merge changes I76eee5c5,Ie45ab1d8,Iddcb83d3,I4425777d,I5be2837c, ... into integration
* changes:
drivers/gicv3: also shift eSPI register offset in GICD_OFFSET_64()
drivers/gicv3: add debug log for maximum INTID of SPI and eSPI
drivers/gicv3: limit SPI ID to avoid misjudgement in GICD_OFFSET()
drivers/gicv3: fix logical issue for num_eints
drivers/gicv3: fix potential GICD context override with ESPI enabled
drivers/gicv3: use mpidr to probe GICR for current CPU
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|
| 8909fa9b | 25-Feb-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I23f600b5,Icf9ffdf2,Iee7a51d1,I99afc312,I4bf8e8c0, ... into integration
* changes:
plat/marvell/armada: cleanup MSS SRAM if used for copy
plat/marvell: cn913x: allow CP1/CP2 mappin
Merge changes I23f600b5,Icf9ffdf2,Iee7a51d1,I99afc312,I4bf8e8c0, ... into integration
* changes:
plat/marvell/armada: cleanup MSS SRAM if used for copy
plat/marvell: cn913x: allow CP1/CP2 mapping at BLE stage
plat/marvell/armada/common/mss: use MSS SRAM in secure mode
include/drivers/marvell/mochi: add detection of secure mode
plat/marvell: fix SPD handling in dram port
marvell: drivers: move XOR0/1 DIOB from WIN 0 to 1
drivers/marvell/mochi: add support for cn913x in PCIe EP mode
drivers/marvell/mochi: add missing stream IDs configurations
plat/marvell/armada/a8k: support HW RNG by SMC
drivers/rambus: add TRNG-IP-76 driver
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|
| 441a065a | 24-Sep-2020 |
Bharat Gooty <bharat.gooty@broadcom.com> |
driver: brcm: add mdio driver
Change-Id: Id873670f68a4c584e3b7b586cab28565bb5a1c27
Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com> |
| 1d93ce63 | 23-Feb-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "nand: stm32_fmc_nand: remove dead code" into integration |
| 1272391e | 22-Feb-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes Ie5c48303,I5d363c46 into integration
* changes:
tzc400: adjust filter flag if it is set to FILTER_BIT_ALL
tzc400: fix logical error in FILTER_BIT definitions |
| 0d06b058 | 16-Feb-2021 |
Pali Rohár <pali@kernel.org> |
marvell: uart: a3720: Increase TX FIFO EMPTY timeout from 2ms to 3ms
TX FIFO has space for 32 characters. With default UART baudrate 115200 it
takes more than 2ms to transmit all 32 characters, so w
marvell: uart: a3720: Increase TX FIFO EMPTY timeout from 2ms to 3ms
TX FIFO has space for 32 characters. With default UART baudrate 115200 it
takes more than 2ms to transmit all 32 characters, so wait at least 3ms
before flushing TX FIFO.
If WTMI firmware transmitted something via UART before TF-A was booted,
some characters may still wait in TX FIFO when TF-A is initializing UART
driver. So wait at least 3ms to ensure that HW has enough time to transmit
all characters waiting in TX FIFO.
This fixes an issue where sometimes characters transmitted on UART by our
custom WTMI image are lost.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8ea4ea58e4ba3e0c0d7f47e679171b9b94442f19
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|
| 98641515 | 16-Feb-2021 |
Pali Rohár <pali@kernel.org> |
marvell: uart: a3720: Update delay code to be compatible with 1200 MHz CPU
Console initialization function needs to wait at least minimal specified
time. The fastest Armada 3720 CPU is 1200 MHz so i
marvell: uart: a3720: Update delay code to be compatible with 1200 MHz CPU
Console initialization function needs to wait at least minimal specified
time. The fastest Armada 3720 CPU is 1200 MHz so increase loop delay to
wait at least for 100 us on 1200 MHz variant too. The slowest Armada 3720
CPU is 600 MHz and in this case delay loop would take just 2 times more,
which is not a problem.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I1f0b4aabd0e08b7696feec631419f7f7c7ec17d2
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|
| ab1fe188 | 16-Feb-2021 |
Pali Rohár <pali@kernel.org> |
marvell: uart: a3720: Fix comments in console_a3700_core_init() function
The delay loop executes 3 instructions. These 3 instructions are executed
in 2 processor ticks and 30000 iterations on a 600
marvell: uart: a3720: Fix comments in console_a3700_core_init() function
The delay loop executes 3 instructions. These 3 instructions are executed
in 2 processor ticks and 30000 iterations on a 600 MHz CPU should yield
approximately 100 us. This means we are waiting 2 ms, not 20 ms, for TX
FIFO to be empty.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2cccad405bcc73cd6d1062adc0205c405c16c15f
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|
| 3ed01657 | 08-Feb-2021 |
Yann Gautier <yann.gautier@foss.st.com> |
nand: stm32_fmc_nand: remove dead code
The FMC driver in TF-A only supports NAND Mode 0 timings.
The timings are then hard-coded as macros, leading to some parts of code
unreachable.
This issue was
nand: stm32_fmc_nand: remove dead code
The FMC driver in TF-A only supports NAND Mode 0 timings.
The timings are then hard-coded as macros, leading to some parts of code
unreachable.
This issue was found by Coverity scan: CID 366361.
Change-Id: I864c51ce11b9ef74ad82b3301f56f46a2e0f70ca
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
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|
| 27528f72 | 16-Dec-2019 |
Ofer Heifetz <oferh@marvell.com> |
marvell: drivers: move XOR0/1 DIOB from WIN 0 to 1
Change CP110 XOR (DMA) to use WIN1 which is used for PCI-EP address
space only and using this window bypasses the need for translation
in the SMMU
marvell: drivers: move XOR0/1 DIOB from WIN 0 to 1
Change CP110 XOR (DMA) to use WIN1 which is used for PCI-EP address
space only and using this window bypasses the need for translation
in the SMMU which has performance impact.
Change-Id: I98d99da59e904e6721cfa263ce44ad178a0fa956
Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/20389
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
show more ...
|
| 2bcde264 | 17-Dec-2019 |
Konstantin Porotchkin <kostap@marvell.com> |
drivers/marvell/mochi: add support for cn913x in PCIe EP mode
Change-Id: I4dc33d1eb59395605f64e5aad5cafa10c53265cc
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1g
drivers/marvell/mochi: add support for cn913x in PCIe EP mode
Change-Id: I4dc33d1eb59395605f64e5aad5cafa10c53265cc
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/20453
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
show more ...
|
| c82cf21d | 19-Oct-2020 |
Konstantin Porotchkin <kostap@marvell.com> |
drivers/marvell/mochi: add missing stream IDs configurations
- Add setup of DMA stream IDs in AP807/AP806 drivers
Change-Id: I23ffe86002db4753f812c63c31431a3d04056d07
Signed-off-by: Konstantin Poro
drivers/marvell/mochi: add missing stream IDs configurations
- Add setup of DMA stream IDs in AP807/AP806 drivers
Change-Id: I23ffe86002db4753f812c63c31431a3d04056d07
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
show more ...
|
| 57660d9d | 26-Jul-2020 |
Konstantin Porotchkin <kostap@marvell.com> |
plat/marvell/armada/a8k: support HW RNG by SMC
Add initialization for TRNG-IP-76 driver and support SMC call
0xC200FF11 used for reading HW RNG value by secondary bootloader
software for KASLR suppo
plat/marvell/armada/a8k: support HW RNG by SMC
Add initialization for TRNG-IP-76 driver and support SMC call
0xC200FF11 used for reading HW RNG value by secondary bootloader
software for KASLR support.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: I1d644f67457b28d347523f8a7bfc4eacc45cba68
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/32688
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
show more ...
|
| 6aa9f5d1 | 26-Jul-2020 |
Konstantin Porotchkin <kostap@marvell.com> |
drivers/rambus: add TRNG-IP-76 driver
Add Rambus (InsideSecure) TRNG-IP-76 HW RNG driver.
This IP is part of Marvell Armada CP110/CP115 die integrated
to Armada 7k/8K/CN913x SoCs
Change-Id: I9c5f51
drivers/rambus: add TRNG-IP-76 driver
Add Rambus (InsideSecure) TRNG-IP-76 HW RNG driver.
This IP is part of Marvell Armada CP110/CP115 die integrated
to Armada 7k/8K/CN913x SoCs
Change-Id: I9c5f510ad6728c7ed168da43d85b19d5852cd873
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
show more ...
|