Merge changes Id7bdbc9b,Ia813e051,I2c437380,I736724cc,I454fb40a, ... into integration

* changes:
renesas: rzg: Add support to identify EK874 RZ/G2E board
drivers: renesas: common: watchdog: Add

Merge changes Id7bdbc9b,Ia813e051,I2c437380,I736724cc,I454fb40a, ... into integration

* changes:
renesas: rzg: Add support to identify EK874 RZ/G2E board
drivers: renesas: common: watchdog: Add support for RZ/G2E
drivers: renesas: rzg: Add QoS support for RZ/G2E
drivers: renesas: rzg: Add PFC support for RZ/G2E
drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoC
renesas: rzg: Add support to identify HopeRun HiHope RZ/G2N board
drivers: renesas: common: emmc: Select eMMC channel for RZ/G2N SoC
drivers: renesas: rzg: Add QoS support for RZ/G2N
drivers: renesas: rzg: Add PFC support for RZ/G2N
drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoC
renesas: rzg: Add support to identify HopeRun HiHope RZ/G2H board
drivers: renesas: common: emmc: Select eMMC channel for RZ/G2H SoC
drivers: renesas: rzg: Add QoS support for RZ/G2H
drivers: renesas: rzg: Add PFC support for RZ/G2H
drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC
drivers: renesas: rzg: Switch using common ddr code
drivers: renesas: ddr: Move to common

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renesas: rzg: Add support to identify EK874 RZ/G2E board

Add support to identify Silicon Linux RZ/G2E evaluation kit (EK874).

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

renesas: rzg: Add support to identify EK874 RZ/G2E board

Add support to identify Silicon Linux RZ/G2E evaluation kit (EK874).

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Id7bdbc9b0d25aa9af496d58d4bd5055579edc104

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drivers: renesas: common: watchdog: Add support for RZ/G2E

Add watchdog support for RZ/G2E SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.da

drivers: renesas: common: watchdog: Add support for RZ/G2E

Add watchdog support for RZ/G2E SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ia813e051f6605028d0bb83967893ebd107fc8551

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drivers: renesas: rzg: Add QoS support for RZ/G2E

Add QoS support for RZ/G2E SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesa

drivers: renesas: rzg: Add QoS support for RZ/G2E

Add QoS support for RZ/G2E SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I2c4373807ab8c550d86d6abc97f5b01f2fb78fb3

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drivers: renesas: rzg: Add PFC support for RZ/G2E

Add pin control support for RZ/G2E SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@b

drivers: renesas: rzg: Add PFC support for RZ/G2E

Add pin control support for RZ/G2E SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I736724cc0dd32f2169018ed7f2f48319b039b61f

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drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoC

DRAM initialization on RZ/G2E SoC is identical to R-Car E3 so re-use the
same.

Signed-off-by: Lad Prabhakar <prabhakar.ma

drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoC

DRAM initialization on RZ/G2E SoC is identical to R-Car E3 so re-use the
same.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I454fb40af4f8ce6c4c0d2a53edb307326efd02df

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renesas: rzg: Add support to identify HopeRun HiHope RZ/G2N board

Add support to identify HopeRun HiHope RZ/G2N board.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewe

renesas: rzg: Add support to identify HopeRun HiHope RZ/G2N board

Add support to identify HopeRun HiHope RZ/G2N board.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ib47aba84b63488247f6e9da1f5878140129766ce

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drivers: renesas: common: emmc: Select eMMC channel for RZ/G2N SoC

Select MMC_CH1 for eMMC on RZ/G2N SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Da

drivers: renesas: common: emmc: Select eMMC channel for RZ/G2N SoC

Select MMC_CH1 for eMMC on RZ/G2N SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ib584b5203f38423ffe2ab52c6e6922f5b34a33ee

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drivers: renesas: rzg: Add QoS support for RZ/G2N

Add QoS support for RZ/G2N SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesa

drivers: renesas: rzg: Add QoS support for RZ/G2N

Add QoS support for RZ/G2N SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I663b50d9fb41b9b20a6b54795278659b2b184bc4

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drivers: renesas: rzg: Add PFC support for RZ/G2N

Add pin control support for RZ/G2N SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@b

drivers: renesas: rzg: Add PFC support for RZ/G2N

Add pin control support for RZ/G2N SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Ib5eb4f3b1b75e158ec13c4eefdbe9688344206a3

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drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoC

Add support for initializing DRAM on RZ/G2N SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
R

drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoC

Add support for initializing DRAM on RZ/G2N SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Id09a367b92b11a5da88f2dce6887677cc935d0c0

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renesas: rzg: Add support to identify HopeRun HiHope RZ/G2H board

Add support to identify HopeRun HiHope RZ/G2H board.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewe

renesas: rzg: Add support to identify HopeRun HiHope RZ/G2H board

Add support to identify HopeRun HiHope RZ/G2H board.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I6b28350ef50595fea9a1b1b7353fcabaeb935970

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drivers: renesas: common: emmc: Select eMMC channel for RZ/G2H SoC

Select MMC_CH1 for eMMC on RZ/G2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Da

drivers: renesas: common: emmc: Select eMMC channel for RZ/G2H SoC

Select MMC_CH1 for eMMC on RZ/G2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I1bdfa462fd98b144042c014701b342b87e1efc9d

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drivers: renesas: rzg: Add QoS support for RZ/G2H

Add QoS support for RZ/G2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesa

drivers: renesas: rzg: Add QoS support for RZ/G2H

Add QoS support for RZ/G2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: If7d8940148fc31887568fd501c6cab609e715ba4

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drivers: renesas: rzg: Add PFC support for RZ/G2H

Add pin control support for RZ/G2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@b

drivers: renesas: rzg: Add PFC support for RZ/G2H

Add pin control support for RZ/G2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I06dc259d7d26a5a5313e8731ea72f846bfca09ed

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drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC

Add support for initializing DRAM on RZ/G2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
R

drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC

Add support for initializing DRAM on RZ/G2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: Iae23f1093f65a9efd065d37b7d6e9340ff6350b9

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drivers: renesas: rzg: Switch using common ddr code

Switch using common ddr driver code from renesas/common/ddr directory
for RZ/G2M SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.r

drivers: renesas: rzg: Switch using common ddr code

Switch using common ddr driver code from renesas/common/ddr directory
for RZ/G2M SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I807dcb0bc5186bd32bc1c577945d28634bb10e1f

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drivers: renesas: ddr: Move to common

Move ddr driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Lad Prabhakar <prabhakar.

drivers: renesas: ddr: Move to common

Move ddr driver code to common directory, so that the same
code can be re-used by both R-Car Gen3 and RZ/G2 platforms.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Change-Id: I9aef73d3e9a027a127ce7483b72d339559866727

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Add SiP service to configure Arm Ethos-N NPU

By default the Arm Ethos-N NPU will boot up in secure mode. In this mode
the non-secure world cannot access the registers needed to use the NPU.
To still

Add SiP service to configure Arm Ethos-N NPU

By default the Arm Ethos-N NPU will boot up in secure mode. In this mode
the non-secure world cannot access the registers needed to use the NPU.
To still allow the non-secure world to use the NPU, a SiP service has
been added that can delegate non-secure access to the registers needed
to use it.

Only the HW_CONFIG for the Arm Juno platform has been updated to include
the device tree for the NPU and the platform currently only loads the
HW_CONFIG in AArch64 builds.

Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I65dfd864042ed43faae0a259dcf319cbadb5f3d2

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drivers/marvell: check if TRNG unit is present

Some Marvell SoCs may have crypto engine disabled in the HW.
This patch checks the AP LD0 efuse for crypto engine/TRNG
presence before initializing the

drivers/marvell: check if TRNG unit is present

Some Marvell SoCs may have crypto engine disabled in the HW.
This patch checks the AP LD0 efuse for crypto engine/TRNG
presence before initializing the driver.

Change-Id: I441e7c69a137106bd36302b028b04c0b31896dbd
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/47314
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Yi Guo <yi.guo@cavium.com>

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drivers: marvell: comphy: add rx training on 10G port

This patch forces rx training on 10G ports
as part of comphy_smc call from Linux.

Signed-off-by: Alex Evraev <alexev@marvell.com>
Change-Id: Ie

drivers: marvell: comphy: add rx training on 10G port

This patch forces rx training on 10G ports
as part of comphy_smc call from Linux.

Signed-off-by: Alex Evraev <alexev@marvell.com>
Change-Id: Iebe6ea7c8b21cbdce5c466c8a69b92e9d7c8a8ca
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/30763
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>

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plat/marvell/armada: allow builds without MSS support

Setting MSS_SUPPORT to 0 also removes requirement for SCP_BL2
definition.
Images build with MSS_SUPPORT=0 will not include service CPUs
FW and w

plat/marvell/armada: allow builds without MSS support

Setting MSS_SUPPORT to 0 also removes requirement for SCP_BL2
definition.
Images build with MSS_SUPPORT=0 will not include service CPUs
FW and will not support PM, FC and other features implemented
in these FW images.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Change-Id: Idf301ebd218ce65a60f277f3876d0aeb6c72f105
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/37769
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Stefan Chulski <stefanc@marvell.com>
Reviewed-by: Ofer Heifetz <oferh@marvell.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>

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drivers: marvell: misc-dfx: extend dfx whitelist

Linux cpu clk driver requires access to some dfx registers. By adding
these registers to the white list, we enable access to them from
non-secure wor

drivers: marvell: misc-dfx: extend dfx whitelist

Linux cpu clk driver requires access to some dfx registers. By adding
these registers to the white list, we enable access to them from
non-secure world.

Change-Id: Ic05c96b375121c025bfb41c2ac9474a530720155
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/25187
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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drivers: marvell: add support for secure read/write of dfx register-set

Since the dfx register set is going to be marked as secure expose dfx
secure read and write function via SiP services. In intr

drivers: marvell: add support for secure read/write of dfx register-set

Since the dfx register set is going to be marked as secure expose dfx
secure read and write function via SiP services. In introduced misc_dfx
driver some registers are white-listed so non-secure software can still
access them.

This will allow non-secure word drivers access some white-listed
registers related to e.g.: Sample at reset, efuses, SoC type and
revision ID accesses.

Change-Id: If9ae2da51ab2e6ca62b9a2c940819259bf25edc0
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/25055
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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ddr_phy: use smc calls to access ddr phy registers

Added smc calls support to access ddr phy registers.

Change-Id: Ibaa0a8e20b6398ab394c7e2e9ea61f9a28cdb870
Signed-off-by: Alex Leibovich <alexl@mar

ddr_phy: use smc calls to access ddr phy registers

Added smc calls support to access ddr phy registers.

Change-Id: Ibaa0a8e20b6398ab394c7e2e9ea61f9a28cdb870
Signed-off-by: Alex Leibovich <alexl@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/20791
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

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