refactor(drivers/marvell/comphy-3700): simplify usage of indirect access on lane2

For code cleanup add two helper functions comphy_sata_set_indirect() and
comphy_usb_set_indirect() for SATA and USB

refactor(drivers/marvell/comphy-3700): simplify usage of indirect access on lane2

For code cleanup add two helper functions comphy_sata_set_indirect() and
comphy_usb_set_indirect() for SATA and USB 3.0 modes and remove additional
'mode' argument which is not needed anymore.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I23146f569db318dbaed5d411d7d175abf6efff85

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refactor(drivers/marvell/comphy-3700): simplify usage of sata power off

Function mvebu_a3700_comphy_sata_power_off() uses comphy_mode parameter
only for extracting mode bits. Mode is always COMPHY_S

refactor(drivers/marvell/comphy-3700): simplify usage of sata power off

Function mvebu_a3700_comphy_sata_power_off() uses comphy_mode parameter
only for extracting mode bits. Mode is always COMPHY_SATA_MODE, so
there is no need to pass comphy_mode parameter to this function. Use
directly COMPHY_SATA_MODE in mvebu_a3700_comphy_sata_power_off().

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ib6b7c2bf62c1ef4d8a6af240c08696d5cd506b14

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Merge "fix(drivers/marvell/comphy): fix name of 3.125G SerDes mode" into integration

fix(drivers/marvell/comphy): fix name of 3.125G SerDes mode

There is no support for 2.5/3.125G SGMII. This 3.125G SerDes mode is not
SGMII. It is just plain 1000Base-X (as defined in IEEE 802.3z sta

fix(drivers/marvell/comphy): fix name of 3.125G SerDes mode

There is no support for 2.5/3.125G SGMII. This 3.125G SerDes mode is not
SGMII. It is just plain 1000Base-X (as defined in IEEE 802.3z standard)
but upclocked 2.5x. This mode is commonly known under name 2500Base-X.

So remove incorrect SGMII keyword from names and comments and replace it
by more adequate 2500Base-X keyword.

There is no functional change in code, just renaming macros and updating
comments.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: If79aec16cc233f4896aafd75bfbbebb3f172a197

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Merge "fix(plat/marvell/a3720/uart): fix UART parent clock rate determination" into integration

fix(plat/marvell/a3720/uart): fix UART parent clock rate determination

The UART code for the A3K platform assumes that UART parent clock rate
is always 25 MHz. This is incorrect, because the xtal cl

fix(plat/marvell/a3720/uart): fix UART parent clock rate determination

The UART code for the A3K platform assumes that UART parent clock rate
is always 25 MHz. This is incorrect, because the xtal clock can also run
at 40 MHz (this is board specific).

The frequency of the xtal clock is determined by a value on a strapping
pin during SOC reset. The code to determine this frequency is already in
A3K's comphy driver.

Move the get_ref_clk() function from the comphy driver to a separate
file and use it for UART parent clock rate determination.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e

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Merge changes Id2a538c3,Ifa0339e7,I8b09fab8 into integration

* changes:
drivers: marvell: comphy-a3700: Set TXDCLK_2X_SEL bit during PCIe initialization
drivers: marvell: comphy-a3700: Set mask

Merge changes Id2a538c3,Ifa0339e7,I8b09fab8 into integration

* changes:
drivers: marvell: comphy-a3700: Set TXDCLK_2X_SEL bit during PCIe initialization
drivers: marvell: comphy-a3700: Set mask parameter for every reg_set call
drivers: marvell: comphy-a3700: Fix configuring polarity invert bits

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drivers: marvell: comphy-a3700: Set TXDCLK_2X_SEL bit during PCIe initialization

Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link
Initialization says that TXDCLK_2X_SEL bit need

drivers: marvell: comphy-a3700: Set TXDCLK_2X_SEL bit during PCIe initialization

Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link
Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe
Root Complex mode. Both U-Boot and Linux kernel support only Root Complex
mode. Set this bit.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Id2a538c379b911b62597f9463b4842b7b5c24df7

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drivers: marvell: comphy-a3700: Set mask parameter for every reg_set call

The third argument of the reg_set() function has name 'mask', which
indicates that it is a mask applied to the register valu

drivers: marvell: comphy-a3700: Set mask parameter for every reg_set call

The third argument of the reg_set() function has name 'mask', which
indicates that it is a mask applied to the register value which is
going to be updated. But the implementation of this function uses
this argument to clear prior value of the register, i.e. instead of
new_val = (old_val & ~mask) | (data & mask);
it does
new_val = (new_val & ~mask) | data;

(The more proper name for this function should be reg_clrsetbits(),
since internally it calls mmio_clrsetbits_32().)

To make code more readable set 'mask' argument to real mask, i.e. bits
of register values which are going to be updated.

This patch does not make any functional change, only cosmetic, due to
how 'mask' is interpreted.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ifa0339e79c07d1994c7971b65d966b92cb735f65

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drivers: marvell: comphy-a3700: Fix configuring polarity invert bits

TXD_INVERT_BIT or RXD_INVERT_BIT needs to be set only in case when
appropriate polarity is inverted. Otherwise these bits should

drivers: marvell: comphy-a3700: Fix configuring polarity invert bits

TXD_INVERT_BIT or RXD_INVERT_BIT needs to be set only in case when
appropriate polarity is inverted. Otherwise these bits should be
cleared.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I8b09fab883a7b995fd72a7d8ae6233f0fa07011b

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Merge "drivers: marvell: comphy-a3700: support SGMII COMPHY power off" into integration

Merge "drivers: marvell: comphy-a3700: fix USB3 powering on when on lane 2" into integration

drivers: marvell: comphy-a3700: support SGMII COMPHY power off

Add support for powering off the SGMII COMPHY (on lanes 0 and 1).
This is needed sometimes on Turris Mox when using KEXEC.

There is al

drivers: marvell: comphy-a3700: support SGMII COMPHY power off

Add support for powering off the SGMII COMPHY (on lanes 0 and 1).
This is needed sometimes on Turris Mox when using KEXEC.

There is also another benefit of a little energy saving when the given
network interface is down.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I55ae0fe3627e7cc0f65c78a00771939d8bf5399f

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drivers: marvell: comphy-a3700: fix USB3 powering on when on lane 2

When USB3 is on lane 2 and indirect register access is used, the polling
at the end of the mvebu_a3700_comphy_usb3_power_on functi

drivers: marvell: comphy-a3700: fix USB3 powering on when on lane 2

When USB3 is on lane 2 and indirect register access is used, the polling
at the end of the mvebu_a3700_comphy_usb3_power_on function is
incorrect.

The LOOPBACK_REG0 register should not be used at all. Instead we have to
write the LANE_STATUS1 register address (with offset
USB3PHY_LANE2_REG_BASE_OFFSET) into the indirect address register and
then we should poll indirect data register.

This fixes problems on Turris Mox, which uses lane 2 for USB3.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I968b0cccee5ddbe10a2b5614e52e52d87682aacd

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Merge pull request #1726 from antonio-nino-diaz-arm/an/includes

Sanitise includes across codebase

Sanitise includes across codebase

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- inclu

Sanitise includes across codebase

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a282 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca33988b9 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1623 from MISL-EBU-System-SW/a3700-support

Add support for Armada 3700 and COMPHY porting layer

drivers: marvell Add Armada-37xx COMPHY driver

Add support for Marvell Armada-3700 COMPHY driver

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Konstantin Porotchkin <kostap@mar

drivers: marvell Add Armada-37xx COMPHY driver

Add support for Marvell Armada-3700 COMPHY driver

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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