| 630a06c4 | 03-Nov-2023 |
Olivier Deprez <olivier.deprez@arm.com> |
fix(el3-spmc): remove experimental flag
The EL3 SPMC is known to be deployed into end products and properly
tested since its introduction into TF-A v2.7.
Signed-off-by: Olivier Deprez <olivier.depr
fix(el3-spmc): remove experimental flag
The EL3 SPMC is known to be deployed into end products and properly
tested since its introduction into TF-A v2.7.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I96bb897cfefef20c33cfc39627b10746dce5485c
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| 31dcf234 | 13-Oct-2023 |
Nishant Sharma <nishant.sharma@arm.com> |
feat(docs): save BL32 image base and size in entry point info
There is no platform function to retrieve the info in the generic code.
Populate the BL32 image base, size and max limit in arg2, arg3 a
feat(docs): save BL32 image base and size in entry point info
There is no platform function to retrieve the info in the generic code.
Populate the BL32 image base, size and max limit in arg2, arg3 and arg4.
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I35527fb41829102083b488a5150c0c707c5ede15
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| 183329a5 | 15-Aug-2023 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
refactor(cm): introduce INIT_UNUSED_NS_EL2 macro
Introducing INIT_UNUSED_NS_EL2 macro which guards the code that
disables the unused EL2 when a platform hands off from EL3
to NS-EL1 instead of NS-EL
refactor(cm): introduce INIT_UNUSED_NS_EL2 macro
Introducing INIT_UNUSED_NS_EL2 macro which guards the code that
disables the unused EL2 when a platform hands off from EL3
to NS-EL1 instead of NS-EL2. Platforms without NS-EL2 in use
must enable this flag.
BREAKING CHANGE: Initialisation code for handoff from EL3 to NS-EL1
disabled by default. Platforms which do that need to enable this macro
going forward
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I61431cc4f7e2feb568d472828e5fd79cc73e51f5
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| 11a8a3e9 | 06-Nov-2023 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes from topic "errata" into integration
* changes:
fix(cpus): workaround for Cortex-X2 erratum 2742423
fix(cpus): workaround for Cortex-A710 erratum 2742423
fix(cpus): workaround fo
Merge changes from topic "errata" into integration
* changes:
fix(cpus): workaround for Cortex-X2 erratum 2742423
fix(cpus): workaround for Cortex-A710 erratum 2742423
fix(cpus): workaround for Neoverse N2 erratum 2340933
fix(cpus): workaround for Neoverse N2 erratum 2346952
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| 29683ef7 | 06-Nov-2023 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "docs: add TF-A version numbering information" into integration |
| dd532b9e | 03-Nov-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_tsp_feat" into integration
* changes:
docs(versal-net): add TSP build documentation
docs(versal): add TSP build documentation
feat(versal-net): add tsp support
Merge changes from topic "xlnx_tsp_feat" into integration
* changes:
docs(versal-net): add TSP build documentation
docs(versal): add TSP build documentation
feat(versal-net): add tsp support
feat(versal): add tsp support
refactor(xilinx): add generic TSP makefile
chore(zynqmp): reorganize tsp code into common path
refactor(xilinx): rename platform function to generic name
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| 3e56c69f | 04-Oct-2023 |
Yann Gautier <yann.gautier@st.com> |
docs: add TF-A version numbering information
Add a chapter "Version numbering" in release information file that
explains macros used for TF-A version. It also introduces VERSION_PATCH
macro that is
docs: add TF-A version numbering information
Add a chapter "Version numbering" in release information file that
explains macros used for TF-A version. It also introduces VERSION_PATCH
macro that is used for LTS releases. A comment for this macro is also
added in Makefile.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I946b6cb91bb8454131f07b24534d28ab1aef1771
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| fe06e118 | 17-Oct-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Cortex-X2 erratum 2742423
Cortex-X2 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open.
The workaround is to set CPUACTLR5_EL1[56:55
fix(cpus): workaround for Cortex-X2 erratum 2742423
Cortex-X2 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open.
The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest
Change-Id: I03897dc2a7f908937612c2b66ce7a043c1b7575d
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
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| d7bc2cb4 | 17-Oct-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Cortex-A710 erratum 2742423
Cortex-A710 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open. The workaround is to set
CPUACTLR5_EL1[5
fix(cpus): workaround for Cortex-A710 erratum 2742423
Cortex-A710 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open. The workaround is to set
CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest
Change-Id: I4d9d3760491f1e6c59b2667c16d59b99cc7979f1
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
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| 68085ad4 | 17-Oct-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Neoverse N2 erratum 2340933
Neoverse N2 erratum 2340933 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1. The workaround is to set
CPUACTLR5_EL1[61] to
fix(cpus): workaround for Neoverse N2 erratum 2340933
Neoverse N2 erratum 2340933 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1. The workaround is to set
CPUACTLR5_EL1[61] to 1.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1982442/latest
Change-Id: I121add0dd35072c53392d33f049d893a5ff6354f
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
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| 6cb8be17 | 17-Oct-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Neoverse N2 erratum 2346952
Neoverse N2 erratum 2346952 is a Cat B erratum that applies to all
revisions <= r0p2 and is fixed in r0p3.
The workaround is to set L2 TQ size s
fix(cpus): workaround for Neoverse N2 erratum 2346952
Neoverse N2 erratum 2346952 is a Cat B erratum that applies to all
revisions <= r0p2 and is fixed in r0p3.
The workaround is to set L2 TQ size statically to it's full size.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1982442/latest
Change-Id: I03c3cf1f951fbc906fdebcb99a523c5ac8ba055d
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
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| 6f802c44 | 02-Nov-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "mp/exceptions" into integration
* changes:
docs(ras): update RAS documentation
docs(el3-runtime): update BL31 exception vector handling
fix(el3-runtime): restrict low
Merge changes from topic "mp/exceptions" into integration
* changes:
docs(ras): update RAS documentation
docs(el3-runtime): update BL31 exception vector handling
fix(el3-runtime): restrict lower el EA handlers in FFH mode
fix(ras): remove RAS_FFH_SUPPORT and introduce FFH_SUPPORT
fix(ras): restrict ENABLE_FEAT_RAS to have only two states
feat(ras): use FEAT_IESB for error synchronization
feat(el3-runtime): modify vector entry paths
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| 5fc1a32a | 02-Nov-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "docs: deletion of a few deprecated platforms not yet confirmed" into integration |
| 41b5a23c | 29-Oct-2023 |
Prasad Kummari <prasad.kummari@amd.com> |
docs(versal-net): add TSP build documentation
Add information about Versal NET platform for TSP and provide
the build commands.
Change-Id: Id7c9d75f8a42813ca2bfd18494bfc6b73df0af52
Signed-off-by: P
docs(versal-net): add TSP build documentation
Add information about Versal NET platform for TSP and provide
the build commands.
Change-Id: Id7c9d75f8a42813ca2bfd18494bfc6b73df0af52
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
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|
| 7b7c5350 | 29-Oct-2023 |
Prasad Kummari <prasad.kummari@amd.com> |
docs(versal): add TSP build documentation
Add information about Versal platform for TSP and provide
the build commands.
Change-Id: I7106ab477a881c58e1c45863bd6854d188982282
Signed-off-by: Prasad Ku
docs(versal): add TSP build documentation
Add information about Versal platform for TSP and provide
the build commands.
Change-Id: I7106ab477a881c58e1c45863bd6854d188982282
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
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|
| 42604d2d | 13-Jul-2023 |
Manish Pandey <manish.pandey2@arm.com> |
docs(ras): update RAS documentation
Add details about RAS error handling philosophies and its implementation
It also updates the tests introduced to verify them.
Signed-off-by: Manish Pandey <manis
docs(ras): update RAS documentation
Add details about RAS error handling philosophies and its implementation
It also updates the tests introduced to verify them.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Iedc8c1e713dad05baadd58e5752df36fa00121a7
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|
| 9f9bfd7a | 21-Jul-2023 |
Manish Pandey <manish.pandey2@arm.com> |
docs(el3-runtime): update BL31 exception vector handling
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ieae66bafe1cdd253edebecddea156551144a1cc9 |
| f87e54f7 | 10-Oct-2023 |
Manish Pandey <manish.pandey2@arm.com> |
fix(ras): remove RAS_FFH_SUPPORT and introduce FFH_SUPPORT
This patch removes RAS_FFH_SUPPORT macro which is the combination of
ENABLE_FEAT_RAS and HANDLE_EA_EL3_FIRST_NS. Instead introduce an
inter
fix(ras): remove RAS_FFH_SUPPORT and introduce FFH_SUPPORT
This patch removes RAS_FFH_SUPPORT macro which is the combination of
ENABLE_FEAT_RAS and HANDLE_EA_EL3_FIRST_NS. Instead introduce an
internal macro FFH_SUPPORT which gets enabled when platforms wants
to enable lower EL EA handling at EL3. The internal macro FFH_SUPPORT
will be automatically enabled if HANDLE_EA_EL3_FIRST_NS is enabled.
FFH_SUPPORT along with ENABLE_FEAT_RAS will be used in source files
to provide equivalent check which was provided by RAS_FFH_SUPPORT
earlier. In generic code we needed a macro which could abstract both
HANDLE_EA_EL3_FIRST_NS and RAS_FFH_SUPPORT macros that had limitations.
Former was tied up with NS world only while the latter was tied to RAS
feature.
This is to allow Secure/Realm world to have their own FFH macros
in future.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ie5692ccbf462f5dcc3f005a5beea5aa35124ac73
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|
| 970a4a8d | 10-Oct-2023 |
Manish Pandey <manish.pandey2@arm.com> |
fix(ras): restrict ENABLE_FEAT_RAS to have only two states
As part of migrating RAS extension to feature detection mechanism, the
macro ENABLE_FEAT_RAS was allowed to have dynamic detection (FEAT_ST
fix(ras): restrict ENABLE_FEAT_RAS to have only two states
As part of migrating RAS extension to feature detection mechanism, the
macro ENABLE_FEAT_RAS was allowed to have dynamic detection (FEAT_STATE
2). Considering this feature does impact execution of EL3 and we need
to know at compile time about the presence of this feature. Do not use
dynamic detection part of feature detection mechanism.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I23858f641f81fbd81b6b17504eb4a2cc65c1a752
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|
| d5be8027 | 05-Sep-2023 |
Olivier Deprez <olivier.deprez@arm.com> |
docs(spm-mm): remove reference to SEL2 SPMC
As the SEL2 SPMC design doc is migrated to Hafnium tree, remove the
reference to this implementation from TF-A's SPM-MM doc.
Signed-off-by: Olivier Depre
docs(spm-mm): remove reference to SEL2 SPMC
As the SEL2 SPMC design doc is migrated to Hafnium tree, remove the
reference to this implementation from TF-A's SPM-MM doc.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I1609c7d1d098420412dffc7b1309cc9c11502f8a
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|
| 6c33e871 | 05-Sep-2023 |
Olivier Deprez <olivier.deprez@arm.com> |
docs: remove SEL2 SPMC threat model
The SEL2/Hafnium SPMC implementation threat model is now hosted at [1].
[1] https://hafnium.readthedocs.io/en/latest/threat_model_spm.html
Signed-off-by: Olivie
docs: remove SEL2 SPMC threat model
The SEL2/Hafnium SPMC implementation threat model is now hosted at [1].
[1] https://hafnium.readthedocs.io/en/latest/threat_model_spm.html
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I83d3f21ef0ee9364529c7b80de9872034ff92b09
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|
| 0fd975ac | 05-Sep-2023 |
Olivier Deprez <olivier.deprez@arm.com> |
docs: remove unused SPM related diagrams
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ia60c4aa6a0aa0da5765d295e658964e6faa5960a |
| 48b92c60 | 30-Oct-2023 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes from topic "mb/psa-crypto-ecdsa" into integration
* changes:
docs: mark PSA_CRYPTO as an experimental feature
feat(fvp): increase BL1 RW area for PSA_CRYPTO implementation
feat(m
Merge changes from topic "mb/psa-crypto-ecdsa" into integration
* changes:
docs: mark PSA_CRYPTO as an experimental feature
feat(fvp): increase BL1 RW area for PSA_CRYPTO implementation
feat(mbedtls-psa): mbedTLS PSA Crypto with ECDSA
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|
| 113273aa | 26-Oct-2023 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes from topic "sm/err_errata" into integration
* changes:
fix(cpus): fix the rev-var of Neoverse-V1
fix(errata-abi): update the Neoverse-N2 errata ABI struct
fix(errata-abi): update
Merge changes from topic "sm/err_errata" into integration
* changes:
fix(cpus): fix the rev-var of Neoverse-V1
fix(errata-abi): update the Neoverse-N2 errata ABI struct
fix(errata-abi): update the neoverse-N1 errata ABI struct
fix(cpus): fix the rev-var of Cortex-X2
fix(errata-abi): update the Cortex-A78C errata ABI struct
fix(cpus): update the rev-var for Cortex-A78AE
fix(errata-abi): update the Cortex-A76 errata ABI struct
fix(cpus): fix the rev-var for Cortex-A710
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| 4c02c99b | 26-Oct-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs: deletion of a few deprecated platforms not yet confirmed
Updated the 'Deprecated Platforms' table to reflect that the
deletion of sgi575 and rdn1Edge is still unconfirmed.
Change-Id: Ie8e8af5
docs: deletion of a few deprecated platforms not yet confirmed
Updated the 'Deprecated Platforms' table to reflect that the
deletion of sgi575 and rdn1Edge is still unconfirmed.
Change-Id: Ie8e8af55a735f624f5ee604d75bb497d870620cd
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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|