docs(psci): expound runtime instrumentation docs

Change-Id: I3c30b44d4196c30fd07373282150e543959fce1a
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

Merge "docs: update release and code freeze dates" into integration

Merge changes from topic "mp/feat_ras" into integration

* changes:
refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED
refactor(ras): replace RAS_EXTENSION with FEAT_RAS

Merge changes from topic "srm/Errata_ABI_El3" into integration

* changes:
docs(errata_abi): document the errata abi changes
feat(fvp): enable errata management interface
fix(cpus): workaround

Merge changes from topic "srm/Errata_ABI_El3" into integration

* changes:
docs(errata_abi): document the errata abi changes
feat(fvp): enable errata management interface
fix(cpus): workaround platforms non-arm interconnect
refactor(errata_abi): factor in non-arm interconnect
feat(errata_abi): errata management firmware interface

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Merge changes from topic "bk/context_refactor" into integration

* changes:
fix(gicv3): restore scr_el3 after changing it
refactor(cm): make SVE and SME build dependencies logical

Merge "docs: update TZC secured DRAM map for FVP and Juno" into integration

Merge changes I06b35f11,If80573d6 into integration

* changes:
docs: remove plat_convert_pk() interface from release doc
chore(io): remove io_dummy driver

refactor(ras): replace RAS_EXTENSION with FEAT_RAS

The current usage of RAS_EXTENSION in TF-A codebase is to cater for two
things in TF-A :
1. Pull in necessary framework and platform hooks for Firm

refactor(ras): replace RAS_EXTENSION with FEAT_RAS

The current usage of RAS_EXTENSION in TF-A codebase is to cater for two
things in TF-A :
1. Pull in necessary framework and platform hooks for Firmware first
handling(FFH) of RAS errors.
2. Manage the FEAT_RAS extension when switching the worlds.

FFH means that all the EAs from NS are trapped in EL3 first and signaled
to NS world later after the first handling is done in firmware. There is
an alternate way of handling RAS errors viz Kernel First handling(KFH).
Tying FEAT_RAS to RAS_EXTENSION build flag was not correct as the
feature is needed for proper handling KFH in as well.

This patch breaks down the RAS_EXTENSION flag into a flag to denote the
CPU architecture `ENABLE_FEAT_RAS` which is used in context management
during world switch and another flag `RAS_FFH_SUPPORT` to pull in
required framework and platform hooks for FFH.

Proper support for KFH will be added in future patches.

BREAKING CHANGE: The previous RAS_EXTENSION is now deprecated. The
equivalent functionality can be achieved by the following
2 options:
- ENABLE_FEAT_RAS
- RAS_FFH_SUPPORT

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I1abb9ab6622b8f1b15712b12f17612804d48a6ec

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docs(build): update GCC to 12.2.Rel1 version

Updating toolchain to the latest production release version
12.2.Rel1 publicly available on https://developer.arm.com/

We build TF-A in CI using:
AArch3

docs(build): update GCC to 12.2.Rel1 version

Updating toolchain to the latest production release version
12.2.Rel1 publicly available on https://developer.arm.com/

We build TF-A in CI using:
AArch32 bare-metal target (arm-none-eabi)
AArch64 ELF bare-metal target (aarch64-none-elf)

Change-Id: Ib603cf7417e6878683a1100d5f55311188e36e8e
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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docs: update TZC secured DRAM map for FVP and Juno

Updated the documentation to include missing details about the
TZC secured DRAM mapping for the FVP and Juno platforms.

Change-Id: I10e59b9f9686fa

docs: update TZC secured DRAM map for FVP and Juno

Updated the documentation to include missing details about the
TZC secured DRAM mapping for the FVP and Juno platforms.

Change-Id: I10e59b9f9686fa2fef97f89864ebc272b10e5c0b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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docs(errata_abi): document the errata abi changes

Updated errata ABI feature enable flag and the errata non-arm
interconnect based flag, the default values for when the
feature is not enabled.

Chan

docs(errata_abi): document the errata abi changes

Updated errata ABI feature enable flag and the errata non-arm
interconnect based flag, the default values for when the
feature is not enabled.

Change-Id: Ieb2144a1bc38f4ed684fda8280842a18964ba148
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

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fix(cpus): workaround platforms non-arm interconnect

The workarounds for these below mentioned errata are not implemented
in EL3, but the flags can be enabled/disabled at a platform level
based on a

fix(cpus): workaround platforms non-arm interconnect

The workarounds for these below mentioned errata are not implemented
in EL3, but the flags can be enabled/disabled at a platform level
based on arm/non-arm interconnect IP. The ABI helps assist the Kernel
in the process of mitigation for the following errata:

Cortex-A715: erratum 2701951
Neoverse V2: erratum 2719103
Cortex-A710: erratum 2701952
Cortex-X2: erratum 2701952
Neoverse N2: erratum 2728475
Neoverse V1: erratum 2701953
Cortex-A78: erratum 2712571
Cortex-A78AE: erratum 2712574
Cortex-A78C: erratum 2712575

EL3 provides an appropriate return value via errata ABI when the
kernel makes an SMC call using the EM_CPU_ERRATUM_FEATURES FID with the
appropriate erratum ID.

Change-Id: I35bd69d812dba37410dd8bc2bbde20d4955b0850
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

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docs: update release and code freeze dates

Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Change-Id: If782bd337d10213cb74503f4ea54ed304d6e4c34

refactor(cm): make SVE and SME build dependencies logical

Currently, enabling SME forces SVE off. However, the SME enablement
requires SVE to be enabled, which is reflected in code. This is the
oppo

refactor(cm): make SVE and SME build dependencies logical

Currently, enabling SME forces SVE off. However, the SME enablement
requires SVE to be enabled, which is reflected in code. This is the
opposite of what the build flags require.

Further, the few platforms that enable SME also explicitly enable SVE.
Their platform.mk runs after the defaults.mk file so this override never
materializes. As a result, the override is only present on the
commandline.

Change it to something sensible where if SME is on then code can rely on
SVE being on too. Do this with a check in the Makefile as it is the more
widely used pattern. This maintains all valid use cases but subtly
changes corner cases no one uses at the moment to require a slightly
different combination of flags.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: If7ca3972ebc3c321e554533d7bc81af49c2472be

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Merge changes from topic "allwinner_t507" into integration

* changes:
feat(allwinner): add support for Allwinner T507 SoC
feat(allwinner): add function to detect H616 die variant
feat(allwinne

Merge changes from topic "allwinner_t507" into integration

* changes:
feat(allwinner): add support for Allwinner T507 SoC
feat(allwinner): add function to detect H616 die variant
feat(allwinner): add extra CPU control registers
refactor(allwinner): consolidate sunxi_cfg.h files

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Merge changes from topic "mp/group0_support" into integration

* changes:
docs(spm): support for handling Group0 interrupts
feat(spmd): introduce platform handler for Group0 interrupt
feat(spmd

Merge changes from topic "mp/group0_support" into integration

* changes:
docs(spm): support for handling Group0 interrupts
feat(spmd): introduce platform handler for Group0 interrupt
feat(spmd): add support for FFA_EL3_INTR_HANDLE_32 ABI
feat(spmd): register handler for group0 interrupt from NWd

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Merge changes I9d06e0ee,I6980e84f into integration

* changes:
feat(tegra): implement 'pwr_domain_off_early' handler
feat(psci): introduce 'pwr_domain_off_early' hook

Merge "feat(el3-runtime): handle traps for IMPDEF registers accesses" into integration

Merge "build: deprecate Arm rde1edge" into integration

Merge "docs(measured-boot): update the build command" into integration

docs(spm): support for handling Group0 interrupts

Please refer the doc update.

Change-Id: Ib79fae1296bc28fa9bd0cd79609d6153bb57519b
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

docs: fix rendering for code blocks in SPM

Two sample build command code blocks are not correctly
rendered by the documentation generator.

Fix that by adding newlines.

Signed-off-by: Nicola Mazzuc

docs: fix rendering for code blocks in SPM

Two sample build command code blocks are not correctly
rendered by the documentation generator.

Fix that by adding newlines.

Signed-off-by: Nicola Mazzucato <nicola.mazzucato@arm.com>
Change-Id: I1bb075ea4fc8e3230307548e40daecf2a79bae8d

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feat(el3-runtime): handle traps for IMPDEF registers accesses

This patch introduces support to handle traps from lower ELs for
IMPDEF system register accesses. The actual support is left to the
plat

feat(el3-runtime): handle traps for IMPDEF registers accesses

This patch introduces support to handle traps from lower ELs for
IMPDEF system register accesses. The actual support is left to the
platforms to implement.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I623d5c432b4ce4328b68f238c15b1c83df97c1e5

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docs: remove plat_convert_pk() interface from release doc

The code was already removed as part of commit 4ac5b3949d87
"refactor(auth): replace plat_convert_pk". The present commit just
removes it fr

docs: remove plat_convert_pk() interface from release doc

The code was already removed as part of commit 4ac5b3949d87
"refactor(auth): replace plat_convert_pk". The present commit just
removes it from the release documentation.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I06b35f110c844267d69a865df55dd451ed2f08cd

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Merge "docs(juno): refer to SCP v2.12.0" into integration