1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /******************************************************************************* 28 * MPIDR macros 29 ******************************************************************************/ 30 #define MPIDR_MT_MASK (ULL(1) << 24) 31 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 32 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 33 #define MPIDR_AFFINITY_BITS U(8) 34 #define MPIDR_AFFLVL_MASK ULL(0xff) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF1_SHIFT U(8) 37 #define MPIDR_AFF2_SHIFT U(16) 38 #define MPIDR_AFF3_SHIFT U(32) 39 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 40 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 41 #define MPIDR_AFFLVL_SHIFT U(3) 42 #define MPIDR_AFFLVL0 ULL(0x0) 43 #define MPIDR_AFFLVL1 ULL(0x1) 44 #define MPIDR_AFFLVL2 ULL(0x2) 45 #define MPIDR_AFFLVL3 ULL(0x3) 46 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 47 #define MPIDR_AFFLVL0_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL1_VAL(mpidr) \ 50 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 51 #define MPIDR_AFFLVL2_VAL(mpidr) \ 52 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 53 #define MPIDR_AFFLVL3_VAL(mpidr) \ 54 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 55 /* 56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 57 * add one while using this macro to define array sizes. 58 * TODO: Support only the first 3 affinity levels for now. 59 */ 60 #define MPIDR_MAX_AFFLVL U(2) 61 62 #define MPID_MASK (MPIDR_MT_MASK | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 67 68 #define MPIDR_AFF_ID(mpid, n) \ 69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 70 71 /* 72 * An invalid MPID. This value can be used by functions that return an MPID to 73 * indicate an error. 74 */ 75 #define INVALID_MPID U(0xFFFFFFFF) 76 77 /******************************************************************************* 78 * Definitions for CPU system register interface to GICv3 79 ******************************************************************************/ 80 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 81 #define ICC_SGI1R S3_0_C12_C11_5 82 #define ICC_ASGI1R S3_0_C12_C11_6 83 #define ICC_SRE_EL1 S3_0_C12_C12_5 84 #define ICC_SRE_EL2 S3_4_C12_C9_5 85 #define ICC_SRE_EL3 S3_6_C12_C12_5 86 #define ICC_CTLR_EL1 S3_0_C12_C12_4 87 #define ICC_CTLR_EL3 S3_6_C12_C12_4 88 #define ICC_PMR_EL1 S3_0_C4_C6_0 89 #define ICC_RPR_EL1 S3_0_C12_C11_3 90 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 91 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 92 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 93 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 94 #define ICC_IAR0_EL1 S3_0_c12_c8_0 95 #define ICC_IAR1_EL1 S3_0_c12_c12_0 96 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 97 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 98 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 99 100 /******************************************************************************* 101 * Definitions for EL2 system registers for save/restore routine 102 ******************************************************************************/ 103 #define CNTPOFF_EL2 S3_4_C14_C0_6 104 #define HAFGRTR_EL2 S3_4_C3_C1_6 105 #define HDFGRTR_EL2 S3_4_C3_C1_4 106 #define HDFGWTR_EL2 S3_4_C3_C1_5 107 #define HFGITR_EL2 S3_4_C1_C1_6 108 #define HFGRTR_EL2 S3_4_C1_C1_4 109 #define HFGWTR_EL2 S3_4_C1_C1_5 110 #define ICH_HCR_EL2 S3_4_C12_C11_0 111 #define ICH_VMCR_EL2 S3_4_C12_C11_7 112 #define MPAMVPM0_EL2 S3_4_C10_C6_0 113 #define MPAMVPM1_EL2 S3_4_C10_C6_1 114 #define MPAMVPM2_EL2 S3_4_C10_C6_2 115 #define MPAMVPM3_EL2 S3_4_C10_C6_3 116 #define MPAMVPM4_EL2 S3_4_C10_C6_4 117 #define MPAMVPM5_EL2 S3_4_C10_C6_5 118 #define MPAMVPM6_EL2 S3_4_C10_C6_6 119 #define MPAMVPM7_EL2 S3_4_C10_C6_7 120 #define MPAMVPMV_EL2 S3_4_C10_C4_1 121 #define TRFCR_EL2 S3_4_C1_C2_1 122 #define VNCR_EL2 S3_4_C2_C2_0 123 #define PMSCR_EL2 S3_4_C9_C9_0 124 #define TFSR_EL2 S3_4_C5_C6_0 125 #define CONTEXTIDR_EL2 S3_4_C13_C0_1 126 #define TTBR1_EL2 S3_4_C2_C0_1 127 128 /******************************************************************************* 129 * Generic timer memory mapped registers & offsets 130 ******************************************************************************/ 131 #define CNTCR_OFF U(0x000) 132 #define CNTCV_OFF U(0x008) 133 #define CNTFID_OFF U(0x020) 134 135 #define CNTCR_EN (U(1) << 0) 136 #define CNTCR_HDBG (U(1) << 1) 137 #define CNTCR_FCREQ(x) ((x) << 8) 138 139 /******************************************************************************* 140 * System register bit definitions 141 ******************************************************************************/ 142 /* CLIDR definitions */ 143 #define LOUIS_SHIFT U(21) 144 #define LOC_SHIFT U(24) 145 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 146 #define CLIDR_FIELD_WIDTH U(3) 147 148 /* CSSELR definitions */ 149 #define LEVEL_SHIFT U(1) 150 151 /* Data cache set/way op type defines */ 152 #define DCISW U(0x0) 153 #define DCCISW U(0x1) 154 #if ERRATA_A53_827319 155 #define DCCSW DCCISW 156 #else 157 #define DCCSW U(0x2) 158 #endif 159 160 #define ID_REG_FIELD_MASK ULL(0xf) 161 162 /* ID_AA64PFR0_EL1 definitions */ 163 #define ID_AA64PFR0_EL0_SHIFT U(0) 164 #define ID_AA64PFR0_EL1_SHIFT U(4) 165 #define ID_AA64PFR0_EL2_SHIFT U(8) 166 #define ID_AA64PFR0_EL3_SHIFT U(12) 167 168 #define ID_AA64PFR0_AMU_SHIFT U(44) 169 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 170 #define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0) 171 #define ID_AA64PFR0_AMU_V1 ULL(0x1) 172 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 173 174 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 175 176 #define ID_AA64PFR0_GIC_SHIFT U(24) 177 #define ID_AA64PFR0_GIC_WIDTH U(4) 178 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 179 180 #define ID_AA64PFR0_SVE_SHIFT U(32) 181 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 182 #define ID_AA64PFR0_SVE_SUPPORTED ULL(0x1) 183 #define ID_AA64PFR0_SVE_LENGTH U(4) 184 185 #define ID_AA64PFR0_SEL2_SHIFT U(36) 186 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 187 188 #define ID_AA64PFR0_MPAM_SHIFT U(40) 189 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 190 191 #define ID_AA64PFR0_DIT_SHIFT U(48) 192 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 193 #define ID_AA64PFR0_DIT_LENGTH U(4) 194 #define ID_AA64PFR0_DIT_SUPPORTED U(1) 195 196 #define ID_AA64PFR0_CSV2_SHIFT U(56) 197 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 198 #define ID_AA64PFR0_CSV2_LENGTH U(4) 199 #define ID_AA64PFR0_CSV2_2_SUPPORTED ULL(0x2) 200 201 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) 202 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) 203 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) 204 #define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0) 205 #define ID_AA64PFR0_FEAT_RME_V1 U(1) 206 207 #define ID_AA64PFR0_RAS_SHIFT U(28) 208 #define ID_AA64PFR0_RAS_MASK ULL(0xf) 209 #define ID_AA64PFR0_RAS_NOT_SUPPORTED ULL(0x0) 210 #define ID_AA64PFR0_RAS_LENGTH U(4) 211 212 /* Exception level handling */ 213 #define EL_IMPL_NONE ULL(0) 214 #define EL_IMPL_A64ONLY ULL(1) 215 #define EL_IMPL_A64_A32 ULL(2) 216 217 /* ID_AA64DFR0_EL1.TraceVer definitions */ 218 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 219 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 220 #define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1) 221 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 222 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) 223 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) 224 #define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1) 225 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) 226 #define ID_AA64DFR0_PMUVER_LENGTH U(4) 227 #define ID_AA64DFR0_PMUVER_SHIFT U(8) 228 #define ID_AA64DFR0_PMUVER_MASK U(0xf) 229 #define ID_AA64DFR0_PMUVER_PMUV3 U(1) 230 #define ID_AA64DFR0_PMUVER_PMUV3P7 U(7) 231 #define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf) 232 233 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 234 #define ID_AA64DFR0_PMS_SHIFT U(32) 235 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 236 #define ID_AA64DFR0_SPE_SUPPORTED ULL(0x1) 237 #define ID_AA64DFR0_SPE_NOT_SUPPORTED ULL(0x0) 238 239 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 240 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 241 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 242 #define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1) 243 244 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 245 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 246 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 247 #define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1) 248 #define ID_AA64DFR0_MTPMU_DISABLED ULL(15) 249 250 /* ID_AA64DFR0_EL1.BRBE definitions */ 251 #define ID_AA64DFR0_BRBE_SHIFT U(52) 252 #define ID_AA64DFR0_BRBE_MASK ULL(0xf) 253 #define ID_AA64DFR0_BRBE_SUPPORTED ULL(1) 254 255 /* ID_AA64ISAR0_EL1 definitions */ 256 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 257 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 258 259 /* ID_AA64ISAR1_EL1 definitions */ 260 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 261 262 #define ID_AA64ISAR1_GPI_SHIFT U(28) 263 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 264 #define ID_AA64ISAR1_GPA_SHIFT U(24) 265 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 266 267 #define ID_AA64ISAR1_API_SHIFT U(8) 268 #define ID_AA64ISAR1_API_MASK ULL(0xf) 269 #define ID_AA64ISAR1_APA_SHIFT U(4) 270 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 271 272 #define ID_AA64ISAR1_SB_SHIFT U(36) 273 #define ID_AA64ISAR1_SB_MASK ULL(0xf) 274 #define ID_AA64ISAR1_SB_SUPPORTED ULL(0x1) 275 #define ID_AA64ISAR1_SB_NOT_SUPPORTED ULL(0x0) 276 277 /* ID_AA64ISAR2_EL1 definitions */ 278 #define ID_AA64ISAR2_EL1 S3_0_C0_C6_2 279 280 /* ID_AA64PFR2_EL1 definitions */ 281 #define ID_AA64PFR2_EL1 S3_0_C0_C4_2 282 283 #define ID_AA64ISAR2_GPA3_SHIFT U(8) 284 #define ID_AA64ISAR2_GPA3_MASK ULL(0xf) 285 286 #define ID_AA64ISAR2_APA3_SHIFT U(12) 287 #define ID_AA64ISAR2_APA3_MASK ULL(0xf) 288 289 /* ID_AA64MMFR0_EL1 definitions */ 290 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 291 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 292 293 #define PARANGE_0000 U(32) 294 #define PARANGE_0001 U(36) 295 #define PARANGE_0010 U(40) 296 #define PARANGE_0011 U(42) 297 #define PARANGE_0100 U(44) 298 #define PARANGE_0101 U(48) 299 #define PARANGE_0110 U(52) 300 301 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 302 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 303 #define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0) 304 #define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1) 305 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 306 307 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 308 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 309 #define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1) 310 #define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0) 311 312 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 313 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 314 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) 315 #define ID_AA64MMFR0_EL1_TGRAN4_52B_SUPPORTED ULL(0x1) 316 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) 317 318 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 319 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 320 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) 321 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) 322 323 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 324 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 325 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) 326 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) 327 #define ID_AA64MMFR0_EL1_TGRAN16_52B_SUPPORTED ULL(0x2) 328 329 /* ID_AA64MMFR1_EL1 definitions */ 330 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 331 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 332 #define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1) 333 #define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0) 334 335 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 336 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 337 #define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0) 338 #define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1) 339 #define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2) 340 #define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3) 341 342 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 343 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 344 345 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) 346 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) 347 #define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1) 348 #define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0) 349 350 /* ID_AA64MMFR2_EL1 definitions */ 351 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 352 353 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 354 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 355 356 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) 357 #define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) 358 #define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) 359 360 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 361 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 362 363 #define ID_AA64MMFR2_EL1_NV_SHIFT U(24) 364 #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) 365 #define ID_AA64MMFR2_EL1_NV_NOT_SUPPORTED ULL(0x0) 366 #define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1) 367 #define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2) 368 369 /* ID_AA64MMFR3_EL1 definitions */ 370 #define ID_AA64MMFR3_EL1 S3_0_C0_C7_3 371 372 #define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20) 373 #define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf) 374 375 #define ID_AA64MMFR3_EL1_S1POE_SHIFT U(16) 376 #define ID_AA64MMFR3_EL1_S1POE_MASK ULL(0xf) 377 378 #define ID_AA64MMFR3_EL1_S2PIE_SHIFT U(12) 379 #define ID_AA64MMFR3_EL1_S2PIE_MASK ULL(0xf) 380 381 #define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8) 382 #define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf) 383 384 #define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0) 385 #define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf) 386 387 /* ID_AA64PFR1_EL1 definitions */ 388 #define ID_AA64PFR1_EL1_GCS_SHIFT U(44) 389 #define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf) 390 391 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 392 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 393 394 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ 395 396 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 397 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 398 399 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 400 401 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 402 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 403 404 #define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28) 405 #define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf) 406 407 #define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1) 408 #define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0) 409 410 /* ID_AA64PFR2_EL1 definitions */ 411 #define ID_AA64PFR2_EL1_MTEPERM_SHIFT U(0) 412 #define ID_AA64PFR2_EL1_MTEPERM_MASK ULL(0xf) 413 414 #define ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT U(4) 415 #define ID_AA64PFR2_EL1_MTESTOREONLY_MASK ULL(0xf) 416 417 #define ID_AA64PFR2_EL1_MTEFAR_SHIFT U(8) 418 #define ID_AA64PFR2_EL1_MTEFAR_MASK ULL(0xf) 419 420 #define VDISR_EL2 S3_4_C12_C1_1 421 #define VSESR_EL2 S3_4_C5_C2_3 422 423 /* Memory Tagging Extension is not implemented */ 424 #define MTE_UNIMPLEMENTED U(0) 425 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 426 #define MTE_IMPLEMENTED_EL0 U(1) 427 /* FEAT_MTE2: Full MTE is implemented */ 428 #define MTE_IMPLEMENTED_ELX U(2) 429 /* 430 * FEAT_MTE3: MTE is implemented with support for 431 * asymmetric Tag Check Fault handling 432 */ 433 #define MTE_IMPLEMENTED_ASY U(3) 434 435 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 436 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 437 438 #define ID_AA64PFR1_EL1_SME_SHIFT U(24) 439 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) 440 #define ID_AA64PFR1_EL1_SME_NOT_SUPPORTED ULL(0x0) 441 #define ID_AA64PFR1_EL1_SME_SUPPORTED ULL(0x1) 442 #define ID_AA64PFR1_EL1_SME2_SUPPORTED ULL(0x2) 443 444 /* ID_PFR1_EL1 definitions */ 445 #define ID_PFR1_VIRTEXT_SHIFT U(12) 446 #define ID_PFR1_VIRTEXT_MASK U(0xf) 447 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 448 & ID_PFR1_VIRTEXT_MASK) 449 450 /* SCTLR definitions */ 451 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 452 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 453 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 454 455 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 456 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 457 458 #define SCTLR_AARCH32_EL1_RES1 \ 459 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 460 (U(1) << 4) | (U(1) << 3)) 461 462 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 463 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 464 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 465 466 #define SCTLR_M_BIT (ULL(1) << 0) 467 #define SCTLR_A_BIT (ULL(1) << 1) 468 #define SCTLR_C_BIT (ULL(1) << 2) 469 #define SCTLR_SA_BIT (ULL(1) << 3) 470 #define SCTLR_SA0_BIT (ULL(1) << 4) 471 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 472 #define SCTLR_nAA_BIT (ULL(1) << 6) 473 #define SCTLR_ITD_BIT (ULL(1) << 7) 474 #define SCTLR_SED_BIT (ULL(1) << 8) 475 #define SCTLR_UMA_BIT (ULL(1) << 9) 476 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 477 #define SCTLR_EOS_BIT (ULL(1) << 11) 478 #define SCTLR_I_BIT (ULL(1) << 12) 479 #define SCTLR_EnDB_BIT (ULL(1) << 13) 480 #define SCTLR_DZE_BIT (ULL(1) << 14) 481 #define SCTLR_UCT_BIT (ULL(1) << 15) 482 #define SCTLR_NTWI_BIT (ULL(1) << 16) 483 #define SCTLR_NTWE_BIT (ULL(1) << 18) 484 #define SCTLR_WXN_BIT (ULL(1) << 19) 485 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 486 #define SCTLR_IESB_BIT (ULL(1) << 21) 487 #define SCTLR_EIS_BIT (ULL(1) << 22) 488 #define SCTLR_SPAN_BIT (ULL(1) << 23) 489 #define SCTLR_E0E_BIT (ULL(1) << 24) 490 #define SCTLR_EE_BIT (ULL(1) << 25) 491 #define SCTLR_UCI_BIT (ULL(1) << 26) 492 #define SCTLR_EnDA_BIT (ULL(1) << 27) 493 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 494 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 495 #define SCTLR_EnIB_BIT (ULL(1) << 30) 496 #define SCTLR_EnIA_BIT (ULL(1) << 31) 497 #define SCTLR_BT0_BIT (ULL(1) << 35) 498 #define SCTLR_BT1_BIT (ULL(1) << 36) 499 #define SCTLR_BT_BIT (ULL(1) << 36) 500 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 501 #define SCTLR_TCF0_SHIFT U(38) 502 #define SCTLR_TCF0_MASK ULL(3) 503 #define SCTLR_ENTP2_BIT (ULL(1) << 60) 504 505 /* Tag Check Faults in EL0 have no effect on the PE */ 506 #define SCTLR_TCF0_NO_EFFECT U(0) 507 /* Tag Check Faults in EL0 cause a synchronous exception */ 508 #define SCTLR_TCF0_SYNC U(1) 509 /* Tag Check Faults in EL0 are asynchronously accumulated */ 510 #define SCTLR_TCF0_ASYNC U(2) 511 /* 512 * Tag Check Faults in EL0 cause a synchronous exception on reads, 513 * and are asynchronously accumulated on writes 514 */ 515 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 516 517 #define SCTLR_TCF_SHIFT U(40) 518 #define SCTLR_TCF_MASK ULL(3) 519 520 /* Tag Check Faults in EL1 have no effect on the PE */ 521 #define SCTLR_TCF_NO_EFFECT U(0) 522 /* Tag Check Faults in EL1 cause a synchronous exception */ 523 #define SCTLR_TCF_SYNC U(1) 524 /* Tag Check Faults in EL1 are asynchronously accumulated */ 525 #define SCTLR_TCF_ASYNC U(2) 526 /* 527 * Tag Check Faults in EL1 cause a synchronous exception on reads, 528 * and are asynchronously accumulated on writes 529 */ 530 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 531 532 #define SCTLR_ATA0_BIT (ULL(1) << 42) 533 #define SCTLR_ATA_BIT (ULL(1) << 43) 534 #define SCTLR_DSSBS_SHIFT U(44) 535 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 536 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 537 #define SCTLR_TWEDEL_SHIFT U(46) 538 #define SCTLR_TWEDEL_MASK ULL(0xf) 539 #define SCTLR_EnASR_BIT (ULL(1) << 54) 540 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 541 #define SCTLR_EnALS_BIT (ULL(1) << 56) 542 #define SCTLR_EPAN_BIT (ULL(1) << 57) 543 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 544 545 /* CPACR_EL1 definitions */ 546 #define CPACR_EL1_FPEN(x) ((x) << 20) 547 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 548 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 549 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 550 #define CPACR_EL1_SMEN_SHIFT U(24) 551 #define CPACR_EL1_SMEN_MASK ULL(0x3) 552 553 /* SCR definitions */ 554 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 555 #define SCR_NSE_SHIFT U(62) 556 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) 557 #define SCR_GPF_BIT (UL(1) << 48) 558 #define SCR_TWEDEL_SHIFT U(30) 559 #define SCR_TWEDEL_MASK ULL(0xf) 560 #define SCR_PIEN_BIT (UL(1) << 45) 561 #define SCR_TCR2EN_BIT (UL(1) << 43) 562 #define SCR_TRNDR_BIT (UL(1) << 40) 563 #define SCR_GCSEn_BIT (UL(1) << 39) 564 #define SCR_HXEn_BIT (UL(1) << 38) 565 #define SCR_ENTP2_SHIFT U(41) 566 #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) 567 #define SCR_AMVOFFEN_SHIFT U(35) 568 #define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT) 569 #define SCR_TWEDEn_BIT (UL(1) << 29) 570 #define SCR_ECVEN_BIT (UL(1) << 28) 571 #define SCR_FGTEN_BIT (UL(1) << 27) 572 #define SCR_ATA_BIT (UL(1) << 26) 573 #define SCR_EnSCXT_BIT (UL(1) << 25) 574 #define SCR_FIEN_BIT (UL(1) << 21) 575 #define SCR_EEL2_BIT (UL(1) << 18) 576 #define SCR_API_BIT (UL(1) << 17) 577 #define SCR_APK_BIT (UL(1) << 16) 578 #define SCR_TERR_BIT (UL(1) << 15) 579 #define SCR_TWE_BIT (UL(1) << 13) 580 #define SCR_TWI_BIT (UL(1) << 12) 581 #define SCR_ST_BIT (UL(1) << 11) 582 #define SCR_RW_BIT (UL(1) << 10) 583 #define SCR_SIF_BIT (UL(1) << 9) 584 #define SCR_HCE_BIT (UL(1) << 8) 585 #define SCR_SMD_BIT (UL(1) << 7) 586 #define SCR_EA_BIT (UL(1) << 3) 587 #define SCR_FIQ_BIT (UL(1) << 2) 588 #define SCR_IRQ_BIT (UL(1) << 1) 589 #define SCR_NS_BIT (UL(1) << 0) 590 #define SCR_VALID_BIT_MASK U(0x24000002F8F) 591 #define SCR_RESET_VAL SCR_RES1_BITS 592 593 /* MDCR_EL3 definitions */ 594 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 595 #define MDCR_MPMX_BIT (ULL(1) << 35) 596 #define MDCR_MCCD_BIT (ULL(1) << 34) 597 #define MDCR_SBRBE_SHIFT U(32) 598 #define MDCR_SBRBE_MASK ULL(0x3) 599 #define MDCR_NSTB(x) ((x) << 24) 600 #define MDCR_NSTB_EL1 ULL(0x3) 601 #define MDCR_NSTBE_BIT (ULL(1) << 26) 602 #define MDCR_MTPME_BIT (ULL(1) << 28) 603 #define MDCR_TDCC_BIT (ULL(1) << 27) 604 #define MDCR_SCCD_BIT (ULL(1) << 23) 605 #define MDCR_EPMAD_BIT (ULL(1) << 21) 606 #define MDCR_EDAD_BIT (ULL(1) << 20) 607 #define MDCR_TTRF_BIT (ULL(1) << 19) 608 #define MDCR_STE_BIT (ULL(1) << 18) 609 #define MDCR_SPME_BIT (ULL(1) << 17) 610 #define MDCR_SDD_BIT (ULL(1) << 16) 611 #define MDCR_SPD32(x) ((x) << 14) 612 #define MDCR_SPD32_LEGACY ULL(0x0) 613 #define MDCR_SPD32_DISABLE ULL(0x2) 614 #define MDCR_SPD32_ENABLE ULL(0x3) 615 #define MDCR_NSPB(x) ((x) << 12) 616 #define MDCR_NSPB_EL1 ULL(0x3) 617 #define MDCR_NSPBE_BIT (ULL(1) << 11) 618 #define MDCR_TDOSA_BIT (ULL(1) << 10) 619 #define MDCR_TDA_BIT (ULL(1) << 9) 620 #define MDCR_TPM_BIT (ULL(1) << 6) 621 #define MDCR_EL3_RESET_VAL MDCR_MTPME_BIT 622 623 /* MDCR_EL2 definitions */ 624 #define MDCR_EL2_MTPME (U(1) << 28) 625 #define MDCR_EL2_HLP_BIT (U(1) << 26) 626 #define MDCR_EL2_E2TB(x) ((x) << 24) 627 #define MDCR_EL2_E2TB_EL1 U(0x3) 628 #define MDCR_EL2_HCCD_BIT (U(1) << 23) 629 #define MDCR_EL2_TTRF (U(1) << 19) 630 #define MDCR_EL2_HPMD_BIT (U(1) << 17) 631 #define MDCR_EL2_TPMS (U(1) << 14) 632 #define MDCR_EL2_E2PB(x) ((x) << 12) 633 #define MDCR_EL2_E2PB_EL1 U(0x3) 634 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 635 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 636 #define MDCR_EL2_TDA_BIT (U(1) << 9) 637 #define MDCR_EL2_TDE_BIT (U(1) << 8) 638 #define MDCR_EL2_HPME_BIT (U(1) << 7) 639 #define MDCR_EL2_TPM_BIT (U(1) << 6) 640 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 641 #define MDCR_EL2_HPMN_MASK U(0x1f) 642 #define MDCR_EL2_RESET_VAL U(0x0) 643 644 /* HSTR_EL2 definitions */ 645 #define HSTR_EL2_RESET_VAL U(0x0) 646 #define HSTR_EL2_T_MASK U(0xff) 647 648 /* CNTHP_CTL_EL2 definitions */ 649 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 650 #define CNTHP_CTL_RESET_VAL U(0x0) 651 652 /* VTTBR_EL2 definitions */ 653 #define VTTBR_RESET_VAL ULL(0x0) 654 #define VTTBR_VMID_MASK ULL(0xff) 655 #define VTTBR_VMID_SHIFT U(48) 656 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 657 #define VTTBR_BADDR_SHIFT U(0) 658 659 /* HCR definitions */ 660 #define HCR_RESET_VAL ULL(0x0) 661 #define HCR_AMVOFFEN_SHIFT U(51) 662 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) 663 #define HCR_TEA_BIT (ULL(1) << 47) 664 #define HCR_API_BIT (ULL(1) << 41) 665 #define HCR_APK_BIT (ULL(1) << 40) 666 #define HCR_E2H_BIT (ULL(1) << 34) 667 #define HCR_HCD_BIT (ULL(1) << 29) 668 #define HCR_TGE_BIT (ULL(1) << 27) 669 #define HCR_RW_SHIFT U(31) 670 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 671 #define HCR_TWE_BIT (ULL(1) << 14) 672 #define HCR_TWI_BIT (ULL(1) << 13) 673 #define HCR_AMO_BIT (ULL(1) << 5) 674 #define HCR_IMO_BIT (ULL(1) << 4) 675 #define HCR_FMO_BIT (ULL(1) << 3) 676 677 /* ISR definitions */ 678 #define ISR_A_SHIFT U(8) 679 #define ISR_I_SHIFT U(7) 680 #define ISR_F_SHIFT U(6) 681 682 /* CNTHCTL_EL2 definitions */ 683 #define CNTHCTL_RESET_VAL U(0x0) 684 #define EVNTEN_BIT (U(1) << 2) 685 #define EL1PCEN_BIT (U(1) << 1) 686 #define EL1PCTEN_BIT (U(1) << 0) 687 688 /* CNTKCTL_EL1 definitions */ 689 #define EL0PTEN_BIT (U(1) << 9) 690 #define EL0VTEN_BIT (U(1) << 8) 691 #define EL0PCTEN_BIT (U(1) << 0) 692 #define EL0VCTEN_BIT (U(1) << 1) 693 #define EVNTEN_BIT (U(1) << 2) 694 #define EVNTDIR_BIT (U(1) << 3) 695 #define EVNTI_SHIFT U(4) 696 #define EVNTI_MASK U(0xf) 697 698 /* CPTR_EL3 definitions */ 699 #define TCPAC_BIT (U(1) << 31) 700 #define TAM_SHIFT U(30) 701 #define TAM_BIT (U(1) << TAM_SHIFT) 702 #define TTA_BIT (U(1) << 20) 703 #define ESM_BIT (U(1) << 12) 704 #define TFP_BIT (U(1) << 10) 705 #define CPTR_EZ_BIT (U(1) << 8) 706 #define CPTR_EL3_RESET_VAL ((TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT) & \ 707 ~(CPTR_EZ_BIT | ESM_BIT)) 708 709 /* CPTR_EL2 definitions */ 710 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 711 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 712 #define CPTR_EL2_TAM_SHIFT U(30) 713 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) 714 #define CPTR_EL2_SMEN_MASK ULL(0x3) 715 #define CPTR_EL2_SMEN_SHIFT U(24) 716 #define CPTR_EL2_TTA_BIT (U(1) << 20) 717 #define CPTR_EL2_TSM_BIT (U(1) << 12) 718 #define CPTR_EL2_TFP_BIT (U(1) << 10) 719 #define CPTR_EL2_TZ_BIT (U(1) << 8) 720 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 721 722 /* VTCR_EL2 definitions */ 723 #define VTCR_RESET_VAL U(0x0) 724 #define VTCR_EL2_MSA (U(1) << 31) 725 726 /* CPSR/SPSR definitions */ 727 #define DAIF_FIQ_BIT (U(1) << 0) 728 #define DAIF_IRQ_BIT (U(1) << 1) 729 #define DAIF_ABT_BIT (U(1) << 2) 730 #define DAIF_DBG_BIT (U(1) << 3) 731 #define SPSR_DAIF_SHIFT U(6) 732 #define SPSR_DAIF_MASK U(0xf) 733 734 #define SPSR_AIF_SHIFT U(6) 735 #define SPSR_AIF_MASK U(0x7) 736 737 #define SPSR_E_SHIFT U(9) 738 #define SPSR_E_MASK U(0x1) 739 #define SPSR_E_LITTLE U(0x0) 740 #define SPSR_E_BIG U(0x1) 741 742 #define SPSR_T_SHIFT U(5) 743 #define SPSR_T_MASK U(0x1) 744 #define SPSR_T_ARM U(0x0) 745 #define SPSR_T_THUMB U(0x1) 746 747 #define SPSR_M_SHIFT U(4) 748 #define SPSR_M_MASK U(0x1) 749 #define SPSR_M_AARCH64 U(0x0) 750 #define SPSR_M_AARCH32 U(0x1) 751 #define SPSR_M_EL2H U(0x9) 752 753 #define SPSR_EL_SHIFT U(2) 754 #define SPSR_EL_WIDTH U(2) 755 756 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 757 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 758 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 759 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 760 761 #define SPSR_PAN_BIT BIT_64(22) 762 763 #define SPSR_DIT_BIT BIT(24) 764 765 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 766 767 #define DISABLE_ALL_EXCEPTIONS \ 768 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 769 770 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 771 772 /* 773 * RMR_EL3 definitions 774 */ 775 #define RMR_EL3_RR_BIT (U(1) << 1) 776 #define RMR_EL3_AA64_BIT (U(1) << 0) 777 778 /* 779 * HI-VECTOR address for AArch32 state 780 */ 781 #define HI_VECTOR_BASE U(0xFFFF0000) 782 783 /* 784 * TCR definitions 785 */ 786 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 787 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 788 #define TCR_EL1_IPS_SHIFT U(32) 789 #define TCR_EL2_PS_SHIFT U(16) 790 #define TCR_EL3_PS_SHIFT U(16) 791 792 #define TCR_TxSZ_MIN ULL(16) 793 #define TCR_TxSZ_MAX ULL(39) 794 #define TCR_TxSZ_MAX_TTST ULL(48) 795 796 #define TCR_T0SZ_SHIFT U(0) 797 #define TCR_T1SZ_SHIFT U(16) 798 799 /* (internal) physical address size bits in EL3/EL1 */ 800 #define TCR_PS_BITS_4GB ULL(0x0) 801 #define TCR_PS_BITS_64GB ULL(0x1) 802 #define TCR_PS_BITS_1TB ULL(0x2) 803 #define TCR_PS_BITS_4TB ULL(0x3) 804 #define TCR_PS_BITS_16TB ULL(0x4) 805 #define TCR_PS_BITS_256TB ULL(0x5) 806 807 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 808 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 809 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 810 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 811 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 812 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 813 814 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 815 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 816 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 817 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 818 819 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 820 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 821 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 822 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 823 824 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 825 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 826 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 827 828 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 829 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 830 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 831 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 832 833 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 834 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 835 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 836 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 837 838 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 839 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 840 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 841 842 #define TCR_TG0_SHIFT U(14) 843 #define TCR_TG0_MASK ULL(3) 844 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 845 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 846 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 847 848 #define TCR_TG1_SHIFT U(30) 849 #define TCR_TG1_MASK ULL(3) 850 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 851 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 852 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 853 854 #define TCR_EPD0_BIT (ULL(1) << 7) 855 #define TCR_EPD1_BIT (ULL(1) << 23) 856 857 #define MODE_SP_SHIFT U(0x0) 858 #define MODE_SP_MASK U(0x1) 859 #define MODE_SP_EL0 U(0x0) 860 #define MODE_SP_ELX U(0x1) 861 862 #define MODE_RW_SHIFT U(0x4) 863 #define MODE_RW_MASK U(0x1) 864 #define MODE_RW_64 U(0x0) 865 #define MODE_RW_32 U(0x1) 866 867 #define MODE_EL_SHIFT U(0x2) 868 #define MODE_EL_MASK U(0x3) 869 #define MODE_EL_WIDTH U(0x2) 870 #define MODE_EL3 U(0x3) 871 #define MODE_EL2 U(0x2) 872 #define MODE_EL1 U(0x1) 873 #define MODE_EL0 U(0x0) 874 875 #define MODE32_SHIFT U(0) 876 #define MODE32_MASK U(0xf) 877 #define MODE32_usr U(0x0) 878 #define MODE32_fiq U(0x1) 879 #define MODE32_irq U(0x2) 880 #define MODE32_svc U(0x3) 881 #define MODE32_mon U(0x6) 882 #define MODE32_abt U(0x7) 883 #define MODE32_hyp U(0xa) 884 #define MODE32_und U(0xb) 885 #define MODE32_sys U(0xf) 886 887 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 888 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 889 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 890 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 891 892 #define SPSR_64(el, sp, daif) \ 893 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 894 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 895 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 896 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 897 (~(SPSR_SSBS_BIT_AARCH64))) 898 899 #define SPSR_MODE32(mode, isa, endian, aif) \ 900 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 901 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 902 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 903 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 904 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 905 (~(SPSR_SSBS_BIT_AARCH32))) 906 907 /* 908 * TTBR Definitions 909 */ 910 #define TTBR_CNP_BIT ULL(0x1) 911 912 /* 913 * CTR_EL0 definitions 914 */ 915 #define CTR_CWG_SHIFT U(24) 916 #define CTR_CWG_MASK U(0xf) 917 #define CTR_ERG_SHIFT U(20) 918 #define CTR_ERG_MASK U(0xf) 919 #define CTR_DMINLINE_SHIFT U(16) 920 #define CTR_DMINLINE_MASK U(0xf) 921 #define CTR_L1IP_SHIFT U(14) 922 #define CTR_L1IP_MASK U(0x3) 923 #define CTR_IMINLINE_SHIFT U(0) 924 #define CTR_IMINLINE_MASK U(0xf) 925 926 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 927 928 /* Physical timer control register bit fields shifts and masks */ 929 #define CNTP_CTL_ENABLE_SHIFT U(0) 930 #define CNTP_CTL_IMASK_SHIFT U(1) 931 #define CNTP_CTL_ISTATUS_SHIFT U(2) 932 933 #define CNTP_CTL_ENABLE_MASK U(1) 934 #define CNTP_CTL_IMASK_MASK U(1) 935 #define CNTP_CTL_ISTATUS_MASK U(1) 936 937 /* Physical timer control macros */ 938 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 939 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 940 941 /* Exception Syndrome register bits and bobs */ 942 #define ESR_EC_SHIFT U(26) 943 #define ESR_EC_MASK U(0x3f) 944 #define ESR_EC_LENGTH U(6) 945 #define ESR_ISS_SHIFT U(0) 946 #define ESR_ISS_LENGTH U(25) 947 #define EC_UNKNOWN U(0x0) 948 #define EC_WFE_WFI U(0x1) 949 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 950 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 951 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 952 #define EC_AARCH32_CP14_LDC_STC U(0x6) 953 #define EC_FP_SIMD U(0x7) 954 #define EC_AARCH32_CP10_MRC U(0x8) 955 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 956 #define EC_ILLEGAL U(0xe) 957 #define EC_AARCH32_SVC U(0x11) 958 #define EC_AARCH32_HVC U(0x12) 959 #define EC_AARCH32_SMC U(0x13) 960 #define EC_AARCH64_SVC U(0x15) 961 #define EC_AARCH64_HVC U(0x16) 962 #define EC_AARCH64_SMC U(0x17) 963 #define EC_AARCH64_SYS U(0x18) 964 #define EC_IABORT_LOWER_EL U(0x20) 965 #define EC_IABORT_CUR_EL U(0x21) 966 #define EC_PC_ALIGN U(0x22) 967 #define EC_DABORT_LOWER_EL U(0x24) 968 #define EC_DABORT_CUR_EL U(0x25) 969 #define EC_SP_ALIGN U(0x26) 970 #define EC_AARCH32_FP U(0x28) 971 #define EC_AARCH64_FP U(0x2c) 972 #define EC_SERROR U(0x2f) 973 #define EC_BRK U(0x3c) 974 975 /* 976 * External Abort bit in Instruction and Data Aborts synchronous exception 977 * syndromes. 978 */ 979 #define ESR_ISS_EABORT_EA_BIT U(9) 980 981 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 982 983 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 984 #define RMR_RESET_REQUEST_SHIFT U(0x1) 985 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 986 987 /******************************************************************************* 988 * Definitions of register offsets, fields and macros for CPU system 989 * instructions. 990 ******************************************************************************/ 991 992 #define TLBI_ADDR_SHIFT U(12) 993 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 994 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 995 996 /******************************************************************************* 997 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 998 * system level implementation of the Generic Timer. 999 ******************************************************************************/ 1000 #define CNTCTLBASE_CNTFRQ U(0x0) 1001 #define CNTNSAR U(0x4) 1002 #define CNTNSAR_NS_SHIFT(x) (x) 1003 1004 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 1005 #define CNTACR_RPCT_SHIFT U(0x0) 1006 #define CNTACR_RVCT_SHIFT U(0x1) 1007 #define CNTACR_RFRQ_SHIFT U(0x2) 1008 #define CNTACR_RVOFF_SHIFT U(0x3) 1009 #define CNTACR_RWVT_SHIFT U(0x4) 1010 #define CNTACR_RWPT_SHIFT U(0x5) 1011 1012 /******************************************************************************* 1013 * Definitions of register offsets and fields in the CNTBaseN Frame of the 1014 * system level implementation of the Generic Timer. 1015 ******************************************************************************/ 1016 /* Physical Count register. */ 1017 #define CNTPCT_LO U(0x0) 1018 /* Counter Frequency register. */ 1019 #define CNTBASEN_CNTFRQ U(0x10) 1020 /* Physical Timer CompareValue register. */ 1021 #define CNTP_CVAL_LO U(0x20) 1022 /* Physical Timer Control register. */ 1023 #define CNTP_CTL U(0x2c) 1024 1025 /* PMCR_EL0 definitions */ 1026 #define PMCR_EL0_RESET_VAL U(0x0) 1027 #define PMCR_EL0_N_SHIFT U(11) 1028 #define PMCR_EL0_N_MASK U(0x1f) 1029 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 1030 #define PMCR_EL0_LP_BIT (U(1) << 7) 1031 #define PMCR_EL0_LC_BIT (U(1) << 6) 1032 #define PMCR_EL0_DP_BIT (U(1) << 5) 1033 #define PMCR_EL0_X_BIT (U(1) << 4) 1034 #define PMCR_EL0_D_BIT (U(1) << 3) 1035 #define PMCR_EL0_C_BIT (U(1) << 2) 1036 #define PMCR_EL0_P_BIT (U(1) << 1) 1037 #define PMCR_EL0_E_BIT (U(1) << 0) 1038 1039 /******************************************************************************* 1040 * Definitions for system register interface to SVE 1041 ******************************************************************************/ 1042 #define ZCR_EL3 S3_6_C1_C2_0 1043 #define ZCR_EL2 S3_4_C1_C2_0 1044 1045 /* ZCR_EL3 definitions */ 1046 #define ZCR_EL3_LEN_MASK U(0xf) 1047 1048 /* ZCR_EL2 definitions */ 1049 #define ZCR_EL2_LEN_MASK U(0xf) 1050 1051 /******************************************************************************* 1052 * Definitions for system register interface to SME as needed in EL3 1053 ******************************************************************************/ 1054 #define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 1055 #define SMCR_EL3 S3_6_C1_C2_6 1056 1057 /* ID_AA64SMFR0_EL1 definitions */ 1058 #define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63) 1059 #define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1) 1060 #define ID_AA64SMFR0_EL1_SME_FA64_SUPPORTED U(0x1) 1061 #define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55) 1062 #define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf) 1063 #define ID_AA64SMFR0_EL1_SME_INST_SUPPORTED ULL(0x0) 1064 #define ID_AA64SMFR0_EL1_SME2_INST_SUPPORTED ULL(0x1) 1065 1066 /* SMCR_ELx definitions */ 1067 #define SMCR_ELX_LEN_SHIFT U(0) 1068 #define SMCR_ELX_LEN_MAX U(0x1ff) 1069 #define SMCR_ELX_FA64_BIT (U(1) << 31) 1070 #define SMCR_ELX_EZT0_BIT (U(1) << 30) 1071 1072 /******************************************************************************* 1073 * Definitions of MAIR encodings for device and normal memory 1074 ******************************************************************************/ 1075 /* 1076 * MAIR encodings for device memory attributes. 1077 */ 1078 #define MAIR_DEV_nGnRnE ULL(0x0) 1079 #define MAIR_DEV_nGnRE ULL(0x4) 1080 #define MAIR_DEV_nGRE ULL(0x8) 1081 #define MAIR_DEV_GRE ULL(0xc) 1082 1083 /* 1084 * MAIR encodings for normal memory attributes. 1085 * 1086 * Cache Policy 1087 * WT: Write Through 1088 * WB: Write Back 1089 * NC: Non-Cacheable 1090 * 1091 * Transient Hint 1092 * NTR: Non-Transient 1093 * TR: Transient 1094 * 1095 * Allocation Policy 1096 * RA: Read Allocate 1097 * WA: Write Allocate 1098 * RWA: Read and Write Allocate 1099 * NA: No Allocation 1100 */ 1101 #define MAIR_NORM_WT_TR_WA ULL(0x1) 1102 #define MAIR_NORM_WT_TR_RA ULL(0x2) 1103 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 1104 #define MAIR_NORM_NC ULL(0x4) 1105 #define MAIR_NORM_WB_TR_WA ULL(0x5) 1106 #define MAIR_NORM_WB_TR_RA ULL(0x6) 1107 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 1108 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 1109 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 1110 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 1111 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 1112 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 1113 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 1114 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 1115 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 1116 1117 #define MAIR_NORM_OUTER_SHIFT U(4) 1118 1119 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 1120 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 1121 1122 /* PAR_EL1 fields */ 1123 #define PAR_F_SHIFT U(0) 1124 #define PAR_F_MASK ULL(0x1) 1125 #define PAR_ADDR_SHIFT U(12) 1126 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 1127 1128 /******************************************************************************* 1129 * Definitions for system register interface to SPE 1130 ******************************************************************************/ 1131 #define PMBLIMITR_EL1 S3_0_C9_C10_0 1132 1133 /******************************************************************************* 1134 * Definitions for system register interface, shifts and masks for MPAM 1135 ******************************************************************************/ 1136 #define MPAMIDR_EL1 S3_0_C10_C4_4 1137 #define MPAM2_EL2 S3_4_C10_C5_0 1138 #define MPAMHCR_EL2 S3_4_C10_C4_0 1139 #define MPAM3_EL3 S3_6_C10_C5_0 1140 1141 #define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(18) 1142 #define MPAMIDR_EL1_VPMR_MAX_MASK ULL(0x7) 1143 /******************************************************************************* 1144 * Definitions for system register interface to AMU for FEAT_AMUv1 1145 ******************************************************************************/ 1146 #define AMCR_EL0 S3_3_C13_C2_0 1147 #define AMCFGR_EL0 S3_3_C13_C2_1 1148 #define AMCGCR_EL0 S3_3_C13_C2_2 1149 #define AMUSERENR_EL0 S3_3_C13_C2_3 1150 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 1151 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 1152 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 1153 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 1154 1155 /* Activity Monitor Group 0 Event Counter Registers */ 1156 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 1157 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 1158 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 1159 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 1160 1161 /* Activity Monitor Group 0 Event Type Registers */ 1162 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 1163 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 1164 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 1165 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 1166 1167 /* Activity Monitor Group 1 Event Counter Registers */ 1168 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 1169 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 1170 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 1171 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 1172 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 1173 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 1174 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 1175 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 1176 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 1177 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 1178 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 1179 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 1180 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 1181 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 1182 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 1183 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 1184 1185 /* Activity Monitor Group 1 Event Type Registers */ 1186 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1187 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1188 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1189 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1190 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1191 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1192 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1193 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1194 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1195 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1196 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1197 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1198 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1199 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1200 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1201 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1202 1203 /* AMCNTENSET0_EL0 definitions */ 1204 #define AMCNTENSET0_EL0_Pn_SHIFT U(0) 1205 #define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff) 1206 1207 /* AMCNTENSET1_EL0 definitions */ 1208 #define AMCNTENSET1_EL0_Pn_SHIFT U(0) 1209 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) 1210 1211 /* AMCNTENCLR0_EL0 definitions */ 1212 #define AMCNTENCLR0_EL0_Pn_SHIFT U(0) 1213 #define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff) 1214 1215 /* AMCNTENCLR1_EL0 definitions */ 1216 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0) 1217 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) 1218 1219 /* AMCFGR_EL0 definitions */ 1220 #define AMCFGR_EL0_NCG_SHIFT U(28) 1221 #define AMCFGR_EL0_NCG_MASK U(0xf) 1222 #define AMCFGR_EL0_N_SHIFT U(0) 1223 #define AMCFGR_EL0_N_MASK U(0xff) 1224 1225 /* AMCGCR_EL0 definitions */ 1226 #define AMCGCR_EL0_CG0NC_SHIFT U(0) 1227 #define AMCGCR_EL0_CG0NC_MASK U(0xff) 1228 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1229 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1230 1231 /* MPAM register definitions */ 1232 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1233 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1234 1235 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1236 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1237 1238 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1239 1240 /******************************************************************************* 1241 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1242 ******************************************************************************/ 1243 1244 /* Definition for register defining which virtual offsets are implemented. */ 1245 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1246 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1247 #define AMCG1IDR_CTR_SHIFT U(0) 1248 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1249 #define AMCG1IDR_VOFF_SHIFT U(16) 1250 1251 /* New bit added to AMCR_EL0 */ 1252 #define AMCR_CG1RZ_SHIFT U(17) 1253 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) 1254 1255 /* 1256 * Definitions for virtual offset registers for architected activity monitor 1257 * event counters. 1258 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1259 */ 1260 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1261 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1262 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1263 1264 /* 1265 * Definitions for virtual offset registers for auxiliary activity monitor event 1266 * counters. 1267 */ 1268 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1269 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1270 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1271 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1272 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1273 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1274 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1275 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1276 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1277 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1278 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1279 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1280 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1281 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1282 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1283 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1284 1285 /******************************************************************************* 1286 * Realm management extension register definitions 1287 ******************************************************************************/ 1288 #define GPCCR_EL3 S3_6_C2_C1_6 1289 #define GPTBR_EL3 S3_6_C2_C1_4 1290 1291 #define SCXTNUM_EL2 S3_4_C13_C0_7 1292 1293 /******************************************************************************* 1294 * RAS system registers 1295 ******************************************************************************/ 1296 #define DISR_EL1 S3_0_C12_C1_1 1297 #define DISR_A_BIT U(31) 1298 1299 #define ERRIDR_EL1 S3_0_C5_C3_0 1300 #define ERRIDR_MASK U(0xffff) 1301 1302 #define ERRSELR_EL1 S3_0_C5_C3_1 1303 1304 /* System register access to Standard Error Record registers */ 1305 #define ERXFR_EL1 S3_0_C5_C4_0 1306 #define ERXCTLR_EL1 S3_0_C5_C4_1 1307 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1308 #define ERXADDR_EL1 S3_0_C5_C4_3 1309 #define ERXPFGF_EL1 S3_0_C5_C4_4 1310 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1311 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1312 #define ERXMISC0_EL1 S3_0_C5_C5_0 1313 #define ERXMISC1_EL1 S3_0_C5_C5_1 1314 1315 #define ERXCTLR_ED_SHIFT U(0) 1316 #define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) 1317 #define ERXCTLR_UE_BIT (U(1) << 4) 1318 1319 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1320 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1321 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1322 1323 /******************************************************************************* 1324 * Armv8.3 Pointer Authentication Registers 1325 ******************************************************************************/ 1326 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1327 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1328 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1329 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1330 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1331 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1332 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1333 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1334 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1335 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1336 1337 /******************************************************************************* 1338 * Armv8.4 Data Independent Timing Registers 1339 ******************************************************************************/ 1340 #define DIT S3_3_C4_C2_5 1341 #define DIT_BIT BIT(24) 1342 1343 /******************************************************************************* 1344 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1345 ******************************************************************************/ 1346 #define SSBS S3_3_C4_C2_6 1347 1348 /******************************************************************************* 1349 * Armv8.5 - Memory Tagging Extension Registers 1350 ******************************************************************************/ 1351 #define TFSRE0_EL1 S3_0_C5_C6_1 1352 #define TFSR_EL1 S3_0_C5_C6_0 1353 #define RGSR_EL1 S3_0_C1_C0_5 1354 #define GCR_EL1 S3_0_C1_C0_6 1355 1356 /******************************************************************************* 1357 * Armv8.5 - Random Number Generator Registers 1358 ******************************************************************************/ 1359 #define RNDR S3_3_C2_C4_0 1360 #define RNDRRS S3_3_C2_C4_1 1361 1362 /******************************************************************************* 1363 * FEAT_HCX - Extended Hypervisor Configuration Register 1364 ******************************************************************************/ 1365 #define HCRX_EL2 S3_4_C1_C2_2 1366 #define HCRX_EL2_MSCEn_BIT (UL(1) << 11) 1367 #define HCRX_EL2_MCE2_BIT (UL(1) << 10) 1368 #define HCRX_EL2_CMOW_BIT (UL(1) << 9) 1369 #define HCRX_EL2_VFNMI_BIT (UL(1) << 8) 1370 #define HCRX_EL2_VINMI_BIT (UL(1) << 7) 1371 #define HCRX_EL2_TALLINT_BIT (UL(1) << 6) 1372 #define HCRX_EL2_SMPME_BIT (UL(1) << 5) 1373 #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) 1374 #define HCRX_EL2_FnXS_BIT (UL(1) << 3) 1375 #define HCRX_EL2_EnASR_BIT (UL(1) << 2) 1376 #define HCRX_EL2_EnALS_BIT (UL(1) << 1) 1377 #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) 1378 #define HCRX_EL2_INIT_VAL ULL(0x0) 1379 1380 /******************************************************************************* 1381 * FEAT_TCR2 - Extended Translation Control Register 1382 ******************************************************************************/ 1383 #define TCR2_EL2 S3_4_C2_C0_3 1384 1385 /******************************************************************************* 1386 * Permission indirection and overlay 1387 ******************************************************************************/ 1388 1389 #define PIRE0_EL2 S3_4_C10_C2_2 1390 #define PIR_EL2 S3_4_C10_C2_3 1391 #define POR_EL2 S3_4_C10_C2_4 1392 #define S2PIR_EL2 S3_4_C10_C2_5 1393 1394 /******************************************************************************* 1395 * FEAT_GCS - Guarded Control Stack Registers 1396 ******************************************************************************/ 1397 #define GCSCR_EL2 S3_4_C2_C5_0 1398 #define GCSPR_EL2 S3_4_C2_C5_1 1399 1400 /******************************************************************************* 1401 * Definitions for DynamicIQ Shared Unit registers 1402 ******************************************************************************/ 1403 #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 1404 1405 /* CLUSTERPWRDN_EL1 register definitions */ 1406 #define DSU_CLUSTER_PWR_OFF 0 1407 #define DSU_CLUSTER_PWR_ON 1 1408 #define DSU_CLUSTER_PWR_MASK U(1) 1409 1410 /******************************************************************************* 1411 * Definitions for CPU Power/Performance Management registers 1412 ******************************************************************************/ 1413 1414 #define CPUPPMCR_EL3 S3_6_C15_C2_0 1415 #define CPUPPMCR_EL3_MPMMPINCTL_SHIFT UINT64_C(0) 1416 #define CPUPPMCR_EL3_MPMMPINCTL_MASK UINT64_C(0x1) 1417 1418 #define CPUMPMMCR_EL3 S3_6_C15_C2_1 1419 #define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0) 1420 #define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1) 1421 1422 /* alternative system register encoding for the "sb" speculation barrier */ 1423 #define SYSREG_SB S0_3_C3_C0_7 1424 1425 #endif /* ARCH_H */ 1426