docs(fvp): update model version documentation

This change updates the model versions that we claim to be testing with
to reflect what the reality in the CI.

Change-Id: Ieb44f3f21cd0ba7149d47f768869

docs(fvp): update model version documentation

This change updates the model versions that we claim to be testing with
to reflect what the reality in the CI.

Change-Id: Ieb44f3f21cd0ba7149d47f7688698831c9eab487
Signed-off-by: Chris Kay <chris.kay@arm.com>

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docs(juno): update PSCI instrumentation data

Change-Id: Iadbaf3d52c5e86f53b05c09e2decce3c089ab83c
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

docs(n1sdp): update N1SDP PSCI instrumentation data

Change-Id: I11c747acfdd376668b44a116258ee75e8cba214d
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

Merge changes from topic "od/hf-doc-migration" into integration

* changes:
docs(spm-mm): remove reference to SEL2 SPMC
docs: remove SEL2 SPMC threat model
docs: remove unused SPM related diagr

Merge changes from topic "od/hf-doc-migration" into integration

* changes:
docs(spm-mm): remove reference to SEL2 SPMC
docs: remove SEL2 SPMC threat model
docs: remove unused SPM related diagrams

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docs(threat-model): add a threat model for TF-A with Arm CCA

Arm Confidential Compute Architecture (Arm CCA) support, underpinned by
Arm Realm Management Extension (RME) support, brings in a few imp

docs(threat-model): add a threat model for TF-A with Arm CCA

Arm Confidential Compute Architecture (Arm CCA) support, underpinned by
Arm Realm Management Extension (RME) support, brings in a few important
software and hardware architectural changes in TF-A, which warrants a
new security analysis of the code base. Results of this analysis are
captured in a new threat model document, provided in this patch.

The main changes introduced in TF-A to support Arm CCA / RME are:

- Presence of a new threat agent: realm world clients.

- Availability of Arm CCA Hardware Enforced Security (HES) to support
measured boot and trusted boot.

- Configuration of the Granule Protection Tables (GPT) for
inter-world memory protection.

This is only an initial version of the threat model and we expect to
enrich it in the future.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Co-authored-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Iab84dc724df694511508f90dc76b6d469c4cccd5

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refactor(fvp): remove RSS usage

Removed RSS usage from the Base AEM FVP platform, as it wasn't
functional on this platform. The Base AEM FVP platform lacks
support for RSS.
Instead, the TC2 platform

refactor(fvp): remove RSS usage

Removed RSS usage from the Base AEM FVP platform, as it wasn't
functional on this platform. The Base AEM FVP platform lacks
support for RSS.
Instead, the TC2 platform with RSS is available for actual RSS
interface implementation and testing.

Change-Id: I8f68157319399ab526f9e851b26dba903db5c2e7
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "docs(threat-model): cover threats inherent to receiving data over UART" into integration

refactor(rss)!: remove PLAT_RSS_NOT_SUPPORTED build option

Removed the PLAT_RSS_NOT_SUPPORTED build option, which was initially
introduced for building the Base AEM FVP platform platform with RSS.
H

refactor(rss)!: remove PLAT_RSS_NOT_SUPPORTED build option

Removed the PLAT_RSS_NOT_SUPPORTED build option, which was initially
introduced for building the Base AEM FVP platform platform with RSS.
However, we now have a well-defined TC2 platform with RSS, making it
unnecessary to keep this flag.

Note -
Theoretically this is a breaking change. Other platforms could be
using the PLAT_RSS_NOT_SUPPORTED build option. Among upstream platforms,
only the Base AEM FVP uses it right now but we don't know about
downstream platforms.

Change-Id: I931905a4c6ac1ebe3895ab6e0287d0fa07721707
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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build(mbedtls): add deprecation notice

Add a deprecation notice for building TF-A with mbedtls-2.x
This was notified earlier in TF-A mailing list:

https://lists.trustedfirmware.org/archives/list/tf

build(mbedtls): add deprecation notice

Add a deprecation notice for building TF-A with mbedtls-2.x
This was notified earlier in TF-A mailing list:

https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.org/message/YDPOPASMGEQBCOI5TKUSD3V3J75NAT7A/

We will be removing support to build TF-A with mbedtls-2.x after
TF-A 2.10 release.

Change-Id: I669b423ee9af9f5c5255fce370413fffaf38e8eb
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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docs(threat-model): cover threats inherent to receiving data over UART

TF-A supports reading input data from UART interfaces. This opens up
an attack vector for arbitrary data to be injected into TF

docs(threat-model): cover threats inherent to receiving data over UART

TF-A supports reading input data from UART interfaces. This opens up
an attack vector for arbitrary data to be injected into TF-A, which is
not covered in the threat model right now.

Fill this gap by:

- Updating the data flow diagrams. Data may flow from the UART into
TF-A (and not only the other way around).

- Documenting the threats inherent to reading untrusted data from a
UART.

Change-Id: I508da5d2f7ad5d20717b958d76ab9337c5eca50f
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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chore(auth)!: remove CryptoCell-712/713 support

CryptoCell-712 and CryptoCell-713 drivers have been deprecated since
TF-A v2.9 and their removal was announced for TF-A v2.10 release.
See [1].

As th

chore(auth)!: remove CryptoCell-712/713 support

CryptoCell-712 and CryptoCell-713 drivers have been deprecated since
TF-A v2.9 and their removal was announced for TF-A v2.10 release.
See [1].

As the release is approaching, this patch deletes these drivers' code as
well as all references to them in the documentation and Arm platforms
code (Nuvoton platform is taken care in a subsequent patch). Associated
build options (ARM_CRYPTOCELL_INTEG and PLAT_CRYPTOCELL_BASE) have also
been removed and thus will have no effect if defined.

This is a breaking change for downstream platforms which use these
drivers.

[1] https://trustedfirmware-a.readthedocs.io/en/v2.9/about/release-information.html#removal-of-deprecated-drivers
Note that TF-A v3.0 release later got renumbered into v2.10.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: Idabbc9115f6732ac1a0e52b273d3380677a39813

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Merge "refactor(cm): introduce INIT_UNUSED_NS_EL2 macro" into integration

Merge "fix(el3-spmc): remove experimental flag" into integration

fix(el3-spmc): remove experimental flag

The EL3 SPMC is known to be deployed into end products and properly
tested since its introduction into TF-A v2.7.

Signed-off-by: Olivier Deprez <olivier.depr

fix(el3-spmc): remove experimental flag

The EL3 SPMC is known to be deployed into end products and properly
tested since its introduction into TF-A v2.7.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I96bb897cfefef20c33cfc39627b10746dce5485c

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feat(docs): save BL32 image base and size in entry point info

There is no platform function to retrieve the info in the generic code.
Populate the BL32 image base, size and max limit in arg2, arg3 a

feat(docs): save BL32 image base and size in entry point info

There is no platform function to retrieve the info in the generic code.
Populate the BL32 image base, size and max limit in arg2, arg3 and arg4.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I35527fb41829102083b488a5150c0c707c5ede15

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refactor(cm): introduce INIT_UNUSED_NS_EL2 macro

Introducing INIT_UNUSED_NS_EL2 macro which guards the code that
disables the unused EL2 when a platform hands off from EL3
to NS-EL1 instead of NS-EL

refactor(cm): introduce INIT_UNUSED_NS_EL2 macro

Introducing INIT_UNUSED_NS_EL2 macro which guards the code that
disables the unused EL2 when a platform hands off from EL3
to NS-EL1 instead of NS-EL2. Platforms without NS-EL2 in use
must enable this flag.

BREAKING CHANGE: Initialisation code for handoff from EL3 to NS-EL1
disabled by default. Platforms which do that need to enable this macro
going forward

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I61431cc4f7e2feb568d472828e5fd79cc73e51f5

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Merge changes from topic "errata" into integration

* changes:
fix(cpus): workaround for Cortex-X2 erratum 2742423
fix(cpus): workaround for Cortex-A710 erratum 2742423
fix(cpus): workaround fo

Merge changes from topic "errata" into integration

* changes:
fix(cpus): workaround for Cortex-X2 erratum 2742423
fix(cpus): workaround for Cortex-A710 erratum 2742423
fix(cpus): workaround for Neoverse N2 erratum 2340933
fix(cpus): workaround for Neoverse N2 erratum 2346952

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Merge "docs: add TF-A version numbering information" into integration

Merge changes from topic "xlnx_tsp_feat" into integration

* changes:
docs(versal-net): add TSP build documentation
docs(versal): add TSP build documentation
feat(versal-net): add tsp support

Merge changes from topic "xlnx_tsp_feat" into integration

* changes:
docs(versal-net): add TSP build documentation
docs(versal): add TSP build documentation
feat(versal-net): add tsp support
feat(versal): add tsp support
refactor(xilinx): add generic TSP makefile
chore(zynqmp): reorganize tsp code into common path
refactor(xilinx): rename platform function to generic name

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docs: add TF-A version numbering information

Add a chapter "Version numbering" in release information file that
explains macros used for TF-A version. It also introduces VERSION_PATCH
macro that is

docs: add TF-A version numbering information

Add a chapter "Version numbering" in release information file that
explains macros used for TF-A version. It also introduces VERSION_PATCH
macro that is used for LTS releases. A comment for this macro is also
added in Makefile.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I946b6cb91bb8454131f07b24534d28ab1aef1771

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fix(cpus): workaround for Cortex-X2 erratum 2742423

Cortex-X2 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open.
The workaround is to set CPUACTLR5_EL1[56:55

fix(cpus): workaround for Cortex-X2 erratum 2742423

Cortex-X2 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open.
The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest

Change-Id: I03897dc2a7f908937612c2b66ce7a043c1b7575d
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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fix(cpus): workaround for Cortex-A710 erratum 2742423

Cortex-A710 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open. The workaround is to set
CPUACTLR5_EL1[5

fix(cpus): workaround for Cortex-A710 erratum 2742423

Cortex-A710 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open. The workaround is to set
CPUACTLR5_EL1[56:55] to 2'b01.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest

Change-Id: I4d9d3760491f1e6c59b2667c16d59b99cc7979f1
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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fix(cpus): workaround for Neoverse N2 erratum 2340933

Neoverse N2 erratum 2340933 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1. The workaround is to set
CPUACTLR5_EL1[61] to

fix(cpus): workaround for Neoverse N2 erratum 2340933

Neoverse N2 erratum 2340933 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1. The workaround is to set
CPUACTLR5_EL1[61] to 1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1982442/latest

Change-Id: I121add0dd35072c53392d33f049d893a5ff6354f
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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fix(cpus): workaround for Neoverse N2 erratum 2346952

Neoverse N2 erratum 2346952 is a Cat B erratum that applies to all
revisions <= r0p2 and is fixed in r0p3.
The workaround is to set L2 TQ size s

fix(cpus): workaround for Neoverse N2 erratum 2346952

Neoverse N2 erratum 2346952 is a Cat B erratum that applies to all
revisions <= r0p2 and is fixed in r0p3.
The workaround is to set L2 TQ size statically to it's full size.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1982442/latest

Change-Id: I03c3cf1f951fbc906fdebcb99a523c5ac8ba055d
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>

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Merge changes from topic "mp/exceptions" into integration

* changes:
docs(ras): update RAS documentation
docs(el3-runtime): update BL31 exception vector handling
fix(el3-runtime): restrict low

Merge changes from topic "mp/exceptions" into integration

* changes:
docs(ras): update RAS documentation
docs(el3-runtime): update BL31 exception vector handling
fix(el3-runtime): restrict lower el EA handlers in FFH mode
fix(ras): remove RAS_FFH_SUPPORT and introduce FFH_SUPPORT
fix(ras): restrict ENABLE_FEAT_RAS to have only two states
feat(ras): use FEAT_IESB for error synchronization
feat(el3-runtime): modify vector entry paths

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