Allow style checking of tree and local changes

New phony Makefile targets have been added:

* checkcodebase
* checkpatch

The checkcodebase target will run a Linux style compliance check over the

Allow style checking of tree and local changes

New phony Makefile targets have been added:

* checkcodebase
* checkpatch

The checkcodebase target will run a Linux style compliance check over the
entire codebase, and honours the V=1 Makefile verbose setting and so will
show more information when this is enabled.

If the local directory is a git checkout then the output of git ls-files is
used to decide which files to test for compliance. If the local directory
is not under git control then a 'best attempt' is made, but in this case it
should be noted that it is possible for additional non-codebase files to be
tested, so care should be taken when parsing the output.

The checkpatch target will compare local changes against the git origin/master
to allow issues with the last set of changes to be identified. To override
the change comparision location, set the BASE_COMMIT variable to your
desired git branch.

Both targets rely on the Linux source tree script checkpatch.pl to do the
syntax checking, and expects that the CHECKPATCH environment variable points
to the location of this file.

Notes on the usage of these targets have been added to the contributing.md
and docs/user-guide.md text files.

Change-Id: I6d73c97af578e24a34226d972afadab9d30f1d8d

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psci: fix affinity level upgrade issue

The psci implementation does not track target affinity level requests
specified during cpu_suspend calls correctly as per the following
example.

1. cpu0.clust

psci: fix affinity level upgrade issue

The psci implementation does not track target affinity level requests
specified during cpu_suspend calls correctly as per the following
example.

1. cpu0.cluster0 calls cpu_suspend with the target affinity level as 0
2. Only the cpu0.cluster0 is powered down while cluster0 remains
powered up
3. cpu1.cluster0 calls cpu_off to power itself down to highest
possible affinity level
4. cluster0 will be powered off even though cpu0.cluster0 does not
allow cluster shutdown

This patch introduces reference counts at affinity levels > 0 to track
the number of cpus which want an affinity instance at level X to
remain powered up. This instance can be turned off only if its
reference count is 0. Cpus still undergo the normal state transitions
(ON, OFF, ON_PENDING, SUSPEND) but the higher levels can only be
either ON or OFF depending upon their reference count.

The above issue is thus fixed as follows:

1. cluster0's reference count is incremented by two when cpu0 and cpu1
are initially powered on.

2. cpu0.cluster0 calls cpu_suspend with the target affinity level as
0. This does not affect the cluster0 reference count.

3. Only the cpu0.cluster0 is powered down while cluster0 remains
powered up as it has a non-zero reference count.

4. cpu1.cluster0 call cpu_off to power itself down to highest possible
affinity level. This decrements the cluster0 reference count.

5. cluster0 is still not powered off since its reference count will at
least be 1 due to the restriction placed by cpu0.

Change-Id: I433dfe82b946f5f6985b1602c2de87800504f7a9

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fvp: rename fvp_* files to plat_*

The FVP platform has a few filenames that begin with fvp_. These are
renamed to plat_ to make it easier to use the FVP port as a template.

Change-Id: I601e6256d5e

fvp: rename fvp_* files to plat_*

The FVP platform has a few filenames that begin with fvp_. These are
renamed to plat_ to make it easier to use the FVP port as a template.

Change-Id: I601e6256d5ef3bae81a2e1f5df6de56db5b27069
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>

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Build system: Fixes #2: Add multi-platform support

Move all explicit platform or architecture specific references
into a new platform.mk file that is defined for each platform.

Change-Id: I9d6320d1

Build system: Fixes #2: Add multi-platform support

Move all explicit platform or architecture specific references
into a new platform.mk file that is defined for each platform.

Change-Id: I9d6320d1ba957e0cc8d9b316b3578132331fa428
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>

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Probe for GICv3 re-distributors on core bring-up

The GICv3 distributor can have more ports than CPUs are available in
the system. Probe all re-distributors and use the matching affinity
levels as sp

Probe for GICv3 re-distributors on core bring-up

The GICv3 distributor can have more ports than CPUs are available in
the system. Probe all re-distributors and use the matching affinity
levels as specified by each core and re-distributor to decide which
re-distributor to use with which CPU core.

If a core cannot be matched with a re-distributor, the core panics and
is placed in an endless loop.

Change-Id: Ie393cfe07c7449a2383959e3c968664882e18afc

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Do not trap access to floating point registers

Traps when accessing architectural features are disabled by clearing bits
in CPTR_EL3 during early boot, including accesses to floating point
registers

Do not trap access to floating point registers

Traps when accessing architectural features are disabled by clearing bits
in CPTR_EL3 during early boot, including accesses to floating point
registers. The value of this register was previously undetermined, causing
unwanted traps to EL3. Future EL3 code (for example, context save/restore
code) may use floating point registers, although they are not used by current
code.

Also, the '-mgeneral-regs-only' flag is enabled in the GCC settings to
prevent generation of code that uses floating point registers.

Change-Id: I9a03675f6387bbbee81a6f2c9ccf81150db03747

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Update year in copyright text to 2014

Change-Id: Ic7fb61aabae1d515b9e6baf3dd003807ff42da60

Refer to separate issue tracking repository

Update documentation to refer to separate issue tracking
repository, https://github.com/ARM-software/tf-issues/issues.

Change-Id: Ib1cef65b0da420bec58290

Refer to separate issue tracking repository

Update documentation to refer to separate issue tracking
repository, https://github.com/ARM-software/tf-issues/issues.

Change-Id: Ib1cef65b0da420bec58290d8743eb069b1226c96

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Do not let GCC use built-in functions

In order to reduce the software dependency on the compiler, the project
is now compiled with the '-ffreestanding' flag. This is to prevent GCC
from replacing fu

Do not let GCC use built-in functions

In order to reduce the software dependency on the compiler, the project
is now compiled with the '-ffreestanding' flag. This is to prevent GCC
from replacing functions with more optimised versions. An example is
where GCC replaces a simple printf() with a puts().

Change-Id: I1973fe6957cd708e8432a0039af9d50e037bd884

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Local C library documentation updates

- Update porting guide to describe where files live and how to get
FreeBSD source code.
- Update change-log to describe relocation and new functions.

Change-

Local C library documentation updates

- Update porting guide to describe where files live and how to get
FreeBSD source code.
- Update change-log to describe relocation and new functions.

Change-Id: Id8f30cc7bafdd1064b3a5c5aae958c5aa3fb79f3

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Remove useless copies of meminfo structures

Platform setup code has to reserve some memory for storing the
memory layout information. It is populated in early platform setup
code.

blx_get_sec_mem_

Remove useless copies of meminfo structures

Platform setup code has to reserve some memory for storing the
memory layout information. It is populated in early platform setup
code.

blx_get_sec_mem_layout() functions used to return a copy of this
structure. This patch modifies blx_get_sec_mem_layout() functions
so that they now directly return a pointer to their memory layout
structure. It ensures that the memory layout returned by
blx_get_sec_mem_layout() is always up-to-date and also avoids a
useless copy of the meminfo structure.

Also rename blx_get_sec_mem_layout() to blx_plat_sec_mem_layout()
to make it clear those functions are platform specific.

Change-Id: Ic7a6f9d6b6236b14865ab48a9f5eff545ce56551

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psci: update docs with status of cpu_suspend api

This patch makes changes to the documents to reflect the current
state of play of the psci cpu_suspend function.

Change-Id: I086509fb75111b6e9f93b7f

psci: update docs with status of cpu_suspend api

This patch makes changes to the documents to reflect the current
state of play of the psci cpu_suspend function.

Change-Id: I086509fb75111b6e9f93b7f6dbcd33cc4591b9f3

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remove check on non-secure entrypoint parameter

In fvp_affinst_on/suspend, the non-secure entrypoint is always
expected to lie in the DRAM. This check will not be valid if
non-secure code executes d

remove check on non-secure entrypoint parameter

In fvp_affinst_on/suspend, the non-secure entrypoint is always
expected to lie in the DRAM. This check will not be valid if
non-secure code executes directly out of flash e.g. a baremetal
test. This patch removes this check.

Change-Id: I0436e1138fc394aae8ff1ea59ebe38b46a440b61

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psci: fix error due to a non zero context id

In the previous psci implementation, the psci_afflvl_power_on_finish()
function would run into an error condition if the value of the context
id paramete

psci: fix error due to a non zero context id

In the previous psci implementation, the psci_afflvl_power_on_finish()
function would run into an error condition if the value of the context
id parameter in the cpu_on and cpu_suspend psci calls was != 0. The
parameter was being restored as the return value of the affinity level
0 finisher function. A non zero context id would be treated as an
error condition. This would prevent successful wake up of the cpu from
a power down state. Also, the contents of the general purpose
registers were not being cleared upon return to the non-secure world
after a cpu power up. This could potentially allow the non-secure
world to view secure data.

This patch ensures that all general purpose registers are set to ~0
prior to the final eret that drops the execution to the non-secure
world. The context id is used to initialize the general purpose
register x0 prior to re-entry into the non-secure world and is no
longer restored as a function return value. A platform helper
(platform_get_stack()) has been introduced to facilitate this change.

Change-Id: I2454911ffd75705d6aa8609a5d250d9b26fa097c

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psci: fix values of incorrectly defined constants

This patch fixes the following constant values in the psci.h:

1. The affinity level shift value in the power_state parameter of the
cpu_suspend

psci: fix values of incorrectly defined constants

This patch fixes the following constant values in the psci.h:

1. The affinity level shift value in the power_state parameter of the
cpu_suspend psci call. The previous value was preventing shutdown
of the affinity level 1.

2. The values used for affinity state constants (ON, OFF,
ON_PENDING). They did not match the values expected to be returned
by the affinity_info psci api as mentioned in the spec.

3. The state id shift value in the power_state parameter of the
cpu_suspend psci call.

Change-Id: I62ed5eb0e9640b4aa97b93923d6630e6b877a097

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clear wakeup enable bit upon resuming from suspend

The FVP specific code that gets called after a cpu has been physically
powered on after having been turned off or suspended earlier does not
clear

clear wakeup enable bit upon resuming from suspend

The FVP specific code that gets called after a cpu has been physically
powered on after having been turned off or suspended earlier does not
clear the PWRC.PWKUPR.WEN bit. Not doing so causes problems if: a cpu
is suspended, woken from suspend, powered down through a cpu_off call
& receives a spurious interrupt. Since the WEN bit is not cleared
after the cpu woke up from suspend, the spurious wakeup will power the
cpu on. Since the cpu_off call clears the jump address in the mailbox
this spurious wakeup will cause the cpu to crash.

This patch fixes this issue by clearing the WEN bit whenever a cpu is
powered up.

Change-Id: Ic91f5dffe1ed01d76bc7fc807acf0ecd3e38ce5b

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Enable third party contributions

- Add instructions for contributing to ARM Trusted Firmware.

- Update copyright text in all files to acknowledge contributors.

Change-Id: I9311aac81b00c6c167d2f8c8

Enable third party contributions

- Add instructions for contributing to ARM Trusted Firmware.

- Update copyright text in all files to acknowledge contributors.

Change-Id: I9311aac81b00c6c167d2f8c889aea403b84450e5

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Update user guide further to linker scripts changes

This patch updates the user guide section about the memory layout.
- Explain the verifications that the linker scripts does on the
global me

Update user guide further to linker scripts changes

This patch updates the user guide section about the memory layout.
- Explain the verifications that the linker scripts does on the
global memory layout.
- Refer to the new linker symbols.
- Describe the linker symbols exported to the trusted firmware code.

Change-Id: I033ab2b867e8b9776deb4185b9986bcb8218f286

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Generate build products in sub-directories

A single binary can be compiled using a command such as:
make CROSS_COMPILE=aarch64-none-elf- bl1

Also make use of brackets consistent in the Makefile.

Generate build products in sub-directories

A single binary can be compiled using a command such as:
make CROSS_COMPILE=aarch64-none-elf- bl1

Also make use of brackets consistent in the Makefile.

Change-Id: I2180fdb473411ef7cffe39670a7b2de82def812e

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Increase default amount of RAM for Base FVPs in FDTs

- Large RAM-disks may have trouble starting with 2GB of memory.
- Increase from 2GB to 4GB in FDT.

Change-Id: I12c1b8e5db41114b88c69c48621cb2124

Increase default amount of RAM for Base FVPs in FDTs

- Large RAM-disks may have trouble starting with 2GB of memory.
- Increase from 2GB to 4GB in FDT.

Change-Id: I12c1b8e5db41114b88c69c48621cb21247a6a6a7

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Unmask SError and Debug exceptions.

Any asynchronous exception caused by the firmware should be handled
in the firmware itself. For this reason, unmask SError exceptions
(and Debug ones as well) on

Unmask SError and Debug exceptions.

Any asynchronous exception caused by the firmware should be handled
in the firmware itself. For this reason, unmask SError exceptions
(and Debug ones as well) on all boot paths. Also route external
abort and SError interrupts to EL3, otherwise they will target EL1.

Change-Id: I9c191d2d0dcfef85f265641c8460dfbb4d112092

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fvp: Remove unnecessary initializers

Global and static variables are expected to be initialised to zero
by default. This is specified by the C99 standard. This patch
removes some unnecessary initia

fvp: Remove unnecessary initializers

Global and static variables are expected to be initialised to zero
by default. This is specified by the C99 standard. This patch
removes some unnecessary initialisations of such variables.

It fixes a compilation warning at the same time:
plat/fvp/bl31_plat_setup.c:82:3: warning: missing braces around
initializer [-Wmissing-braces]
section("tzfw_coherent_mem"))) = {0};
^
plat/fvp/bl31_plat_setup.c:82:3: warning: (near initialization for
‘ns_entry_info[0]’) [-Wmissing-braces]

Note that GCC should not have emitted this warning message in the
first place. The C Standard permits braces to be elided around
subaggregate initializers. See this GCC bug report:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119

Change-Id: I13cb0c344feb9803bca8819f976377741fa6bc35

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Fix documentation issues in v0.2 release

Change-Id: I4e2a9daa97e3be3d2f53894f2ec7947ba6bb3a16

Add Foundation FVP documentation

Change-Id: I5e47ba96e128d3a793517441f5a6c9f2ccbdfc66

ARMv8 Trusted Firmware release v0.2