| 992f091b | 12-Jul-2019 |
Ambroise Vincent <ambroise.vincent@arm.com> |
debugfs: add SMC channel
Provide an SMC interface to the 9p filesystem. This permits
accessing firmware drivers through a common interface, using
standardized read/write/control operations.
Signed-
debugfs: add SMC channel
Provide an SMC interface to the 9p filesystem. This permits
accessing firmware drivers through a common interface, using
standardized read/write/control operations.
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I9314662314bb060f6bc02714476574da158b2a7d
show more ...
|
| 52ff3b4c | 17-Dec-2019 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "doc: Fix indentation in build options documentation" into integration |
| 535fa663 | 17-Dec-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
doc: Fix indentation in build options documentation
Sphinx was showing the following warning message:
docs/getting_started/build-options.rst:200: WARNING: Bullet list ends
without a blank line; une
doc: Fix indentation in build options documentation
Sphinx was showing the following warning message:
docs/getting_started/build-options.rst:200: WARNING: Bullet list ends
without a blank line; unexpected unindent.
Change-Id: Iad5d49c1e0d25dd623ad15bce1af31babf860c03
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
show more ...
|
| 985c8a36 | 17-Dec-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "Update list of main maintainers" into integration |
| 186acdd9 | 16-Dec-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "cryptocell: add cryptocell 712 RSA 3K support" into integration |
| 01534e85 | 16-Dec-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Update list of main maintainers
Change-Id: Ia4faf873f8946992737f76870ac92bc5cb3f4020
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> |
| 11a96e0e | 18-Sep-2019 |
Justin Chadwell <justin.chadwell@arm.com> |
Remove -Wpadded warning
-Wpadded warns whenever the C compiler automatically includes any
padding in a structure. Because TF-A has a large number of structures,
this occurs fairly frequently and is
Remove -Wpadded warning
-Wpadded warns whenever the C compiler automatically includes any
padding in a structure. Because TF-A has a large number of structures,
this occurs fairly frequently and is incredibly verbose, and as such is
unlikely to ever be fixed.
The utility of this warning is also extremely limited - knowing that a
structure includes padding does not point to the existence of an error,
and is probably quite unlikely to indicate actually buggy behaviour.
Therefore, it's probably best to keep this warning off at all times.
Change-Id: I0797cb75f06b4fea0d2fdc16fd5ad978a31d76ec
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
show more ...
|
| b8622922 | 15-Sep-2019 |
Gilad Ben-Yossef <gilad.benyossef@arm.com> |
cryptocell: add cryptocell 712 RSA 3K support
Add the support needed to enable using CryptoCell integration with
with RSA 3K support.
Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com>
Chang
cryptocell: add cryptocell 712 RSA 3K support
Add the support needed to enable using CryptoCell integration with
with RSA 3K support.
Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com>
Change-Id: I95527cb0c41ae012109e8968dd20a4ae9fe67f17
show more ...
|
| fbd9eb58 | 03-Dec-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
docs: tegra: add support for Tegra194 class of SoCs
This patch adds the Tegra194 SoC information to the nvidia-tegra.rst
file.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Id649a5f
docs: tegra: add support for Tegra194 class of SoCs
This patch adds the Tegra194 SoC information to the nvidia-tegra.rst
file.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Id649a5ff1b3f70eeee34b508edb7965e7b7a2454
show more ...
|
| 84bd7a43 | 04-Dec-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "Enable Link Time Optimization in GCC" into integration |
| 6141eeeb | 03-Dec-2019 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "Remove unnecessary warning options" into integration |
| edbce9aa | 12-Nov-2019 |
zelalem-aweke <zelalem.aweke@arm.com> |
Enable Link Time Optimization in GCC
This patch enables LTO for TF-A when compiled with GCC.
LTO is disabled by default and is enabled by
ENABLE_LTO=1 build option.
LTO is enabled only for aarch64
Enable Link Time Optimization in GCC
This patch enables LTO for TF-A when compiled with GCC.
LTO is disabled by default and is enabled by
ENABLE_LTO=1 build option.
LTO is enabled only for aarch64 as there seem to be
a bug in the aarch32 compiler when LTO is enabled.
The changes in the makefiles include:
- Adding -flto and associated flags to enable LTO.
- Using gcc as a wrapper at link time instead of ld.
This is recommended when using LTO as gcc internally
takes care of invoking the necessary plugins for LTO.
- Adding switches to pass options to ld.
- Adding a flag to disable fix for erratum cortex-a53-843419
unless explicitly enabled. This is needed because GCC
seem to automatically add the erratum fix when used
as a wrapper for LD.
Additionally, this patch updates the TF-A user guide with
the new build option.
Signed-off-by: zelalem-aweke <zelalem.aweke@arm.com>
Change-Id: I1188c11974da98434b7dc9344e058cd1eacf5468
show more ...
|
| 76f25eb5 | 29-Nov-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "Changes to support updated register usage in SMCCC v1.2" into integration |
| 43f35ef5 | 29-May-2019 |
Paul Beesley <paul.beesley@arm.com> |
doc: Split the User Guide into multiple files
The User Guide document has grown organically over time and
now covers a wide range of topics, making it difficult to
skim read and extract information
doc: Split the User Guide into multiple files
The User Guide document has grown organically over time and
now covers a wide range of topics, making it difficult to
skim read and extract information from. Currently, it covers
these topics and maybe a couple more:
- Requirements (hardware, tools, libs)
- Checking out the repo
- Basic build instructions
- A comprehensive list of build flags
- FIP packaging
- Building specifically for Juno
- Firmware update images
- EL3 payloads
- Preloaded BL33 boot flow
- Running on FVPs
- Running on Juno
I have separated these out into a few groups that become new
documents. Broadly speaking, build instructions for the tools,
for TF-A generally, and for specific scenarios are separated.
Content relating to specific platforms (Juno and the FVPs are
Arm-specific platforms, essentially) has been moved into the
documentation that is specific to those platforms, under
docs/plat/arm.
Change-Id: Ica87c52d8cd4f577332be0b0738998ea3ba3bbec
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
show more ...
|
| e34cc0ce | 10-Nov-2019 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Changes to support updated register usage in SMCCC v1.2
From AArch64 state, arguments are passed in registers W0-W7(X0-X7)
and results are returned in W0-W7(X0-X7) for SMC32(SMC64) calls.
From AArch
Changes to support updated register usage in SMCCC v1.2
From AArch64 state, arguments are passed in registers W0-W7(X0-X7)
and results are returned in W0-W7(X0-X7) for SMC32(SMC64) calls.
From AArch32 state, arguments are passed in registers R0-R7 and
results are returned in registers R0-R7 for SMC32 calls.
Most of the functions and macros already existed to support using
upto 8 registers for passing/returning parameters/results. Added
few helper macros for SMC calls from AArch32 state.
Link to the specification:
https://developer.arm.com/docs/den0028/c
Change-Id: I87976b42454dc3fc45c8343e9640aa78210e9741
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
show more ...
|
| b8baa934 | 31-Jul-2019 |
Justin Chadwell <justin.chadwell@arm.com> |
Remove unnecessary warning options
Both -Wmissing-field-initializers and -Wsign-compare are both covered by
-Wextra which is enabled at W=1 anyway. Therefore, the explicit options
are not required.
Remove unnecessary warning options
Both -Wmissing-field-initializers and -Wsign-compare are both covered by
-Wextra which is enabled at W=1 anyway. Therefore, the explicit options
are not required.
Change-Id: I2e7d95b5fc14af7c70895859a7ebbeac5bc0d2a4
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
show more ...
|
| 896add4f | 18-Nov-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "lm/improve_memory_layout" into integration
* changes:
DOC: Update ROMLIB page with memory impact info
ROMLIB: Optimize memory layout when ROMLIB is used |
| 4685b64f | 11-Oct-2019 |
Louis Mayencourt <louis.mayencourt@arm.com> |
DOC: Update ROMLIB page with memory impact info
Complete the Library at ROM documentation with information regarding
the memory impact of the feature.
Change-Id: I5a10620a8e94f123021bb19523a36d558b
DOC: Update ROMLIB page with memory impact info
Complete the Library at ROM documentation with information regarding
the memory impact of the feature.
Change-Id: I5a10620a8e94f123021bb19523a36d558b330deb
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
show more ...
|
| ff2d38c2 | 17-Oct-2019 |
Paul Beesley <paul.beesley@arm.com> |
doc: Add missing terms to the glossary
Change-Id: Ibca94eae1a9a89c98b4d7cb5b4fd8943bf854030
Signed-off-by: Paul Beesley <paul.beesley@arm.com> |
| 5d0bdd57 | 13-Nov-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "docs: Add Cortex-Hercules/HerculesAE CPU support" into integration |
| 39009031 | 23-Oct-2019 |
laurenw-arm <lauren.wehrmeister@arm.com> |
docs: Add Cortex-Hercules/HerculesAE CPU support
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ia1ff13be1308e63c2854d2b6e5f6651750186abe |
| 87d35d93 | 12-Nov-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge "TF-A Documentation: Update Security Advisory TFV-5 (CVE-2017-15031)" into integration |
| c605ecd1 | 30-Oct-2019 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
TF-A Documentation: Update Security Advisory TFV-5 (CVE-2017-15031)
This patch updates description of Security Advisory TFV-5.
Change-Id: Ieaee0b51a79843345b1aca5d0e20c4964beb3c95
Signed-off-by: Al
TF-A Documentation: Update Security Advisory TFV-5 (CVE-2017-15031)
This patch updates description of Security Advisory TFV-5.
Change-Id: Ieaee0b51a79843345b1aca5d0e20c4964beb3c95
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
show more ...
|
| ec477e7d | 28-Oct-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
doc: Fix syntax erros in I/O storage layer plantuml diagrams
Some of the plantuml diagrams in the I/O storage abstraction layer
documentation are absent from the rendered version of the porting
guid
doc: Fix syntax erros in I/O storage layer plantuml diagrams
Some of the plantuml diagrams in the I/O storage abstraction layer
documentation are absent from the rendered version of the porting
guide. The build log (see [1] for example) reports a syntax error in
these files. This is due to the usage of the 'order' keyword on the
participants list, which does not seem to be supported by the version
of plantuml installed on the ReadTheDocs server.
Fix these syntax errors by removing the 'order' keyword altogether. We
simply rely on the participants being declared in the desired order,
which will be the order of display, according to the plantuml
documentation.
[1] https://readthedocs.org/api/v2/build/9870345.txt
Change-Id: Ife35c74cb2f1dac28bda07df395244639a8d6a2b
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
show more ...
|
| c381ab68 | 22-Oct-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge "Update change log for v2.2 Release" into integration |