| be3a3bc7 | 08-Dec-2020 |
Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> |
docs: arm: Add OPTEE_SP_FW_CONFIG
This adds documentation for device tree build flag OPTEE_SP_FW_CONFIG.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Ie45f075cf04
docs: arm: Add OPTEE_SP_FW_CONFIG
This adds documentation for device tree build flag OPTEE_SP_FW_CONFIG.
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Ie45f075cf04182701007f87aa0c8912cd567157a
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| de155790 | 11-Dec-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "TF-A: Add build option for Arm Feature Modifiers" into integration |
| bd054fd6 | 11-Dec-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "rdevans" into integration
* changes:
doc: Update list of supported FVP platforms
board/rdn2: add board support for rdn2 platform
plat/arm/sgi: adapt to changes in mem
Merge changes from topic "rdevans" into integration
* changes:
doc: Update list of supported FVP platforms
board/rdn2: add board support for rdn2 platform
plat/arm/sgi: adapt to changes in memory map
plat/arm/sgi: add platform id value for rdn2 platform
plat/arm/sgi: platform definitions for upcoming platforms
plat/arm/sgi: refactor header file inclusions
plat/arm/sgi: refactor the inclusion of memory mapping
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| 0063dd17 | 23-Nov-2020 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
Add support for FEAT_MTPMU for Armv8.6
If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented
as well, it is possible to control whether PMU counters take into account
events happ
Add support for FEAT_MTPMU for Armv8.6
If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented
as well, it is possible to control whether PMU counters take into account
events happening on other threads.
If FEAT_MTPMU is implemented, EL3 (or EL2) can override the MT bit
leaving it to effective state of 0 regardless of any write to it.
This patch introduces the DISABLE_MTPMU flag, which allows to diable
multithread event count from EL3 (or EL2). The flag is disabled
by default so the behavior is consistent with those architectures
that do not implement FEAT_MTPMU.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Iee3a8470ae8ba13316af1bd40c8d4aa86e0cb85e
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| f1821790 | 07-Dec-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
TF-A: Add build option for Arm Feature Modifiers
This patch adds a new ARM_ARCH_FEATURE build option
to add support for compiler's feature modifiers.
It has the form '[no]feature+...' and defaults t
TF-A: Add build option for Arm Feature Modifiers
This patch adds a new ARM_ARCH_FEATURE build option
to add support for compiler's feature modifiers.
It has the form '[no]feature+...' and defaults to
'none'. This option translates into compiler option
'-march=armvX[.Y]-a+[no]feature+...'.
Change-Id: I37742f270a898f5d6968e146cbcc04cbf53ef2ad
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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| 745da67b | 25-Nov-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs: Update the FIP generation process using SP images
Updated the documentation for the FIP generation process using
SP images.
Change-Id: I4df7f379f08f33adba6f5c82904291576972e106
Signed-off-by:
docs: Update the FIP generation process using SP images
Updated the documentation for the FIP generation process using
SP images.
Change-Id: I4df7f379f08f33adba6f5c82904291576972e106
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 7b24e48a | 08-Dec-2020 |
Aditya Angadi <aditya.angadi@arm.com> |
doc: Update list of supported FVP platforms
Updated the list of supported FVP platforms with support for RD-N2 FVP.
Change-Id: I861bbb6d520c20e718f072e118c66dab61fe1386
Signed-off-by: Aditya Angadi
doc: Update list of supported FVP platforms
Updated the list of supported FVP platforms with support for RD-N2 FVP.
Change-Id: I861bbb6d520c20e718f072e118c66dab61fe1386
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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| 91cc872c | 02-Dec-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "Add myself and Venkatesh Yadav Abbarapu as code owners for Xilinx platforms" into integration |
| 25bbbd2d | 23-Oct-2020 |
Javier Almansa Sobrino <javier.almansasobrino@arm.com> |
Add support for Neoverse-N2 CPUs.
Enable basic support for Neoverse-N2 CPUs.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8
Add support for Neoverse-N2 CPUs.
Enable basic support for Neoverse-N2 CPUs.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad
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| f20cb7e5 | 29-Oct-2020 |
Pali Rohár <pali@kernel.org> |
docs: marvell: Update build documentation to reflect mrvl_bootimage and mrvl_flash changes
Also add example how to build TF-A for A3720 Turris MOX board and also fix
style/indentation issues and inf
docs: marvell: Update build documentation to reflect mrvl_bootimage and mrvl_flash changes
Also add example how to build TF-A for A3720 Turris MOX board and also fix
style/indentation issues and information about default values.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2dc957307b1b627b403a8d960e85f5ac9e15aee5
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| 7b12a8d6 | 19-Nov-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "Revert workaround for A77 erratum 1800714" into integration |
| b9ad2bb8 | 19-Nov-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "Revert workaround for A76 erratum 1800710" into integration |
| 7096a45a | 19-Nov-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "Fix typos and misspellings" into integration |
| 0bd1a2e9 | 29-Oct-2020 |
Chris Kay <chris.kay@arm.com> |
docs: Update changelog for v2.4 release
Change-Id: I67c9db2fc6d4b83fec2d001745b9305102d4a2ae
Signed-off-by: Chris Kay <chris.kay@arm.com> |
| 9bbc03a6 | 12-Nov-2020 |
johpow01 <john.powell@arm.com> |
Revert workaround for A77 erratum 1800714
This errata workaround did not work as intended and was revised in
subsequent SDEN releases so we are reverting this change.
This is the patch being revert
Revert workaround for A77 erratum 1800714
This errata workaround did not work as intended and was revised in
subsequent SDEN releases so we are reverting this change.
This is the patch being reverted:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4686
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I8554c75d7217331c7effd781b5f7f49b781bbebe
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| 95ed9a9e | 12-Nov-2020 |
johpow01 <john.powell@arm.com> |
Revert workaround for A76 erratum 1800710
This errata workaround did not work as intended and was revised in
subsequent SDEN releases so we are reverting this change.
This is the patch being revert
Revert workaround for A76 erratum 1800710
This errata workaround did not work as intended and was revised in
subsequent SDEN releases so we are reverting this change.
This is the patch being reverted:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4684
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I560749a5b55e22fbe49d3f428a8b9545d6bdaaf0
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| 5d9101b3 | 12-Nov-2020 |
David Horstmann <david.horstmann@arm.com> |
Fix typos and misspellings
Fix a number of typos and misspellings in TF-A
documentation and comments.
Signed-off-by: David Horstmann <david.horstmann@arm.com>
Change-Id: I34c5a28c3af15f28d1ccada4d9
Fix typos and misspellings
Fix a number of typos and misspellings in TF-A
documentation and comments.
Signed-off-by: David Horstmann <david.horstmann@arm.com>
Change-Id: I34c5a28c3af15f28d1ccada4d9866aee6af136ee
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| 942d0c7c | 12-Nov-2020 |
Michal Simek <michal.simek@xilinx.com> |
Add myself and Venkatesh Yadav Abbarapu as code owners for Xilinx platforms
Jolly left the company and Siva (DP) has moved to different possition
that's why it is necessary to change code ownership.
Add myself and Venkatesh Yadav Abbarapu as code owners for Xilinx platforms
Jolly left the company and Siva (DP) has moved to different possition
that's why it is necessary to change code ownership.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I546d9a0f7a2abd0c7a65be807725bc609160f3b2
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| 95fca110 | 24-Oct-2020 |
Varun Wadekar <vwadekar@nvidia.com> |
Merge "docs: marvell: update ddr3 build instructions" into integration |
| c4d919ee | 21-Oct-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "tc0_sel2_spmc" into integration
* changes:
lib: el3_runtime: Fix SPE system registers in el2_sysregs_context
lib: el3_runtime: Conditionally save/restore EL2 NEVE regis
Merge changes from topic "tc0_sel2_spmc" into integration
* changes:
lib: el3_runtime: Fix SPE system registers in el2_sysregs_context
lib: el3_runtime: Conditionally save/restore EL2 NEVE registers
lib: el3_runtime: Fix aarch32 system registers in el2_sysregs_context
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| bd260fcb | 20-Oct-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "docs: code review guidelines" into integration |
| 062f8aaf | 28-May-2020 |
Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> |
lib: el3_runtime: Conditionally save/restore EL2 NEVE registers
Include EL2 registers related to Nested Virtualization in EL2 context
save/restore routines if architecture supports it and platform w
lib: el3_runtime: Conditionally save/restore EL2 NEVE registers
Include EL2 registers related to Nested Virtualization in EL2 context
save/restore routines if architecture supports it and platform wants to
use these features in Secure world.
Change-Id: If006ab83bbc2576488686f5ffdff88b91adced5c
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
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| 3bd19575 | 08-Oct-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs: Remove deprecated information
There are no references to AARCH32, AARCH64 and
__ASSEMBLY__ macros in the TF-A code hence
removed the deprecated information mentioning about
these macros in the
docs: Remove deprecated information
There are no references to AARCH32, AARCH64 and
__ASSEMBLY__ macros in the TF-A code hence
removed the deprecated information mentioning about
these macros in the document.
Change-Id: I472ab985ca2e4173bae23ff7b4465a9b60bc82eb
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| c20bbfa1 | 08-Oct-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs: Update Release information for v2.5
Updated tentative code freeze and release target date
for v2.5 release.
Change-Id: Idcfd9a127e9210846370dfa0685badac5b1c25c7
Signed-off-by: Manish V Badark
docs: Update Release information for v2.5
Updated tentative code freeze and release target date
for v2.5 release.
Change-Id: Idcfd9a127e9210846370dfa0685badac5b1c25c7
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| f329442c | 08-Oct-2020 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs: Update code freeze and release target date for v2.4
Updated code freeze and release information date for v2.4
release.
Change-Id: I76d5d04d0ee062a350f6a693eb04c29017d8b2e0
Signed-off-by: Mani
docs: Update code freeze and release target date for v2.4
Updated code freeze and release information date for v2.4
release.
Change-Id: I76d5d04d0ee062a350f6a693eb04c29017d8b2e0
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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