| 3f4d81df | 09-Mar-2022 |
Varun Wadekar <vwadekar@nvidia.com> |
fix(errata): workaround for Cortex A78 AE erratum 2395408
Cortex A78 AE erratum 2395408 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.
This erratum states, "A translation t
fix(errata): workaround for Cortex A78 AE erratum 2395408
Cortex A78 AE erratum 2395408 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.
This erratum states, "A translation table walk that matches an
existing L1 prefetch with a read request outstanding on CHI might
fold into the prefetch, which might lead to data corruption for
a future instruction fetch"
This erratum is avoided by setting CPUACTLR2_EL1[40] to 1 to
disable folding of demand requests into older prefetches with
L2 miss requests outstanding.
SDEN is available at https://developer.arm.com/documentation/SDEN-1707912
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ic17968987ca3c67fa7f64211bcde6dfcb35ed5d6
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| 92e87084 | 09-Mar-2022 |
Varun Wadekar <vwadekar@nvidia.com> |
fix(errata): workaround for Cortex A78 AE erratum 2376748
Cortex A78 AE erratum 2376748 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.
The erratum states, "A PE executing a
fix(errata): workaround for Cortex A78 AE erratum 2376748
Cortex A78 AE erratum 2376748 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.
The erratum states, "A PE executing a PLDW or PRFM PST instruction
that lies on a mispredicted branch path might cause a second PE
executing a store exclusive to the same cache line address to fail
continuously."
The erratum is avoided by setting CPUACTLR2_EL1[0] to 1 to force
PLDW/PFRM ST to behave like PLD/PRFM LD and not cause invalidations
to other PE caches. There might be a small performance degradation
to this workaround for certain workloads that share data.
SDEN is available at https://developer.arm.com/documentation/SDEN-1707912
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I93bd392a870d4584f3e12c8e4626dbe5a3a40a4d
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|
| e638c228 | 23-Mar-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "build(sptool): handle uuid field in SP layout file" into integration |
| 2ff6a49e | 22-Mar-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "stm32mp13" into integration
* changes:
feat(stm32mp1): select platform compilation either by flag or DT
feat(stm32mp1-fdts): add support for STM32MP13 DK board
feat(s
Merge changes from topic "stm32mp13" into integration
* changes:
feat(stm32mp1): select platform compilation either by flag or DT
feat(stm32mp1-fdts): add support for STM32MP13 DK board
feat(stm32mp1-fdts): add DDR support for STM32MP13
feat(stm32mp1-fdts): add st-io_policies node for STM32MP13
feat(stm32mp1): updates for STM32MP13 device tree compilation
feat(stm32mp1-fdts): add DT files for STM32MP13
feat(dt-bindings): add TZC400 bindings for STM32MP13
feat(stm32mp1): add "Boot mode" management for STM32MP13
feat(stm32mp1): manage HSLV on STM32MP13
feat(stm32mp1): add sdmmc compatible in platform define
feat(st-sdmmc2): allow compatible to be defined in platform code
feat(stm32mp1): update IO compensation on STM32MP13
feat(stm32mp1): call pmic_voltages_init() in platform init
feat(st-pmic): add pmic_voltages_init() function
feat(stm32mp1): update CFG0 OTP for STM32MP13
feat(stm32mp1): usb descriptor update for STM32MP13
feat(st-clock): add clock driver for STM32MP13
feat(dt-bindings): add bindings for STM32MP13
feat(stm32mp1): get CPU info from SYSCFG on STM32MP13
feat(stm32mp1): use only one filter for TZC400 on STM32MP13
feat(stm32mp1): add a second fixed regulator
feat(stm32mp1): adaptations for STM32MP13 image header
feat(stm32mp1): update boot API for header v2.0
feat(stm32mp1): update IP addresses for STM32MP13
feat(stm32mp1): add part numbers for STM32MP13
feat(stm32mp1): chip rev. Z is 0x1001 on STM32MP13
feat(stm32mp1): update BACKUP_BOOT_MODE for STM32MP13
feat(stm32mp1): stm32mp_is_single_core() for STM32MP13
feat(stm32mp1): remove unsupported features on STM32MP13
feat(stm32mp1): update memory mapping for STM32MP13
feat(stm32mp1): introduce new flag for STM32MP13
feat(st): update stm32image tool for header v2
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| bdec516e | 18-Dec-2020 |
Sebastien Pasdeloup <sebastien.pasdeloup-ext@st.com> |
feat(stm32mp1): introduce new flag for STM32MP13
STM32MP13 is a variant of STM32MP1, with a single Cortex-A7, and no
Cortex-M4.
There is only one DDR port.
SP_min is not supported, only OP-TEE can b
feat(stm32mp1): introduce new flag for STM32MP13
STM32MP13 is a variant of STM32MP1, with a single Cortex-A7, and no
Cortex-M4.
There is only one DDR port.
SP_min is not supported, only OP-TEE can be used as monitor.
STM32MP13 uses the header v2.0 format for stm32image generation
for BL2.
Change-Id: Ie5b0e3230c5e064fe96f3561fc5b3208914dea53
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 19a2d518 | 16-Mar-2022 |
Pali Rohár <pali@kernel.org> |
docs(a3k): update documentation about DEBUG mode for UART
DEBUG mode can be enabled without any issue for Armada 37xx and also for
other A7K/A8K/CN913x. There is no incompatibility with Xmodem proto
docs(a3k): update documentation about DEBUG mode for UART
DEBUG mode can be enabled without any issue for Armada 37xx and also for
other A7K/A8K/CN913x. There is no incompatibility with Xmodem protocol
like it was written before, because Armada 37xx UART images do not print
anything on UART during image transfer and A7K/A8K/CN913x BLE image
automatically turn off debugging output when booting over UART. Looks
like this incorrect information is some relict from the past.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I85adc3c21036656b4620c4692e04330cad11ea2f
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| 1fe4a9d1 | 18-Jan-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(security): workaround for CVE-2022-23960
Implements the loop workaround for Cortex-A77, Cortex-A78,
Cortex-A710, Cortex-X2, Neoverse N1, Neoverse N2 and Neoverse V1
CPUs.
Signed-off-by: Bipin R
fix(security): workaround for CVE-2022-23960
Implements the loop workaround for Cortex-A77, Cortex-A78,
Cortex-A710, Cortex-X2, Neoverse N1, Neoverse N2 and Neoverse V1
CPUs.
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I11d342df7a2068a15e18f4974c645af3b341235b
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| ef934cd1 | 01-Mar-2022 |
johpow01 <john.powell@arm.com> |
fix(errata): workaround for Cortex-A710 2282622
Cortex-A710 erratum 2282622 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set
CPUACTL
fix(errata): workaround for Cortex-A710 2282622
Cortex-A710 erratum 2282622 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set
CPUACTLR2_EL1[0] to 1, which will force PLDW/PFRM ST to behave like
PLD/PRFM LD and not cause invalidations to other PE caches.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ic48409822536e9eacc003300036a1f0489593020
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|
| a82f5bbf | 08-Mar-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "docs(security): security advisory for CVE-2022-23960" into integration |
| 2d972cc9 | 26-Feb-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
docs(security): security advisory for CVE-2022-23960
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I17b0847ff71e4a291bf7ba41fd71fe08c400b5e8 |
| 1cfe4896 | 07-Mar-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "docs(maintainers): add maintained files for MediaTek SoCs" into integration |
| 99887cb9 | 02-Mar-2022 |
Yann Gautier <yann.gautier@foss.st.com> |
refactor(st): configure UART baudrate
Add the possibility to configure console UART baudrate, it can be passed
as a command line parameter with STM32MP_UART_BAUDRATE. The default value
remains 11520
refactor(st): configure UART baudrate
Add the possibility to configure console UART baudrate, it can be passed
as a command line parameter with STM32MP_UART_BAUDRATE. The default value
remains 115200.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I000df70c10b2b4dac1449556596f9820c36cf243
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|
| 975cf6ff | 03-Mar-2022 |
Yann Gautier <yann.gautier@st.com> |
docs(stm32mp1): document some compilation flags
Add missing serial boot devices flags.
Add optional compilation flags, and their defauld values.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Ch
docs(stm32mp1): document some compilation flags
Add missing serial boot devices flags.
Add optional compilation flags, and their defauld values.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I507f7110bcd7b9af136a6fc6b8af342b084c8dbc
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|
| 44cf2b1a | 04-Mar-2022 |
Rex-BC Chen <rex-bc.chen@mediatek.com> |
docs(maintainers): add maintained files for MediaTek SoCs
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I2d71b2fef2f2aee507a6e7c4b9b9d8175446a0ca |
| 3f7c8861 | 02-Mar-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "docs(rme): minor update to 4 world execution instructions" into integration |
| 1dd4bafb | 02-Mar-2022 |
Manish Pandey <manish.pandey2@arm.com> |
docs(rme): minor update to 4 world execution instructions
Following updates done
- Clarification on building Hafnium
- New test suite "Invalid memory access"
Signed-off-by: Manish Pandey <manis
docs(rme): minor update to 4 world execution instructions
Following updates done
- Clarification on building Hafnium
- New test suite "Invalid memory access"
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I04a934a648d53a860f06cd6cf3776ee534675bd9
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|
| 8a342992 | 25-Feb-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge changes I1784d643,Icb6e3699,I7805756e into integration
* changes:
fix(errata): workaround for Cortex-A510 erratum 2172148
fix(errata): workaround for Cortex-A510 erratum 2218950
fix(erra
Merge changes I1784d643,Icb6e3699,I7805756e into integration
* changes:
fix(errata): workaround for Cortex-A510 erratum 2172148
fix(errata): workaround for Cortex-A510 erratum 2218950
fix(errata): workaround for Cortex-A510 erratum 2250311
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|
| c0959d2c | 16-Feb-2022 |
johpow01 <john.powell@arm.com> |
fix(errata): workaround for Cortex-A510 erratum 2172148
Cortex-A510 erratum 2172148 is a Cat B erratum that applies to revisions
r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.
SDEN can be f
fix(errata): workaround for Cortex-A510 erratum 2172148
Cortex-A510 erratum 2172148 is a Cat B erratum that applies to revisions
r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2397239
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I1784d643ca3d1d448340cd421facb5f229df1d22
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|
| cc79018b | 15-Feb-2022 |
johpow01 <john.powell@arm.com> |
fix(errata): workaround for Cortex-A510 erratum 2218950
Cortex-A510 erratum 2218950 is a Cat B erratum that applies to revisions
r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.
SDEN can be f
fix(errata): workaround for Cortex-A510 erratum 2218950
Cortex-A510 erratum 2218950 is a Cat B erratum that applies to revisions
r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2397239
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Icb6e369946f8978a08cf8ed5e4452782efb0a77a
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|
| 7f304b02 | 14-Feb-2022 |
johpow01 <john.powell@arm.com> |
fix(errata): workaround for Cortex-A510 erratum 2250311
Cortex-A510 erratum 2250311 is a Cat B erratum that applies to revisions
r0p0, r0p1, r0p2, r0p3 and r1p0 and is fixed in r1p1.
This erratum w
fix(errata): workaround for Cortex-A510 erratum 2250311
Cortex-A510 erratum 2250311 is a Cat B erratum that applies to revisions
r0p0, r0p1, r0p2, r0p3 and r1p0 and is fixed in r1p1.
This erratum workaround is a bit different because it interacts with a
feature supported in TFA. The typical method of implementing an errata
workaround will not work in this case as the MPMM feature would just be
re-enabled by context management at every core power on after being
disabled by the errata framework. So in addition to disabling MPMM, this
workaround also sets a flag in the MPMM runtime framework indicating
that the feature should not be enabled even if ENABLE_MPMM=1.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2397239
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7805756e65ec90b6ef8af47e200617c9e07a3a7e
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|
| 510155aa | 24-Feb-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge changes I7b1498fa,I1d2ebee3,I875519ff,I8c427ef2 into integration
* changes:
fix(errata): workaround for Cortex-A510 erratum 2041909
fix(errata): workaround for Cortex-A510 erratum 2042739
Merge changes I7b1498fa,I1d2ebee3,I875519ff,I8c427ef2 into integration
* changes:
fix(errata): workaround for Cortex-A510 erratum 2041909
fix(errata): workaround for Cortex-A510 erratum 2042739
fix(errata): workaround for Cortex-A510 erratum 2288014
fix(errata): workaround for Cortex-A510 erratum 1922240
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|
| 32742263 | 24-Jan-2022 |
Soby Mathew <soby.mathew@arm.com> |
docs(el3-runtimes): context management refactor proposal
This patch submits an RFC to refactor the context management
mechanism in TF-A.
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id:
docs(el3-runtimes): context management refactor proposal
This patch submits an RFC to refactor the context management
mechanism in TF-A.
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: Ia1ad5a85cb86c129e2feaf36bed123f0067c3965
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|
| e76b018f | 23-Feb-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "docs(a3k): add information about system-wide Crypto++ library" into integration |
| e72bbe47 | 11-Jan-2022 |
johpow01 <john.powell@arm.com> |
fix(errata): workaround for Cortex-A510 erratum 2041909
Cortex-A510 erratum 2041909 is a Cat B erratum that applies to revision
r0p2 and is fixed in r0p3. It is also present in r0p0 and r0p1 but the
fix(errata): workaround for Cortex-A510 erratum 2041909
Cortex-A510 erratum 2041909 is a Cat B erratum that applies to revision
r0p2 and is fixed in r0p3. It is also present in r0p0 and r0p1 but there
is no workaround in these revisions.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2397239
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7b1498faa0c79488dee0d11d07f6e9f58144e298
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|
| d48088ac | 07-Jan-2022 |
johpow01 <john.powell@arm.com> |
fix(errata): workaround for Cortex-A510 erratum 2042739
Cortex-A510 erratum 2042739 is a Cat B erratum that applies to revisions
r0p0, r0p1 and r0p2 and is fixed in r0p3.
SDEN can be found here:
ht
fix(errata): workaround for Cortex-A510 erratum 2042739
Cortex-A510 erratum 2042739 is a Cat B erratum that applies to revisions
r0p0, r0p1 and r0p2 and is fixed in r0p3.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2397239
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I1d2ebee3914396e1e298eb45bdab35ce9e194ad9
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|