| 099c90b8 | 20-Aug-2021 |
Pali Rohár <pali@kernel.org> |
docs(plat/marvell/a8k): document MSS_SUPPORT and SCP_BL2 build options
Add missing documentation for MSS_SUPPORT and SCP_BL2 build options used
on Marvell platforms.
Signed-off-by: Pali Rohár <pali
docs(plat/marvell/a8k): document MSS_SUPPORT and SCP_BL2 build options
Add missing documentation for MSS_SUPPORT and SCP_BL2 build options used
on Marvell platforms.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I852f60569a9a49269ae296c56cc83eb438528bee
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| bd4b4b03 | 20-Aug-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "docs(spmc): threat model document" into integration |
| 47d6f5ff | 27-Jul-2021 |
Varun Wadekar <vwadekar@nvidia.com> |
feat(cpus): workaround for Cortex A78 AE erratum 1941500
Cortex A78 AE erratum 1941500 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.
This erratum is avoided by by setting
feat(cpus): workaround for Cortex A78 AE erratum 1941500
Cortex A78 AE erratum 1941500 is a Cat B erratum that applies
to revisions <= r0p1. It is still open.
This erratum is avoided by by setting CPUECTLR_EL1[8] to 1.
There is a small performance cost (<0.5%) for setting this
bit.
SDEN is available at https://developer.arm.com/documentation/SDEN1707912/0900
Change-Id: I2d72666468b146714a0340ba114ccf0f5165b39c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| 3af9b3f0 | 01-Jun-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
docs(spmc): threat model document
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ib5f443a6997239d6ba4655d7df6c3fc61d45f991 |
| 0ed87212 | 19-Aug-2021 |
Varun Wadekar <vwadekar@nvidia.com> |
Merge "feat(cpus): workaround for Cortex A78 AE erratum 1951502" into integration |
| 8913047a | 27-Jul-2021 |
Varun Wadekar <vwadekar@nvidia.com> |
feat(cpus): workaround for Cortex A78 AE erratum 1951502
Cortex A78 AE erratum 1951502 is a Cat B erratum that applies to revisions
<= r0p1. It is still open. This erratum is avoided by inserting a
feat(cpus): workaround for Cortex A78 AE erratum 1951502
Cortex A78 AE erratum 1951502 is a Cat B erratum that applies to revisions
<= r0p1. It is still open. This erratum is avoided by inserting a DMB ST
before acquire atomic instructions without release semantics through a series
of writes to implementation defined system registers.
SDEN is available at https://developer.arm.com/documentation/SDEN1707912/0900
Change-Id: I812c5a37cdd03486df8af6046d9fa988f6a0a098
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| d4ad3da0 | 24-Apr-2021 |
Varun Wadekar <vwadekar@nvidia.com> |
refactor(tegra132): deprecate platform
The Tegra132 platforms have reached their end of life and are
no longer used in the field. Internally and externally, all
known programs have removed support f
refactor(tegra132): deprecate platform
The Tegra132 platforms have reached their end of life and are
no longer used in the field. Internally and externally, all
known programs have removed support for this legacy platform.
This change removes this platform from the Tegra tree as a result.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I72edb689293e23b63290cdcaef60468b90687a5a
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| be3a51ce | 13-Aug-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(plat/versal): add support for SLS mitigation" into integration |
| 6ec0c65b | 09-Apr-2021 |
Usama Arif <usama.arif@arm.com> |
feat(plat/arm): Introduce TC1 platform
This renames tc0 platform folder and files to tc, and introduces
TARGET_PLATFORM variable to account for the differences between
TC0 and TC1.
Signed-off-by: U
feat(plat/arm): Introduce TC1 platform
This renames tc0 platform folder and files to tc, and introduces
TARGET_PLATFORM variable to account for the differences between
TC0 and TC1.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I5b4a83f3453afd12542267091b3edab4c139c5cd
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| 100d4029 | 03-Aug-2021 |
johpow01 <john.powell@arm.com> |
errata: workaround for Neoverse V1 errata 2139242
Neoverse V1 erratum 2139242 is a Cat B erratum present in the V1
processor core. This issue is present in revisions r0p0, r1p0,
and r1p1, and it is
errata: workaround for Neoverse V1 errata 2139242
Neoverse V1 erratum 2139242 is a Cat B erratum present in the V1
processor core. This issue is present in revisions r0p0, r1p0,
and r1p1, and it is still open.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I5c2e9beec72a64ac4131fb6dd76199821a934ebe
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| 1a8804c3 | 02-Aug-2021 |
johpow01 <john.powell@arm.com> |
errata: workaround for Neoverse V1 errata 1966096
Neoverse V1 erratum 1966096 is a Cat B erratum present in the V1
processor core. This issue is present in revisions r0p0, r1p0,
and r1p1, but the w
errata: workaround for Neoverse V1 errata 1966096
Neoverse V1 erratum 1966096 is a Cat B erratum present in the V1
processor core. This issue is present in revisions r0p0, r1p0,
and r1p1, but the workaround only applies to r1p0 and r1p1, it is still
open.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ic0b9a931e38da8a7000648e221481e17c253563b
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|
| d1987f4c | 09-Aug-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "errata: workaround for Neoverse V1 errata 1925756" into integration |
| 55120f9c | 09-Aug-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "errata: workaround for Neoverse V1 errata 1852267" into integration |
| 1d24eb33 | 09-Aug-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "errata: workaround for Neoverse V1 errata 1774420" into integration |
| 741dd04c | 02-Aug-2021 |
laurenw-arm <lauren.wehrmeister@arm.com> |
errata: workaround for Neoverse V1 errata 1925756
Neoverse V1 erratum 1925756 is a Cat B erratum present in r0p0, r1p0,
and r1p1 of the V1 processor core, and it is still open.
SDEN can be found he
errata: workaround for Neoverse V1 errata 1925756
Neoverse V1 erratum 1925756 is a Cat B erratum present in r0p0, r1p0,
and r1p1 of the V1 processor core, and it is still open.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I6500dc98da92a7c405b9ae09d794d666e8f4ae52
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| 143b1965 | 02-Aug-2021 |
laurenw-arm <lauren.wehrmeister@arm.com> |
errata: workaround for Neoverse V1 errata 1852267
Neoverse V1 erratum 1852267 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
http
errata: workaround for Neoverse V1 errata 1852267
Neoverse V1 erratum 1852267 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ide5e0bc09371fbc91c2385ffdff74e604beb2dbe
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| 4789cf66 | 02-Aug-2021 |
laurenw-arm <lauren.wehrmeister@arm.com> |
errata: workaround for Neoverse V1 errata 1774420
Neoverse V1 erratum 1774420 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
http
errata: workaround for Neoverse V1 errata 1774420
Neoverse V1 erratum 1774420 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I66e27b2518f73faeedd8615a1443a74b6a30f123
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| 5e4e13e1 | 02-Aug-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "fw-update-2" into integration
* changes:
feat(sw_crc32): add software CRC32 support
refactor(hw_crc32): renamed hw_crc32 to tf_crc32
feat(fwu): avoid booting with an
Merge changes from topic "fw-update-2" into integration
* changes:
feat(sw_crc32): add software CRC32 support
refactor(hw_crc32): renamed hw_crc32 to tf_crc32
feat(fwu): avoid booting with an alternate boot source
docs(fwu): add firmware update documentation
feat(fwu): avoid NV counter upgrade in trial run state
feat(plat/arm): add FWU support in Arm platforms
feat(fwu): initialize FWU driver in BL2
feat(fwu): add FWU driver
feat(fwu): introduce FWU platform-specific functions declarations
docs(fwu_metadata): add FWU metadata build options
feat(fwu_metadata): add FWU metadata header and build options
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| 0f20e50b | 20-Jun-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs(fwu): add firmware update documentation
Added firmware update documentation for:
1. PSA firmware update build flag
2. Porting guidelines to set the addresses of FWU metadata image
and update
docs(fwu): add firmware update documentation
Added firmware update documentation for:
1. PSA firmware update build flag
2. Porting guidelines to set the addresses of FWU metadata image
and updated components in I/O policy
Change-Id: Iad3eb68b4be01a0b5850b69a067c60fcb464f54b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| c7e39dcf | 02-Aug-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "feat(ff-a): change manifest messaging method" into integration |
| 34f702d5 | 16-Mar-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs(fwu_metadata): add FWU metadata build options
Added the build options used in defining the firmware update metadata
structure.
Change-Id: Idd40ea629e643e775083f283b75c80f6c026b127
Signed-off-b
docs(fwu_metadata): add FWU metadata build options
Added the build options used in defining the firmware update metadata
structure.
Change-Id: Idd40ea629e643e775083f283b75c80f6c026b127
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 6ea1a75d | 29-Jul-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "refactor(plat/marvell): move doc platform build options into own subsections" into integration |
| 92024f81 | 20-Jul-2021 |
Pali Rohár <pali@kernel.org> |
refactor(plat/marvell): move doc platform build options into own subsections
Update documentation and group platform specific build options into
their own subsections.
Signed-off-by: Pali Rohár <pa
refactor(plat/marvell): move doc platform build options into own subsections
Update documentation and group platform specific build options into
their own subsections.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I05927d8abf9f811493c49b856f06329220e7d8bb
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| 76cce571 | 25-Jul-2021 |
Joanna Farley <joanna.farley@arm.com> |
Merge "docs(maintainers): update imx8 entry" into integration |
| 7b514399 | 23-Jul-2021 |
Peng Fan <peng.fan@nxp.com> |
docs(maintainers): update imx8 entry
Add myself as i.MX8 maintainer.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: Ib037c24a75d42febd79f2eb1ab3b985356dbfb58 |