| def661b6 | 22-Sep-2022 |
Michal Simek <michal.simek@amd.com> |
docs(maintainers): update xilinx record to cover docs
Recently new Xilinx Versal NET platform has been merged but documentation
cover only zynqmp. Fix the fragment to cover all Xilinx documentation.
docs(maintainers): update xilinx record to cover docs
Recently new Xilinx Versal NET platform has been merged but documentation
cover only zynqmp. Fix the fragment to cover all Xilinx documentation.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I10f8f865ca8d46518135adb80ba0ba4470534529
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| cdbea240 | 21-Sep-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "docs(build): update GCC to 11.3.Rel1 version" into integration |
| 4efdc488 | 31-Aug-2022 |
Michal Simek <michal.simek@amd.com> |
feat(versal-net): add documentation for Versal NET SoC
Add description for Versal NET SoC.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
feat(versal-net): add documentation for Versal NET SoC
Add description for Versal NET SoC.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: Idcbb893c6b9e46512308c53ba2a0bee48a022b0a
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| b86cbe10 | 16-Sep-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "provencore-spd" into integration
* changes:
feat(zynqmp): add support for ProvenCore
feat(services): add a SPD for ProvenCore
feat(gic): add APIs to raise NS and S-EL
Merge changes from topic "provencore-spd" into integration
* changes:
feat(zynqmp): add support for ProvenCore
feat(services): add a SPD for ProvenCore
feat(gic): add APIs to raise NS and S-EL1 SGIs
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| eb3d4015 | 04-Jul-2022 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs(fwu): update firmware update design
Refactored legacy firmware design and added details about PSA
firmware updates.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I9c123
docs(fwu): update firmware update design
Refactored legacy firmware design and added details about PSA
firmware updates.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I9c123b3f62580d4271dbaff0a728b6412fae7890
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| b0980e58 | 08-Sep-2021 |
Florian Lugou <florian.lugou@provenrun.com> |
feat(services): add a SPD for ProvenCore
Adds a dispatcher for ProvenCore based on the test secure payload
dispatcher.
Signed-off-by: Florian Lugou <florian.lugou@provenrun.com>
Change-Id: I978afc3
feat(services): add a SPD for ProvenCore
Adds a dispatcher for ProvenCore based on the test secure payload
dispatcher.
Signed-off-by: Florian Lugou <florian.lugou@provenrun.com>
Change-Id: I978afc3af6a6f65791655685a7bc80070673c9f3
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| 158ed580 | 27-Jul-2022 |
Pranav Madhu <pranav.madhu@arm.com> |
feat(plat/arm/css): add per-cpu power down support for warm reset
Add a new function to setup a SGI interrupt that will be used to trigger
a request for per-cpu power down when executing the PSCI SY
feat(plat/arm/css): add per-cpu power down support for warm reset
Add a new function to setup a SGI interrupt that will be used to trigger
a request for per-cpu power down when executing the PSCI SYSTEM_RESET
request. This will be used on CSS platform that require all the CPUs to
execute the CPU specific power down sequence to complete a warm reboot
sequence in which only the CPUs are power cycled.
Change-Id: I80da0f6c3cd0c5c442c82239ba1e1f773821a7f5
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
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| 95925676 | 13-Sep-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(cpus): workaround for Cortex-A710 2216384" into integration |
| 49154435 | 12-Sep-2022 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
docs(build): update GCC to 11.3.Rel1 version
This toolchain provides multiple cross compilers and is publicly
available on https://developer.arm.com/
We build TF-A in CI using:
AArch32 bare-metal t
docs(build): update GCC to 11.3.Rel1 version
This toolchain provides multiple cross compilers and is publicly
available on https://developer.arm.com/
We build TF-A in CI using:
AArch32 bare-metal target (arm-none-eabi)
AArch64 ELF bare-metal target (aarch64-none-elf)
Change-Id: I94e13f6c1ebe3a4a58ca6c79c1605bd300b372d3
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
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| 1790036d | 13-Sep-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "docs(porting-guide): correct typo of "bits" to "bytes"" into integration |
| 5c60b8c8 | 08-Sep-2022 |
Max Yu <maxlyu@google.com> |
docs(porting-guide): correct typo of "bits" to "bytes"
The CACHE_WRITEBACK_GRANULE is documented to be in bits, but
specifying the value in bits broke a build. Further investigation
suggests that th
docs(porting-guide): correct typo of "bits" to "bytes"
The CACHE_WRITEBACK_GRANULE is documented to be in bits, but
specifying the value in bits broke a build. Further investigation
suggests that the value should in fact be in bytes. See
https://github.com/ARM-software/arm-trusted-firmware/blob/master/include/arch/aarch64/
smccc_helpers.h#L101
and
https://gcc.gnu.org/onlinedocs/gcc-12.2.0/gcc/Common-Type-Attributes.html
Change-Id: I9a2b2fbe18d5a58a8f9aeb2726a0623f3484c88e
Signed-off-by: Max Yu <maxlyu@google.com>
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| 5d3c1f58 | 06-Sep-2022 |
Akram Ahmad <Akram.Ahmad@arm.com> |
fix(cpus): workaround for Cortex-A78C erratum 2376749
Cortex-A78C erratum 2376749 is a Cat B erratum that applies
to revisions r0p1 and r0p2 of the A78C and is currently open.
The workaround is to s
fix(cpus): workaround for Cortex-A78C erratum 2376749
Cortex-A78C erratum 2376749 is a Cat B erratum that applies
to revisions r0p1 and r0p2 of the A78C and is currently open.
The workaround is to set CPUACTLR2_EL1[0] to 1 to force
PLDW/PFRM ST to behave like PLD/PRFM LD and not cause
invalidations to other PE caches.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest
Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I3b29f4b7f167bf499d5d11ffef91a94861bd1383
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| b781fcf1 | 01-Sep-2022 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
fix(cpus): workaround for Cortex-A710 2216384
Cortex-A710 erratum 2216384 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set
CPUACTLR5_
fix(cpus): workaround for Cortex-A710 2216384
Cortex-A710 erratum 2216384 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set
CPUACTLR5_EL1[17] to 1 and applying an instruction patching sequence.
Setting this bit, along with these instructions will prevent the
deadlock, and thereby avoids the reset of the processor.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Change-Id: I2821591c23f854c12111288ad1fd1aef45db6add
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
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| 945f0ad9 | 06-Sep-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(errata): workaround for Cortex-A510 erratum 2347730" into integration |
| 04f28f89 | 05-Sep-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "mt8188" into integration
* changes:
feat(mt8188): add pinctrl support
feat(mt8188): add RTC support
feat(mt8188): add pmic and pwrap support
refator(mediatek): move
Merge changes from topic "mt8188" into integration
* changes:
feat(mt8188): add pinctrl support
feat(mt8188): add RTC support
feat(mt8188): add pmic and pwrap support
refator(mediatek): move pmic.[c|h] to common folder
refator(mediatek): move common definitions of pmic wrap to common folder
feat(mt8188): add IOMMU enable control in SiP service
feat(mt8188): add display port control in SiP service
fix(mediatek): use uppercase for definition
feat(mediatek): move dp drivers to common folder
feat(mediatek): move mtk_cirq.c drivers to cirq folder
feat(mt8188): initialize GIC
feat(mt8188): initialize systimer
feat(mt8188): initialize platform for MediaTek MT8188
refator(mediatek): remove unused files
refator(mediatek): move drivers folder in common to plat/mediatek
feat(mediatek): support coreboot BL31 loading
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| de310e1e | 07-Jul-2022 |
Rex-BC Chen <rex-bc.chen@mediatek.com> |
feat(mt8188): initialize platform for MediaTek MT8188
- Add basic platform setup.
- Add MT8188 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.
- Add mt
feat(mt8188): initialize platform for MediaTek MT8188
- Add basic platform setup.
- Add MT8188 documentation at docs/plat/.
- Add generic CPU helper functions.
- Add basic register address.
- Add mtk_pm.c in lib/pm
TEST=build pass
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I5f8617c42ffba2c9d3a16f3980cb75fda5624031
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| 9a5dec66 | 02-Sep-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "fix(bl31): allow use of EHF with S-EL2 SPMC" into integration |
| 11d448c9 | 21-Jul-2022 |
Akram Ahmad <Akram.Ahmad@arm.com> |
fix(errata): workaround for Cortex-A510 erratum 2347730
Cortex-A510 erratum 2347730 is a Cat B erratum that affects
revisions r0p0, r0p1, r0p2, r0p3, r1p0 and r1p1. It is
fixed in r1p2. The workarou
fix(errata): workaround for Cortex-A510 erratum 2347730
Cortex-A510 erratum 2347730 is a Cat B erratum that affects
revisions r0p0, r0p1, r0p2, r0p3, r1p0 and r1p1. It is
fixed in r1p2. The workaround is to set CPUACTLR_EL1[17]
to 1, which will disable specific microarchitectural clock
gating behaviour.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1873351/latest
https://developer.arm.com/documentation/SDEN1873361/latest
Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I115386284c2d91bd61515142f971e2e72de43e68
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| 7c2fe62f | 25-Jul-2022 |
Raghu Krishnamurthy <raghu.ncstate@gmail.com> |
fix(bl31): allow use of EHF with S-EL2 SPMC
Currently, when SPMC at S-EL2 is used, we cannot use the RAS framework
to handle Group 0 interrupts. This is required on platforms where first
level of tr
fix(bl31): allow use of EHF with S-EL2 SPMC
Currently, when SPMC at S-EL2 is used, we cannot use the RAS framework
to handle Group 0 interrupts. This is required on platforms where first
level of triaging needs to occur at EL3, before forwarding RAS handling
to a secure partition running atop an SPMC (hafnium).
The RAS framework depends on EHF and EHF registers for Group 0
interrupts to be trapped to EL3 when execution is both in secure world
and normal world. However, an FF-A compliant SPMC requires secure
interrupts to be trapped by the SPMC when execution is in S-EL0/S-EL1.
Consequently, the SPMC (hafnium) is incompatible with EHF, since it is
not re-entrant, and a Group 0 interrupt trapped to EL3 when execution is
in secure world, cannot be forwarded to an SP running atop SPMC.
This patch changes EHF to only register for Group 0 interrupts to be
trapped to EL3 when execution is in normal world and also makes it a
valid routing model to do so, when EL3_EXCEPTION_HANDLING is set (when
enabling the RAS framework).
Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
Change-Id: I72d4cf4d8ecc549a832d1c36055fbe95866747fe
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| 00460e7d | 30-Aug-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "docs(marvell): document UART image downloading" into integration |
| 748749a8 | 24-Aug-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(errata): workaround for Cortex-A510 erratum 2371937" into integration |
| ac2605e6 | 24-Aug-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(errata): workaround for Cortex-A78C erratum 2395411" into integration |
| 4b6f0026 | 19-Jul-2022 |
Akram Ahmad <Akram.Ahmad@arm.com> |
fix(errata): workaround for Cortex-A78C erratum 2395411
Cortex-A78C erratum 2395411 is a Cat B erratum that affects
revisions r0p1 and r0p2, and is currently open. The workaround
is to set CPUACTLR2
fix(errata): workaround for Cortex-A78C erratum 2395411
Cortex-A78C erratum 2395411 is a Cat B erratum that affects
revisions r0p1 and r0p2, and is currently open. The workaround
is to set CPUACTLR2_EL1[40] to 1, which will disable folding
of demand requests into older prefetches with L2 miss requests
outstanding.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest
Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I4f0fb278ac20a2eb4dd7e4efd1b1246dd85e48c4
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| a67c1b1b | 22-Jul-2022 |
Akram Ahmad <Akram.Ahmad@arm.com> |
fix(errata): workaround for Cortex-A510 erratum 2371937
Cortex-A510 erratum 2371937 is a Cat B erratum that applies
to revisions r0p0, r0p1, r0p2, r0p3, r1p0, and r1p1. It is
fixed in r1p2. The work
fix(errata): workaround for Cortex-A510 erratum 2371937
Cortex-A510 erratum 2371937 is a Cat B erratum that applies
to revisions r0p0, r0p1, r0p2, r0p3, r1p0, and r1p1. It is
fixed in r1p2. The workaround is to set the ATOM field of
CPUECTLR_EL1 (bits [40:38]) to 0b010, which will force all
cacheable atomic operations to be executed near.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1873351/latest
https://developer.arm.com/documentation/SDEN1873361/latest
Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: Ia219a609a3397e39631de65831ecff8a3cd1227e
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| 3280e5e6 | 21-Jul-2022 |
Akram Ahmad <Akram.Ahmad@arm.com> |
fix(errata): workaround for Cortex-A710 erratum 2147715
Cortex-A710 erratum 2147715 is a Cat B erratum that applies
to revision r2p0 of the CPU, and is fixed in r2p1. The work-
around is to set CPUA
fix(errata): workaround for Cortex-A710 erratum 2147715
Cortex-A710 erratum 2147715 is a Cat B erratum that applies
to revision r2p0 of the CPU, and is fixed in r2p1. The work-
around is to set CPUACTLR_EL1[22]=1. Setting this will cause
the CFP instruction to invalidate all branch predictor resources
regardless of the context.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I94771bc1fc9b65a0c17d75200ec2b1df8a3279c6
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