History log of /rk3399_ARM-atf/docs/ (Results 1351 – 1375 of 3294)
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702b46cb10-Nov-2022 Govindraj Raja <govindraj.raja@arm.com>

chore(docs): fix broken url references to arm procedure call

Couple for urls under section: `5.6. Use of built-in C and libc
data types` from docs has broken urls since the new arm procedure
call do

chore(docs): fix broken url references to arm procedure call

Couple for urls under section: `5.6. Use of built-in C and libc
data types` from docs has broken urls since the new arm procedure
call doc is moved to be part of `ARM-software/abi-aa`.

Change-Id: Ied184ed56c8335d4cbc687e56962439091a18e42
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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4fdeaffe01-Nov-2022 Boyan Karatotev <boyan.karatotev@arm.com>

fix(cpus): workaround for Cortex-A77 erratum 2743100

Cortex-A77 erratum 2743100 is a Cat B erratum that applies to revisions
r0p0, r1p0, r1p1, and is still open. The workaround is to insert a dsb
be

fix(cpus): workaround for Cortex-A77 erratum 2743100

Cortex-A77 erratum 2743100 is a Cat B erratum that applies to revisions
r0p0, r1p0, r1p1, and is still open. The workaround is to insert a dsb
before the isb in the power down sequence.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1152370/latest

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I8e49a2dac8611f31ace249a17ae7a90cd60e742a

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04c7303b04-Nov-2022 Okash Khawaja <okash@google.com>

feat(cpus): make cache ops conditional

When a core is in debug recovery mode its caches are not invalidated
upon reset, so the L1 and L2 cache contents from before reset are
observable after reset.

feat(cpus): make cache ops conditional

When a core is in debug recovery mode its caches are not invalidated
upon reset, so the L1 and L2 cache contents from before reset are
observable after reset. Similarly, debug recovery mode of DynamIQ
cluster ensures that contents of the shared L3 cache are also not
invalidated upon transition to On mode.

Booting cores in debug recovery mode means booting with caches disabled
and preserving the caches until a point where software can dump the
caches and retrieve their contents. TF-A however unconditionally cleans
and invalidates caches at multiple points during boot. This can lead to
memory corruption as well as loss of cache contents to be used for
debugging.

This patch fixes this by calling a platform hook before performing CMOs
in helper routines in cache_helpers.S. The platform hook plat_can_cmo is
an assembly routine which must not clobber x2 and x3, and avoid using
stack. The whole checking is conditional upon `CONDITIONAL_CMO` which
can be set at compile time.

Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I172e999e4acd0f872c24056e647cc947ee54b193

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0d41e17410-Nov-2022 Manish Pandey <manish.pandey2@arm.com>

Merge "chore(docs): move deprecated platforms information around" into integration

c87e1f6209-Nov-2022 Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Merge changes from topic "errata" into integration

* changes:
fix(cpus): workaround for Cortex-A76 erratum 2743102
fix(cpus): workaround for Neoverse N1 erratum 2743102

00bf236e09-Nov-2022 Manish V Badarkhe <manish.badarkhe@arm.com>

Merge "refactor(trng): cleanup the existing TRNG support" into integration

00c322b309-Nov-2022 Soby Mathew <soby.mathew@arm.com>

Merge "docs(rme): add instruction to build rmm" into integration

51a96cee09-Nov-2022 Joanna Farley <joanna.farley@arm.com>

Merge "docs(security): rename Makalu and SB optimisation" into integration

0e5fd06509-Nov-2022 Joanna Farley <joanna.farley@arm.com>

Merge "docs(maintainers): update qti maintainer" into integration

99d9ce8a02-Nov-2022 Shruti Gupta <shruti.gupta@arm.com>

docs(rme): add instruction to build rmm

Add documentation to build and run TF-A with RMM,
Linux kernel and TFTF Realm Payload.

Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: I951b41a

docs(rme): add instruction to build rmm

Add documentation to build and run TF-A with RMM,
Linux kernel and TFTF Realm Payload.

Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: I951b41a144aabe0fec16eb933d7f005a65f06fb2

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2f3d647b09-Nov-2022 Manish V Badarkhe <manish.badarkhe@arm.com>

Merge "docs: add link to DCO" into integration

a6a1dcbe08-Nov-2022 Sandrine Bailleux <sandrine.bailleux@arm.com>

chore(docs): move deprecated platforms information around

We used to have a dedicated page for deprecated platforms information.
This document contained 2 pieces of information:

a) the process for

chore(docs): move deprecated platforms information around

We used to have a dedicated page for deprecated platforms information.
This document contained 2 pieces of information:

a) the process for deprecating a platform port;
b) the list of deprecated platforms to this day.

I think it makes more sense to move b) to the platforms ports landing
page, such that it is more visible.

This also has the nice effect to move the 'Deprecated platforms' title
as the last entry of the 'Platform ports' table of contents, like so:

- Platform ports
- 1. Allwinner ARMv8 SoCs
- 2. Arm Development Platforms
...
- 39. Broadcom Stingray
- Deprecated platforms

instead of it being lost in the middle of supported platform ports.

Regarding a), this gets moved under the "Processes & Policies" section.
More specifically, it gets clubbed with the existing platform
compatibility policy. The combined document gets renamed into a
"Platforms Ports Policy" document.

Change-Id: I6e9ce2abc68b8a8ac88e7bd5f21749c14c9a2af6
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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e28d403c09-Nov-2022 Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge "chore(docs): refresh platform ports landing page" into integration

78e7b2b409-Nov-2022 Olivier Deprez <olivier.deprez@arm.com>

Merge "feat: pass SMCCCv1.3 SVE hint bit to dispatchers" into integration

b80cd43105-Nov-2022 Bipin Ravi <bipin.ravi@arm.com>

docs(security): rename Makalu and SB optimisation

Changing Makalu reference to the public name Cortex-A715. Also, added
a note on use of SB instruction for all CPUs supporting ENABLE_FEAT_SB.

Signe

docs(security): rename Makalu and SB optimisation

Changing Makalu reference to the public name Cortex-A715. Also, added
a note on use of SB instruction for all CPUs supporting ENABLE_FEAT_SB.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I98bd36c684fa7ae79bd4e8e641fd73404435c202

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c2a634b708-Nov-2022 Chris Kay <chris.kay@arm.com>

docs: add link to DCO

The link to the Developer Certificate of Origin was mistakenly removed
in a patch some time ago. This change re-adds it.

Change-Id: Ia8aed055cb449cdf4c1aaeac9b81ca15099e73f5
S

docs: add link to DCO

The link to the Developer Certificate of Origin was mistakenly removed
in a patch some time ago. This change re-adds it.

Change-Id: Ia8aed055cb449cdf4c1aaeac9b81ca15099e73f5
Signed-off-by: Chris Kay <chris.kay@arm.com>

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5988a80702-Nov-2022 Manish Pandey <manish.pandey2@arm.com>

docs: document do_panic() and panic() helper functions

panic() and do_panic() are widely used helper functions called when
encountering a critical failure that cannot be recovered from.
Document the

docs: document do_panic() and panic() helper functions

panic() and do_panic() are widely used helper functions called when
encountering a critical failure that cannot be recovered from.
Document them in porting guide. Also, remove panic() documentation
from PSCI guide(where it is unused anyways).

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ib0965cce56c03d0de5ac0d05d5714a6942793ede

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0b22e59111-Oct-2022 Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

refactor(trng): cleanup the existing TRNG support

This patch adds the following changes to complete the existing
TRNG implementation:

1. Adds a feature specific scope for buildlog generation.
2. Up

refactor(trng): cleanup the existing TRNG support

This patch adds the following changes to complete the existing
TRNG implementation:

1. Adds a feature specific scope for buildlog generation.
2. Updates the docs on the build flag "TRNG_SUPPORT" and its values.
3. Makefile update and improves the existing comments at few sections
for better understanding of the underlying logic.

Change-Id: I3f72f0ccd5c94005a2df87158cf23199d2160d37
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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2fe661c208-Nov-2022 Sandrine Bailleux <sandrine.bailleux@arm.com>

chore(docs): refresh platform ports landing page

- Remove mentions of Arm SGM-775 and MediaTek MT6795 platforms.
Both platform ports were deleted from TF-A source tree in the
last release (v2

chore(docs): refresh platform ports landing page

- Remove mentions of Arm SGM-775 and MediaTek MT6795 platforms.
Both platform ports were deleted from TF-A source tree in the
last release (v2.7).

- Remove mention of Arm Morello platform, as it now has a dedicated
documentation page accessible from the table of contents
(see docs/plat/arm/morello/).

Change-Id: Ie3acdddab81f5589bb36114a8a766200f5b08ad4
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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46cc41d510-Oct-2022 Manish Pandey <manish.pandey2@arm.com>

fix(ras): restrict RAS support for NS world

Current RAS framework in TF-A only supports handling errors originating
from NS world but the HANDLE_EA_EL3_FIRST flag configures it for all
lower Els. To

fix(ras): restrict RAS support for NS world

Current RAS framework in TF-A only supports handling errors originating
from NS world but the HANDLE_EA_EL3_FIRST flag configures it for all
lower Els. To make the current design of RAS explicit, rename this macro
to HANDLE_EA_EL3_FIRST_NS and set EA bit in scr_el3 only when
switching to NS world.

Note: I am unaware of any platform which traps errors originating in
Secure world to EL3, if there is any such platform then it need to
be explicitly implemented in TF-A

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: If58eb201d8fa792c16325c85c26056e9b409b750

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/rk3399_ARM-atf/Makefile
/rk3399_ARM-atf/bl1/bl1.ld.S
/rk3399_ARM-atf/bl2/bl2.ld.S
/rk3399_ARM-atf/bl31/aarch64/ea_delegate.S
/rk3399_ARM-atf/common/aarch64/debug.S
/rk3399_ARM-atf/common/backtrace/backtrace.c
components/ras.rst
getting_started/build-options.rst
plat/marvell/armada/build.rst
/rk3399_ARM-atf/include/common/debug.h
/rk3399_ARM-atf/lib/el3_runtime/aarch64/context_mgmt.c
/rk3399_ARM-atf/make_helpers/defaults.mk
/rk3399_ARM-atf/plat/arm/board/tc/platform.mk
/rk3399_ARM-atf/plat/arm/css/sgi/sgi-common.mk
/rk3399_ARM-atf/plat/common/aarch64/plat_common.c
/rk3399_ARM-atf/plat/hisilicon/hikey960/aarch64/hikey960_common.c
/rk3399_ARM-atf/plat/hisilicon/hikey960/hikey960_bl2_mem_params_desc.c
/rk3399_ARM-atf/plat/hisilicon/hikey960/hikey960_bl2_setup.c
/rk3399_ARM-atf/plat/hisilicon/hikey960/hikey960_bl31_setup.c
/rk3399_ARM-atf/plat/hisilicon/hikey960/hikey960_def.h
/rk3399_ARM-atf/plat/hisilicon/hikey960/hikey960_el3_spmc_logical_sp.c
/rk3399_ARM-atf/plat/hisilicon/hikey960/hikey960_image_load.c
/rk3399_ARM-atf/plat/hisilicon/hikey960/hikey960_io_storage.c
/rk3399_ARM-atf/plat/hisilicon/hikey960/hikey960_private.h
/rk3399_ARM-atf/plat/hisilicon/hikey960/include/plat.ld.S
/rk3399_ARM-atf/plat/hisilicon/hikey960/include/platform_def.h
/rk3399_ARM-atf/plat/hisilicon/hikey960/platform.mk
/rk3399_ARM-atf/plat/marvell/armada/a3k/common/a3700_common.mk
/rk3399_ARM-atf/plat/marvell/armada/a3k/common/a3700_ea.c
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/platform_t194.mk
/rk3399_ARM-atf/plat/qti/common/inc/qti_plat.h
/rk3399_ARM-atf/plat/qti/common/src/qti_common.c
/rk3399_ARM-atf/plat/qti/sc7180/inc/platform_def.h
/rk3399_ARM-atf/plat/qti/sc7180/inc/qti_map_chipinfo.h
/rk3399_ARM-atf/plat/qti/sc7280/inc/platform_def.h
/rk3399_ARM-atf/plat/qti/sc7280/inc/qti_map_chipinfo.h
/rk3399_ARM-atf/plat/renesas/common/common.mk
/rk3399_ARM-atf/plat/ti/k3/common/plat_common.mk
/rk3399_ARM-atf/services/std_svc/drtm/drtm_main.c
/rk3399_ARM-atf/services/std_svc/drtm/drtm_main.h
/rk3399_ARM-atf/services/std_svc/spm/el3_spmc/spmc_shared_mem.c
0fe7b9f211-Oct-2022 Olivier Deprez <olivier.deprez@arm.com>

feat: pass SMCCCv1.3 SVE hint bit to dispatchers

SMCCCv1.3 introduces the SVE hint bit added to the SMC FID (bit 16)
denoting that the world issuing an SMC doesn't expect the callee to
preserve the

feat: pass SMCCCv1.3 SVE hint bit to dispatchers

SMCCCv1.3 introduces the SVE hint bit added to the SMC FID (bit 16)
denoting that the world issuing an SMC doesn't expect the callee to
preserve the SVE state (FFR, predicates, Zn vector bits greater than
127). Update the generic SMC handler to copy the SVE hint bit state
to SMC flags and mask out the bit by default for the services called
by the standard dispatcher. It is permitted by the SMCCC standard to
ignore the bit as long as the SVE state is preserved. In any case a
callee must preserve the NEON state (FPCR/FPSR, Vn 128b vectors)
whichever the SVE hint bit state.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I2b163ed83dc311b8f81f96b23c942829ae9fa1b5

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85918dfd08-Nov-2022 Muhammad Arsath K F <quic_mkf@quicinc.com>

docs(maintainers): update qti maintainer

Add Muhammad Arsath K F in qti maintainer

Signed-off-by: Muhammad Arsath K F <quic_mkf@quicinc.com>
Change-Id: I71e6cc72b3c658730abe5255977f3b93dd7e4563

de89b28206-Nov-2022 Pali Rohár <pali@kernel.org>

docs(marvell): fix typo 8K => A8K

It is Armada 80x0, hence A8K (like A7K).

Change-Id: I4888b472204ecd19bfe9b8c89adaa1a99b01dd5f
Signed-off-by: Pali Rohár <pali@kernel.org>

832df3cc10-Oct-2022 Chris Kay <chris.kay@arm.com>

docs(commit-style): fix incorrect instructions for adding scopes

Change-Id: I3ce7abd1c21b084dea6b618c603f71b5bb4c50e8
Signed-off-by: Chris Kay <chris.kay@arm.com>

10c969c510-Oct-2022 Chris Kay <chris.kay@arm.com>

docs(prerequisites): update Node.js prerequisites documentation

This change updates the version of the Node Version Manager suggested by
the prerequisites documentation. The NVM installation command

docs(prerequisites): update Node.js prerequisites documentation

This change updates the version of the Node Version Manager suggested by
the prerequisites documentation. The NVM installation command line hint
has been replaced with the snippet provided by NVM's user guide, and the
second line now automatically installs a version of Node.js compatible
with TF-A's repository scripts.

Change-Id: I6ef5e504118238716ceb45a52083450c424c5d20
Signed-off-by: Chris Kay <chris.kay@arm.com>

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