| 712a32d9 | 20-Oct-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(cpus): workaround for Cortex-A510 erratum 2666669" into integration |
| 4e7983b7 | 20-Oct-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "feat(ethos-n)!: add support for SMMU streams" into integration |
| de7e9b56 | 26-Sep-2022 |
Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> |
docs(imx8m): update for high assurance boot
Add a section into documentation listing the support for High Assurance
Boot (HABv4), note on the DRAM mapping, and reference to the external
documentatio
docs(imx8m): update for high assurance boot
Add a section into documentation listing the support for High Assurance
Boot (HABv4), note on the DRAM mapping, and reference to the external
documentation.
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Change-Id: Iaca97f4ac2595e35de2664a880394519f96eca07
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| 81f4abb8 | 23-Sep-2022 |
Daniel Boulby <daniel.boulby@arm.com> |
docs(prerequisites): upgrade to Mbed TLS 2.28.1
In anticpation of the next Trusted Firmware release update the to newest
2.x Mbed TLS library [1].
Note that the Mbed TLS project published version 3
docs(prerequisites): upgrade to Mbed TLS 2.28.1
In anticpation of the next Trusted Firmware release update the to newest
2.x Mbed TLS library [1].
Note that the Mbed TLS project published version 3.x some time ago.
However, as this is a major release with API breakages, upgrading to
this one might require some more involved changes in TF-A, which we are
not ready to do. We shall upgrade to Mbed TLS 3.x after the v2.8 release
of TF-A.
[1] https://github.com/Mbed-TLS/mbedtls/tree/v2.28.1
Change-Id: I7594ad062a693d2ecc3b1705e944dce2c3c43bb2
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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| 60c43943 | 14-Oct-2022 |
Mikael Olsson <mikael.olsson@arm.com> |
docs(maintainers): add NPU driver owners
Code owners have been added for the Arm(R) Ethos(TM)-N NPU driver.
Change-Id: I0bda0d95151cdff5cd3a793c6c0e9ef6a9a5f50b
Signed-off-by: Mikael Olsson <mikael
docs(maintainers): add NPU driver owners
Code owners have been added for the Arm(R) Ethos(TM)-N NPU driver.
Change-Id: I0bda0d95151cdff5cd3a793c6c0e9ef6a9a5f50b
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
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| afb5d069 | 21-Sep-2022 |
Akram Ahmad <Akram.Ahmad@arm.com> |
fix(cpus): workaround for Cortex-A510 erratum 2666669
Cortex-A510 erratum 2666669 applies to revisions r1p1 and lower,
and is fixed in r1p2. The errata is mitigated by setting
IMP_CPUACTLR_EL1[38] t
fix(cpus): workaround for Cortex-A510 erratum 2666669
Cortex-A510 erratum 2666669 applies to revisions r1p1 and lower,
and is fixed in r1p2. The errata is mitigated by setting
IMP_CPUACTLR_EL1[38] to 1.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1873351/latest
https://developer.arm.com/documentation/SDEN1873361/latest
Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: Ief27e4a155e43e75f05f2710d0c7bd5da2dec43f
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| 53e4c160 | 11-Oct-2022 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "fvp_dts_rework" into integration
* changes:
fix(fvp_ve): fdts: Fix vexpress,config-bus subnode names
fix(fvp): fdts: Fix idle-states entry method
fix(fvp): fdts: fix
Merge changes from topic "fvp_dts_rework" into integration
* changes:
fix(fvp_ve): fdts: Fix vexpress,config-bus subnode names
fix(fvp): fdts: Fix idle-states entry method
fix(fvp): fdts: fix memtimer subframe addressing
feat(fvp): fdts: update rtsm_ve DT files from the Linux kernel
refactor(fvp): fdts: consolidate GICv2 base FVP DT files
refactor(fvp): fdts: consolidate GICv3 base FVP DT files
feat(fvp): dts: drop 32-bit .dts files
refactor(fvp): fdts: merge motherboard .dtsi files
refactor(fvp_ve): fdts: prepare Cortex-A5 and A7 model DTs
fix(fvp): fdts: unify and fix PSCI nodes
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| b9203307 | 19-Aug-2022 |
Andre Przywara <andre.przywara@arm.com> |
feat(fvp): dts: drop 32-bit .dts files
Conceptually the DT is a hardware description, as such it's independent
from the instruction set that a DT client uses. So having separate DTs
for aarch32 and
feat(fvp): dts: drop 32-bit .dts files
Conceptually the DT is a hardware description, as such it's independent
from the instruction set that a DT client uses. So having separate DTs
for aarch32 and aarch64 does not make sense and is not needed.
Probably due to historic reasons (a Linux bug fixed in 2016 with Linux
commit ba6dea4f7ced, in Linux v4.8) the CPU reg property was using a
different size between aarch64 and aarch32, even though the size of it
is solely governed by the parent's #address-cells property.
Consolidate this to be always 2, and always use two cells to describe
the CPU's MPIDR register.
This removes the last difference of the -aarch32 versions of the FVP
DT files, so just remove all of them. The respective versions without
that suffix can now be used with AArch32 DT clients as well.
Also remove the respective part in the documentation.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I45d3a2cbba8e04595a741e1cf41900377952673e
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| a2506c31 | 11-Oct-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "revert(cpus): "Revert workaround for A77 erratum 1800714"" into integration |
| 08e2fdbd | 27-Sep-2022 |
Boyan Karatotev <boyan.karatotev@arm.com> |
revert(cpus): "Revert workaround for A77 erratum 1800714"
Reinstate the workaround introduced in commit
9bbc03a6e0608a949d66d9da6db12a455b452bfb. The cited change to the SDEN
could not be found and
revert(cpus): "Revert workaround for A77 erratum 1800714"
Reinstate the workaround introduced in commit
9bbc03a6e0608a949d66d9da6db12a455b452bfb. The cited change to the SDEN
could not be found and there are no known problems with the workaround.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Iec9938f173e7565024aca798f224df339de90806
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| 1bc78557 | 16-Sep-2022 |
Tamas Ban <tamas.ban@arm.com> |
docs: add PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE to porting-guide.rst
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I79761347919a0dfa86a29b5424f1d34fc4ab91cb |
| 50a43b0f | 29-Jun-2022 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs(drtm): steps to run DRTM implementation
Documented steps to run DRTM implementation.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I30dd8c1088a54a8906389c2584d922862610
docs(drtm): steps to run DRTM implementation
Documented steps to run DRTM implementation.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I30dd8c1088a54a8906389c2584d922862610dae0
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| b3b227ff | 22-Jun-2022 |
Lucian Paul-Trifu <lucian.paultrifu@gmail.com> |
docs(drtm): add platform APIs for DRTM
Documented platform APIs for DRTM
Signed-off-by: Lucian Paul-Trifu <lucian.paultrifu@gmail.com>
Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Cha
docs(drtm): add platform APIs for DRTM
Documented platform APIs for DRTM
Signed-off-by: Lucian Paul-Trifu <lucian.paultrifu@gmail.com>
Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Change-Id: I22749c26bbe7b3271705dd3db07e8597fce6225b
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| b139f1cf | 15-Aug-2022 |
Mikael Olsson <mikael.olsson@arm.com> |
feat(ethos-n)!: add support for SMMU streams
The Arm(R) Ethos(TM)-N NPU driver now supports configuring the SMMU
streams that the NPU shall use and will therefore no longer delegate
access to these
feat(ethos-n)!: add support for SMMU streams
The Arm(R) Ethos(TM)-N NPU driver now supports configuring the SMMU
streams that the NPU shall use and will therefore no longer delegate
access to these registers to the non-secure world. In order for the
driver to support this, the device tree parsing has been updated to
support parsing the allocators used by the NPU and what SMMU stream that
is associated with each allocator.
To keep track of what NPU device each allocator is associated with, the
resulting config from the device tree parsing will now group the NPU
cores and allocators into their respective NPU device.
The SMC API has been changed to allow the caller to specify what
allocator the NPU shall be configured to use and the API version has
been bumped to indicate this change.
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: I6ac43819133138614e3f55a014e93466fe3d5277
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| bd063a73 | 21-Sep-2022 |
Joel Goddard <joel.goddard@arm.com> |
refactor(cpu): use the updated IP name for Demeter CPU
Neoverse Demeter CPU has been renamed to Neoverse V2 CPU.
Correspondingly, update the CPU library, file names and other
references to use the u
refactor(cpu): use the updated IP name for Demeter CPU
Neoverse Demeter CPU has been renamed to Neoverse V2 CPU.
Correspondingly, update the CPU library, file names and other
references to use the updated IP name.
Signed-off-by: Joel Goddard <joel.goddard@arm.com>
Change-Id: Ia4bf45bf47807c06f4c966861230faea420d088f
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| e8f4ec1a | 03-Oct-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "st_uart_updates" into integration
* changes:
feat(stm32mp1): add early console in SP_min
feat(st): properly manage early console
feat(st-uart): manage STM32MP_RECONFI
Merge changes from topic "st_uart_updates" into integration
* changes:
feat(stm32mp1): add early console in SP_min
feat(st): properly manage early console
feat(st-uart): manage STM32MP_RECONFIGURE_CONSOLE
docs(st): introduce STM32MP_RECONFIGURE_CONSOLE
feat(st): add trace for early console
fix(stm32mp1): enable crash console in FIQ handler
feat(st-uart): add initialization with the device tree
refactor(stm32mp1): move DT_UART_COMPAT in include file
feat(stm32mp1): configure the serial boot load address
fix(stm32mp1): update the FIP load address for serial boot
refactor(st): configure baudrate for UART programmer
refactor(st-uart): compute the over sampling dynamically
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| 2c16b802 | 30-Sep-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(ras): trap "RAS error record" accesses only for NS" into integration |
| ea7aee20 | 29-Sep-2022 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "fix(rmmd): return X4 output value" into integration |
| 00e8f79c | 27-Sep-2022 |
Manish Pandey <manish.pandey2@arm.com> |
fix(ras): trap "RAS error record" accesses only for NS
RAS_TRAP_LOWER_EL_ERR_ACCESS was used to prevent access to RAS error
record registers (RAS ERR* & RAS ERX*) from lower EL's in any security
sta
fix(ras): trap "RAS error record" accesses only for NS
RAS_TRAP_LOWER_EL_ERR_ACCESS was used to prevent access to RAS error
record registers (RAS ERR* & RAS ERX*) from lower EL's in any security
state. To give more fine grain control per world basis re-purpose this
macro to RAS_TRAP_NS_ERR_REC_ACCESS, which will enable the trap only
if Error record registers are accessed from NS.
This will also help in future scenarios when RAS handling(in Firmware
first handling paradigm)can be offloaded to a secure partition.
This is first patch in series to refactor RAS framework in TF-A.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ifa7f60bc8c82c9960adf029001bc36c443016d5d
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| 8e51ccca | 23-Sep-2022 |
AlexeiFedorov <Alexei.Fedorov@arm.com> |
fix(rmmd): return X4 output value
Return values contained in 'smc_result' structure
are shifted down by one register:
X1 written by RMM is returned to NS in X0 and
X5 is returned in X4.
Signed-off-
fix(rmmd): return X4 output value
Return values contained in 'smc_result' structure
are shifted down by one register:
X1 written by RMM is returned to NS in X0 and
X5 is returned in X4.
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I92907ac3ff3bac8554643ae7c198a4a758c38cb3
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| 14ec900a | 27-Sep-2022 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "docs(maintainers): add myself as TC code owner" into integration |
| 8fecda3c | 21-Sep-2022 |
Anders Dellien <anders.dellien@arm.com> |
docs(maintainers): add myself as TC code owner
Signed-off-by: Anders Dellien <anders.dellien@arm.com>
Change-Id: Ic67334bf1a979cb7b7355d0dcca7eb94752c4611 |
| d8d0ea9a | 26-Sep-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "docs(fwu): update firmware update design" into integration |
| 156709dd | 13-Sep-2022 |
Yann Gautier <yann.gautier@foss.st.com> |
docs(st): introduce STM32MP_RECONFIGURE_CONSOLE
This flag will be used in BL32, to reconfigure UART parameters for
the early or crash console. By default, it is zero, as UART is
already configured i
docs(st): introduce STM32MP_RECONFIGURE_CONSOLE
This flag will be used in BL32, to reconfigure UART parameters for
the early or crash console. By default, it is zero, as UART is
already configured in BL2.
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I7b28ff489479ab04a2fade027933524cdd36e959
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| 4b2f23e5 | 15-Mar-2022 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
feat(stm32mp1): configure the serial boot load address
For product with 128MB DDR size, the OP-TEE is located at the end
of the DDR and the FIP can't be loaded at the default location
because it ove
feat(stm32mp1): configure the serial boot load address
For product with 128MB DDR size, the OP-TEE is located at the end
of the DDR and the FIP can't be loaded at the default location
because it overlap the OP-TEE final location. So the default value
for DWL_BUFFER_BASE is invalid.
To avoid this conflict the serial boot load address = DWL_BUFFER_BASE
can be modified with a configuration flags.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ie27b87c10c57fea5d4c6200ce4f624e775b9a080
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