1 /* 2 * Copyright (c) 2020-2022, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 #include <lib/xlat_tables/xlat_tables_defs.h> 12 #include <plat/arm/board/common/board_css_def.h> 13 #include <plat/arm/board/common/v2m_def.h> 14 #include <plat/arm/common/arm_def.h> 15 #include <plat/arm/common/arm_spm_def.h> 16 #include <plat/arm/css/common/css_def.h> 17 #include <plat/arm/soc/common/soc_css_def.h> 18 #include <plat/common/common_def.h> 19 20 #define PLATFORM_CORE_COUNT 8 21 22 #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ 23 24 /* 25 * The top 16MB of ARM_DRAM1 is configured as secure access only using the TZC, 26 * its base is ARM_AP_TZC_DRAM1_BASE. 27 * 28 * Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for: 29 * - BL32_BASE when SPD_spmd is enabled 30 * - Region to load Trusted OS 31 */ 32 #define TC_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \ 33 TC_TZC_DRAM1_SIZE) 34 #define TC_TZC_DRAM1_SIZE UL(0x02000000) /* 32 MB */ 35 #define TC_TZC_DRAM1_END (TC_TZC_DRAM1_BASE + \ 36 TC_TZC_DRAM1_SIZE - 1) 37 38 #define TC_NS_DRAM1_BASE ARM_DRAM1_BASE 39 #define TC_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 40 ARM_TZC_DRAM1_SIZE - \ 41 TC_TZC_DRAM1_SIZE) 42 #define TC_NS_DRAM1_END (TC_NS_DRAM1_BASE + \ 43 TC_NS_DRAM1_SIZE - 1) 44 45 /* 46 * Mappings for TC DRAM1 (non-secure) and TC TZC DRAM1 (secure) 47 */ 48 #define TC_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 49 TC_NS_DRAM1_BASE, \ 50 TC_NS_DRAM1_SIZE, \ 51 MT_MEMORY | MT_RW | MT_NS) 52 53 54 #define TC_MAP_TZC_DRAM1 MAP_REGION_FLAT( \ 55 TC_TZC_DRAM1_BASE, \ 56 TC_TZC_DRAM1_SIZE, \ 57 MT_MEMORY | MT_RW | MT_SECURE) 58 59 #define PLAT_HW_CONFIG_DTB_BASE ULL(0x83000000) 60 #define PLAT_HW_CONFIG_DTB_SIZE ULL(0x8000) 61 62 #define PLAT_DTB_DRAM_NS MAP_REGION_FLAT( \ 63 PLAT_HW_CONFIG_DTB_BASE, \ 64 PLAT_HW_CONFIG_DTB_SIZE, \ 65 MT_MEMORY | MT_RO | MT_NS) 66 /* 67 * Max size of SPMC is 2MB for tc. With SPMD enabled this value corresponds to 68 * max size of BL32 image. 69 */ 70 #if defined(SPD_spmd) 71 #define PLAT_ARM_SPMC_BASE TC_TZC_DRAM1_BASE 72 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 73 #endif 74 75 /* 76 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 77 * plat_arm_mmap array defined for each BL stage. 78 */ 79 #if defined(IMAGE_BL31) 80 # if SPM_MM 81 # define PLAT_ARM_MMAP_ENTRIES 9 82 # define MAX_XLAT_TABLES 7 83 # define PLAT_SP_IMAGE_MMAP_REGIONS 7 84 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 85 # else 86 # define PLAT_ARM_MMAP_ENTRIES 8 87 # define MAX_XLAT_TABLES 8 88 # endif 89 #elif defined(IMAGE_BL32) 90 # define PLAT_ARM_MMAP_ENTRIES 8 91 # define MAX_XLAT_TABLES 5 92 #elif !USE_ROMLIB 93 # define PLAT_ARM_MMAP_ENTRIES 11 94 # define MAX_XLAT_TABLES 7 95 #else 96 # define PLAT_ARM_MMAP_ENTRIES 12 97 # define MAX_XLAT_TABLES 6 98 #endif 99 100 /* 101 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 102 * plus a little space for growth. 103 */ 104 #define PLAT_ARM_MAX_BL1_RW_SIZE 0xC000 105 106 /* 107 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 108 */ 109 110 #if USE_ROMLIB 111 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 112 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 113 #else 114 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 115 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 116 #endif 117 118 /* 119 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 120 * little space for growth. 121 */ 122 #if TRUSTED_BOARD_BOOT 123 # define PLAT_ARM_MAX_BL2_SIZE 0x20000 124 #else 125 # define PLAT_ARM_MAX_BL2_SIZE 0x14000 126 #endif 127 128 /* 129 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 130 * calculated using the current BL31 PROGBITS debug size plus the sizes of 131 * BL2 and BL1-RW 132 */ 133 #define PLAT_ARM_MAX_BL31_SIZE 0x3F000 134 135 /* 136 * Size of cacheable stacks 137 */ 138 #if defined(IMAGE_BL1) 139 # if TRUSTED_BOARD_BOOT 140 # define PLATFORM_STACK_SIZE 0x1000 141 # else 142 # define PLATFORM_STACK_SIZE 0x440 143 # endif 144 #elif defined(IMAGE_BL2) 145 # if TRUSTED_BOARD_BOOT 146 # define PLATFORM_STACK_SIZE 0x1000 147 # else 148 # define PLATFORM_STACK_SIZE 0x400 149 # endif 150 #elif defined(IMAGE_BL2U) 151 # define PLATFORM_STACK_SIZE 0x400 152 #elif defined(IMAGE_BL31) 153 # if SPM_MM 154 # define PLATFORM_STACK_SIZE 0x500 155 # else 156 # define PLATFORM_STACK_SIZE 0x400 157 # endif 158 #elif defined(IMAGE_BL32) 159 # define PLATFORM_STACK_SIZE 0x440 160 #endif 161 162 /* 163 * In the current implementation the RoT Service request that requires the 164 * biggest message buffer is the RSS_DELEGATED_ATTEST_GET_PLATFORM_TOKEN. The 165 * maximum required buffer size is calculated based on the platform-specific 166 * needs of this request. 167 */ 168 #define PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE 0x500 169 170 #define TC_DEVICE_BASE 0x21000000 171 #define TC_DEVICE_SIZE 0x5f000000 172 173 // TC_MAP_DEVICE covers different peripherals 174 // available to the platform 175 #define TC_MAP_DEVICE MAP_REGION_FLAT( \ 176 TC_DEVICE_BASE, \ 177 TC_DEVICE_SIZE, \ 178 MT_DEVICE | MT_RW | MT_SECURE) 179 180 181 #define TC_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 182 V2M_FLASH0_SIZE, \ 183 MT_DEVICE | MT_RO | MT_SECURE) 184 185 #define PLAT_ARM_NSTIMER_FRAME_ID 0 186 187 #if (TARGET_PLATFORM >= 2) 188 #define PLAT_ARM_TRUSTED_ROM_BASE 0x1000 189 #else 190 #define PLAT_ARM_TRUSTED_ROM_BASE 0x0 191 #endif 192 193 /* PLAT_ARM_TRUSTED_ROM_SIZE 512KB minus ROM base. */ 194 #define PLAT_ARM_TRUSTED_ROM_SIZE (0x00080000 - PLAT_ARM_TRUSTED_ROM_BASE) 195 196 #define PLAT_ARM_NSRAM_BASE 0x06000000 197 #define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ 198 199 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) 200 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 201 #define PLAT_ARM_DRAM2_END (PLAT_ARM_DRAM2_BASE + PLAT_ARM_DRAM2_SIZE - 1ULL) 202 203 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) 204 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 205 206 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 207 PLAT_SP_IMAGE_NS_BUF_SIZE) 208 209 /******************************************************************************* 210 * Memprotect definitions 211 ******************************************************************************/ 212 /* PSCI memory protect definitions: 213 * This variable is stored in a non-secure flash because some ARM reference 214 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT 215 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. 216 */ 217 #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ 218 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 219 220 /*Secure Watchdog Constants */ 221 #define SBSA_SECURE_WDOG_BASE UL(0x2A480000) 222 #define SBSA_SECURE_WDOG_TIMEOUT UL(100) 223 224 #define PLAT_ARM_SCMI_CHANNEL_COUNT 1 225 226 #define PLAT_ARM_CLUSTER_COUNT U(1) 227 #define PLAT_MAX_CPUS_PER_CLUSTER U(8) 228 #define PLAT_MAX_PE_PER_CPU U(1) 229 230 /* Message Handling Unit (MHU) base addresses */ 231 #define PLAT_CSS_MHU_BASE UL(0x45400000) 232 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE 233 234 /* TC2: AP<->RSS MHUs */ 235 #define PLAT_RSS_AP_SND_MHU_BASE UL(0x2A840000) 236 #define PLAT_RSS_AP_RCV_MHU_BASE UL(0x2A850000) 237 238 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 239 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 240 241 /* 242 * Physical and virtual address space limits for MMU in AARCH64 243 */ 244 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 245 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 246 247 /* GIC related constants */ 248 #define PLAT_ARM_GICD_BASE UL(0x30000000) 249 #define PLAT_ARM_GICC_BASE UL(0x2C000000) 250 #define PLAT_ARM_GICR_BASE UL(0x30080000) 251 252 /* 253 * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current 254 * SCP_BL2 size plus a little space for growth. 255 */ 256 #define PLAT_CSS_MAX_SCP_BL2_SIZE 0x20000 257 258 /* 259 * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current 260 * SCP_BL2U size plus a little space for growth. 261 */ 262 #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x20000 263 264 /* TZC Related Constants */ 265 #define PLAT_ARM_TZC_BASE UL(0x25000000) 266 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 267 268 #define TZC400_OFFSET UL(0x1000000) 269 #define TZC400_COUNT 4 270 271 #define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \ 272 (n * TZC400_OFFSET)) 273 274 #define TZC_NSAID_DEFAULT U(0) 275 276 #define PLAT_ARM_TZC_NS_DEV_ACCESS \ 277 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT)) 278 279 /* 280 * The first region below, TC_TZC_DRAM1_BASE (0xfd000000) to 281 * ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 48 MB of DRAM as 282 * secure. The second and third regions gives non secure access to rest of DRAM. 283 */ 284 #define TC_TZC_REGIONS_DEF \ 285 {TC_TZC_DRAM1_BASE, ARM_SCP_TZC_DRAM1_END, \ 286 TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 287 {TC_NS_DRAM1_BASE, TC_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 288 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 289 {PLAT_ARM_DRAM2_BASE, PLAT_ARM_DRAM2_END, \ 290 ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS} 291 292 /* virtual address used by dynamic mem_protect for chunk_base */ 293 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 294 295 #endif /* PLATFORM_DEF_H */ 296