fix(cpus): workaround for Cortex-A710 erratum 2768515

Cortex-A710 erratum 2768515 is a Cat B erratum that applies to
all revisions <=r2p1 and is still open. The workaround is to
insert a dsb before

fix(cpus): workaround for Cortex-A710 erratum 2768515

Cortex-A710 erratum 2768515 is a Cat B erratum that applies to
all revisions <=r2p1 and is still open. The workaround is to
insert a dsb before the isb in the power down sequence.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: If17fe04d3fda0dba6b8aabdd837a1c53e1830ed5

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fix(rmmd): add missing padding to RMM Boot Manifest and initialize it

This patch also:
* Enforces the check of RES0 fields on EL3-RMM boot interface
and manifest
* Fixes a couple of

fix(rmmd): add missing padding to RMM Boot Manifest and initialize it

This patch also:
* Enforces the check of RES0 fields on EL3-RMM boot interface
and manifest
* Fixes a couple of nits on the EL3-RMM Boot Interface
documentation.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Idb9e38f9fcda2ba0655646a1e2c4fdbabd5cdc40

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Merge "feat(rmm): add support for the 2nd DRAM bank" into integration

feat(rmm): add support for the 2nd DRAM bank

This patch adds support for RMM granules allocation
in FVP 2nd DRAM 2GB bank at 0x880000000 base address.
For ENABLE_RME = 1 case it also removes "mem=1G

feat(rmm): add support for the 2nd DRAM bank

This patch adds support for RMM granules allocation
in FVP 2nd DRAM 2GB bank at 0x880000000 base address.
For ENABLE_RME = 1 case it also removes "mem=1G"
Linux kernel command line option in fvp-base-psci-common.dsti
to allow memory layout discovery from the FVP device tree.
FVP parameter 'bp.dram_size' - size of main memory in gigabytes
documented in docs/components/realm-management-extension.rst
is changed from 2 to 4.

Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I174da4416ad5a8d41bf0ac89f356dba7c0cd3fe7

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docs(porting-guide): update a reference

The BL31 part has been there forever and the PSCI reference is neither
at section 3.3 or directly below. Update this to locate the section more
easily.

Signe

docs(porting-guide): update a reference

The BL31 part has been there forever and the PSCI reference is neither
at section 3.3 or directly below. Update this to locate the section more
easily.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I9a86e4ef13d1ac5da743917493f63ddd7690e087

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docs: extend generic tf-a threat model

Adding a new threat which is about leaving
sensitive information in internal buffers
which could be stolen by an attacker.

Signed-off-by: Tamas Ban <tamas.ban

docs: extend generic tf-a threat model

Adding a new threat which is about leaving
sensitive information in internal buffers
which could be stolen by an attacker.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I737e802c0adc9b00c89a0e21779745c51afb4b17

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Merge "build: restrict usage of CTX_INCLUDE_EL2_REGS" into integration

build: restrict usage of CTX_INCLUDE_EL2_REGS

CTX_INCLUDE_EL2_REGS is used to save/restore EL2 registers and
it should be only used when there is SPMD or RME enabled.

Make CTX_INCLUDE_EL2_REGS an i

build: restrict usage of CTX_INCLUDE_EL2_REGS

CTX_INCLUDE_EL2_REGS is used to save/restore EL2 registers and
it should be only used when there is SPMD or RME enabled.

Make CTX_INCLUDE_EL2_REGS an internal macro and remove
from documentation.

Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Change-Id: I6a70edfd88163423ff0482de094601cf794246d6

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Merge "fix(cpus): workaround for Cortex-X3 erratum 2615812" into integration

fix(docs): deprecate plat_convert_pk() in v2.9

The deprecation was tagged "Next release after 2.8". Now there is a 2.9
planned, directly use this version.

Signed-off-by: Yann Gautier <yann.gautier@

fix(docs): deprecate plat_convert_pk() in v2.9

The deprecation was tagged "Next release after 2.8". Now there is a 2.9
planned, directly use this version.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I0727eebc4a3800dafafc4166b0c2c40a12c90b4b

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Merge "docs(spm): update threat model" into integration

Merge "docs(qemu): document steps to run in OpenCI" into integration

docs(spm): update threat model

Update SPM threat model for possible threats, from malicious
endpoints, related to interrupt management. The mitigations
are based on the guidance provided in FF-A v1.

docs(spm): update threat model

Update SPM threat model for possible threats, from malicious
endpoints, related to interrupt management. The mitigations
are based on the guidance provided in FF-A v1.1 EAC0 spec.

Change-Id: Ib9e26e3f1c60fe3a2734a67de1dcf1cea4883d38
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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docs(qemu): document steps to run in OpenCI

Add details on how to run QEMU in OpenCI, and what tests are currently
supported.

Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Change-Id: I291e

docs(qemu): document steps to run in OpenCI

Add details on how to run QEMU in OpenCI, and what tests are currently
supported.

Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Change-Id: I291e4eb64a58c766519ff7dcac4841ae75c3934e

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Merge "docs(changelog): changelog for v2.8 release" into integration

fix(docs): add v2.9 release schedule

Signed-off-by: Joanna Farley <Joanna.Farley@arm.com>
Change-Id: I082461d7d21f63e3b8cbee37e8f01b8128e4b5a0

Merge changes I97687f18,I91d5718b into integration

* changes:
docs(spm): interrupt handling guidance FF-A v1.1 EAC0
docs(spm): partition runtime model and schedule modes

fix(cpus): workaround for Cortex-X3 erratum 2615812

Cortex-X3 erratum 2615812 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1, and is still open. The workaround is to disable
the u

fix(cpus): workaround for Cortex-X3 erratum 2615812

Cortex-X3 erratum 2615812 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1, and is still open. The workaround is to disable
the use of the Full Retention power mode in the core (setting
WFI_RET_CTRL and WFE_RET_CTRL in CORTEX_X3_IMP_CPUPWRCTLR_EL1 to 0b000).

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2055130/latest

Change-Id: I5ad66df3e18fc85a6b23f6662239494ee001d82f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes from topic "ja/spm_doc" into integration

* changes:
docs(spm): ff-a v1.1 indirect message
docs(spm): s-el0 partition support update

docs(spm): interrupt handling guidance FF-A v1.1 EAC0

This patch documents the actions taken by Hafnium SPMC in response
to non-secure and secure interrupts.

Change-Id: I97687f188ca97aeb255e3e5b55d

docs(spm): interrupt handling guidance FF-A v1.1 EAC0

This patch documents the actions taken by Hafnium SPMC in response
to non-secure and secure interrupts.

Change-Id: I97687f188ca97aeb255e3e5b55d44ddf5d66b6e0
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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docs(changelog): changelog for v2.8 release

Change-Id: I1d99ea46ad527993ee786c34a67f94d74470f960
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

docs(spm): partition runtime model and schedule modes

This patch documents the support for partition runtime models, call
chains and schedule modes in Hafnium SPMC.

Change-Id: I91d5718bb2c21d475499

docs(spm): partition runtime model and schedule modes

This patch documents the support for partition runtime models, call
chains and schedule modes in Hafnium SPMC.

Change-Id: I91d5718bb2c21d475499e402f6f27076930336cb
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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Merge "docs(marvell): fix typo 8K => A8K" into integration

docs(spm): ff-a v1.1 indirect message

Update secure partition manager documentation to include
FF-A v1.1 indirect messaging implementation.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: If

docs(spm): ff-a v1.1 indirect message

Update secure partition manager documentation to include
FF-A v1.1 indirect messaging implementation.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Ifbca45347f775080ef98ac896d31650204318ba4

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Merge changes If90a18ee,I02e88f8c,Iea447fb5,Ie0570481,Ieeb14cfc into integration

* changes:
docs: add top level section numbering
docs(build): clarify getting started section
docs(build): clar

Merge changes If90a18ee,I02e88f8c,Iea447fb5,Ie0570481,Ieeb14cfc into integration

* changes:
docs: add top level section numbering
docs(build): clarify getting started section
docs(build): clarify docs building instructions
fix(docs): prevent a sphinx warning
fix(docs): prevent a virtual environment from failing a build

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