| d7156d41 | 13-Jan-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
docs(security): security advisory for CVE-2022-47630
Reported-by: Demi Marie Obenour <demiobenour@gmail.com>
Co-authored-by: Demi Marie Obenour <demiobenour@gmail.com>
Signed-off-by: Sandrine Baille
docs(security): security advisory for CVE-2022-47630
Reported-by: Demi Marie Obenour <demiobenour@gmail.com>
Co-authored-by: Demi Marie Obenour <demiobenour@gmail.com>
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I20be2d280437eb223c988e2bf59c4562515817a0
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| 72020318 | 11-Jan-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(cpus): workaround for Cortex-X2 erratum 2282622" into integration |
| fb797974 | 11-Jan-2023 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "fix(cpus): workaround for Cortex-A710 erratum 2282622" into integration |
| f9c6301d | 22-Dec-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Cortex-X2 erratum 2282622
Cortex-X2 erratum 2282622 is a Cat B erratum that applies to
all revisions <=r2p1 and is still open. The workaround is to set
CPUACTLR2_EL1[0] to
fix(cpus): workaround for Cortex-X2 erratum 2282622
Cortex-X2 erratum 2282622 is a Cat B erratum that applies to
all revisions <=r2p1 and is still open. The workaround is to set
CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to behave like
PLD/PRFM LD and not cause invalidations to other PE caches.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1775100/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I43956aa4898a8608eedc5d0dd1471172c641a0c6
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| fa27d116 | 11-Jan-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
docs: change security advisories notification channel
Our documentation currently says that new security advisories will be
announced on the project's issue tracker. However, this issue tracker
is b
docs: change security advisories notification channel
Our documentation currently says that new security advisories will be
announced on the project's issue tracker. However, this issue tracker
is barely used by TF-A community and the software it is based on is
getting deprecated. Thus from now on, security advisories will rather
be announced on the project's mailing list.
Update TF-A documentation to reflect that.
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: If2f635795e0af4c794015a025899bfcc7116ab38
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| 601e2d43 | 10-Jan-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "bk/warnings" into integration
* changes:
docs: describe the new warning levels
build: add -Wunused-const-variable=2 to W=2
build: include -Wextra in generic builds
Merge changes from topic "bk/warnings" into integration
* changes:
docs: describe the new warning levels
build: add -Wunused-const-variable=2 to W=2
build: include -Wextra in generic builds
docs(porting-guide): update a reference
fix(st-usb): replace redundant checks with asserts
fix(brcm): add braces around bodies of conditionals
fix(renesas): align incompatible function pointers
fix(zynqmp): remove redundant api_version check
fix: remove old-style declarations
fix: unify fallthrough annotations
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| 89d85ad0 | 22-Dec-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Cortex-A710 erratum 2282622
Cortex-A710 erratum 2282622 is a Cat B erratum that applies to
all revisions <=r2p1 and is still open. The workaround was earlier
applied to all
fix(cpus): workaround for Cortex-A710 erratum 2282622
Cortex-A710 erratum 2282622 is a Cat B erratum that applies to
all revisions <=r2p1 and is still open. The workaround was earlier
applied to all revisions <= r2p0, this patch extends it to r2p1.
This was thought to have been fixed in r2p1 which is not the case.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Iad38a7fe57bec3f2d8977995acd601dcd9ae69c0
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| c9c752e9 | 09-Jan-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "docs(maintainers): update maintainers for total compute" into integration |
| 08f439f4 | 05-Jan-2023 |
Rupinderjit Singh <rupinderjit.singh@arm.com> |
docs(maintainers): update maintainers for total compute
Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
Change-Id: I64e7b036f404da110339d9013aa5c17ed8bf100f |
| 0c6a0854 | 04-Jan-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "fvp_trap_rng" into integration
* changes:
feat(fvp): emulate trapped RNDR
feat(el3-runtime): introduce system register trap handler |
| 1ee7c823 | 07-Dec-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Neoverse N2 erratum 2743089
Neoverse N2 erratum 2743089 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
insert a dsb befo
fix(cpus): workaround for Neoverse N2 erratum 2743089
Neoverse N2 erratum 2743089 is a Cat B erratum that applies to
all revisions <=r0p2 and is fixed in r0p3. The workaround is to
insert a dsb before the isb in the power down sequence.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Idec862226bd32c91374a8bbd5d73d7ee480a34d9
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| 1ae75529 | 21-Nov-2022 |
Andre Przywara <andre.przywara@arm.com> |
feat(fvp): emulate trapped RNDR
When a platform decides to use FEAT_RNG_TRAP, every RNDR or RNDRSS read
will trap into EL3. The platform can then emulate those instructions, by
either executing the
feat(fvp): emulate trapped RNDR
When a platform decides to use FEAT_RNG_TRAP, every RNDR or RNDRSS read
will trap into EL3. The platform can then emulate those instructions, by
either executing the real CPU instructions, potentially conditioning the
results, or use rate-limiting or filtering to protect the hardware
entropy pool. Another possiblitiy would be to use some platform specific
TRNG device to get entropy and returning this.
To demonstrate platform specific usage, add a demo implementation for the
FVP: It will execute the actual CPU instruction and just return the
result. This should serve as reference code to implement platform specific
policies.
We change the definition of read_rndr() and read_rndrrs() to use the
alternative sysreg encoding, so that all assemblers can handle that.
Add documentation about the new platform specific RNG handler function.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ibce817b3b06ad20129d15531b81402e3cc3e9a9e
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| b10afcce | 15-Dec-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Cortex-A78 erratum 2772019
Cortex-A78 erratum 2772019 is a Cat B erratum that applies to
all revisions <=r1p2 and is still open. The workaround is to
insert a dsb before th
fix(cpus): workaround for Cortex-A78 erratum 2772019
Cortex-A78 erratum 2772019 is a Cat B erratum that applies to
all revisions <=r1p2 and is still open. The workaround is to
insert a dsb before the isb in the power down sequence.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1401784/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I0362da463eca777aa7a385bcdeb39b8549799f02
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|
| 31747f05 | 15-Dec-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Neoverse V1 erratum 2743093
Neoverse V1 erratum 2743093 is a Cat B erratum that applies to
all revisions <=r1p2 and is still open. The workaround is to
insert a dsb before
fix(cpus): workaround for Neoverse V1 erratum 2743093
Neoverse V1 erratum 2743093 is a Cat B erratum that applies to
all revisions <=r1p2 and is still open. The workaround is to
insert a dsb before the isb in the power down sequence.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1401781/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I8ee7c16c14c4fd6ee35d20c855273ecfce0d1b32
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| 21fdbf9b | 22-Nov-2022 |
Yann Gautier <yann.gautier@st.com> |
docs: deprecate io_dummy driver
This drivers was only used by one upstream platform: STM32MP1 but only
when enabling the flag STM32MP_USE_STM32IMAGE. This flag and the
corresponding code is now remo
docs: deprecate io_dummy driver
This drivers was only used by one upstream platform: STM32MP1 but only
when enabling the flag STM32MP_USE_STM32IMAGE. This flag and the
corresponding code is now removed from TF-A. The driver can then be
set to deprecated. It will be removed after v2.9 tag.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ib8242a7291c7011d7f96a6a83609ec1996dce520
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| 6d4f4c3e | 15-Dec-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "qemu_sel2" into integration
* changes:
docs(build): describes the SPMC_OPTEE build option
feat(qemu): support el3 spmc
feat(el3-spmc): make platform logical partition
Merge changes from topic "qemu_sel2" into integration
* changes:
docs(build): describes the SPMC_OPTEE build option
feat(qemu): support el3 spmc
feat(el3-spmc): make platform logical partition optional
feat(qemu): support s-el2 spmc
feat(qemu): update abi between spmd and spmc
fix(sptool): add dependency to SP image
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| 19e09e27 | 14-Dec-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes Ib02688f7,If17fe04d into integration
* changes:
fix(cpus): workaround for Cortex-X2 erratum 2768515
fix(cpus): workaround for Cortex-A710 erratum 2768515 |
| bb0e3360 | 14-Dec-2022 |
Jens Wiklander <jens.wiklander@linaro.org> |
docs(build): describes the SPMC_OPTEE build option
Explains that the SPMC_OPTEE build option is used to load the SPMC at
S-EL1 using an OP-TEE specific mechanism.
Signed-off-by: Jens Wiklander <jen
docs(build): describes the SPMC_OPTEE build option
Explains that the SPMC_OPTEE build option is used to load the SPMC at
S-EL1 using an OP-TEE specific mechanism.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Change-Id: I71757d2d9ac98caf0ac6d8e64b221adaa0f70846
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| abd6d7ea | 12-Dec-2022 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes from topic "full_dev_rsa_key" into integration
* changes:
docs(arm): add ARM_ROTPK_LOCATION variant full key
feat(arm): add ARM_ROTPK_LOCATION variant full key |
| 291be198 | 07-Dec-2022 |
Boyan Karatotev <boyan.karatotev@arm.com> |
docs: describe the new warning levels
When -Wextra was added, the warning levels changed their meaning. Add a
description in the build option section and leave the security hardening
section as most
docs: describe the new warning levels
When -Wextra was added, the warning levels changed their meaning. Add a
description in the build option section and leave the security hardening
section as mostly a pointer to it.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Iabf2f598d0bf3e865c9b991c5d44d2acb9572bd5
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| 9b1dad8b | 01-Dec-2022 |
laurenw-arm <lauren.wehrmeister@arm.com> |
docs(arm): add ARM_ROTPK_LOCATION variant full key
Updating documentation to reflect the new ARM_ROTPK_LOCATION variant of
the full ROTPK, as opposed to the hash of it.
Change-Id: I0f83c519bd607ef1
docs(arm): add ARM_ROTPK_LOCATION variant full key
Updating documentation to reflect the new ARM_ROTPK_LOCATION variant of
the full ROTPK, as opposed to the hash of it.
Change-Id: I0f83c519bd607ef1270c7d30ee9bc55451ce4ae2
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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| c201d6e8 | 30-Nov-2022 |
Tamas Ban <tamas.ban@arm.com> |
docs: add threat model for AP-RSS interface
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Ic818da12584503e1a96396c4b55a8db14ae7584a |
| a0f256b0 | 08-Dec-2022 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "fix(rmmd): add missing padding to RMM Boot Manifest and initialize it" into integration |
| cb875fd3 | 08-Dec-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "docs: extend generic tf-a threat model" into integration |
| 1cfde822 | 07-Dec-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(cpus): workaround for Cortex-X2 erratum 2768515
Cortex-X2 erratum 2768515 is a Cat B erratum that applies to
all revisions <=r2p1 and is still open. The workaround is to
insert a dsb before the
fix(cpus): workaround for Cortex-X2 erratum 2768515
Cortex-X2 erratum 2768515 is a Cat B erratum that applies to
all revisions <=r2p1 and is still open. The workaround is to
insert a dsb before the isb in the power down sequence.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1775100/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ib02688f7b6dc7f6ec305e68e8895174f6fd577a0
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