en Copyright 2025 Java http://opengrok.muzhidianzi.cn:8080/history/rk3399_ARM-atf/docs/plat/ti-k3low-am62lx.rst#6c0c3a74dda68e7ffc8bd6c156918ddbfea7e03a Merge changes from topic "am62l-bl1" into integration* changes: feat(k3low): add BL1 platform definitions and integration for AM62L feat(k3low): add AM62L DDR platform shim and EVM board config feat(k3low): introduce Cadence LPDDR4 core driver for AM62L List of files: /rk3399_ARM-atf/docs/plat/ti-k3low-am62lx.rst Mon, 06 Apr 2026 16:08:45 +0000 Govindraj Raja <govindraj.raja@arm.com> http://opengrok.muzhidianzi.cn:8080/history/rk3399_ARM-atf/docs/plat/ti-k3low-am62lx.rst#5421f84b7e553c16894d7732a6ed531bb661e721 feat(k3low): introduce Cadence LPDDR4 core driver for AM62LAM62L devices support 16-bit DDR4/LPDDR4 DRAM memory devices. The coreDDR4/LPDDR4 driver was developed by Cadence. This patch introduces theCadence IP driver files (lpddr4.c, lpddr4_16bit.c, lpddr4_obj_if.c andtheir associated headers) which carry dual copyright (Cadence + TI).The driver was pruned from ~6800 macros to ~80 with AI-assisted removalof unused code; the Cadence CTL/PHY/PI API surface remains intact forreview against the User Guides.These files are intentionally unreferenced in platform.mk pending theAM62L platform shim in the next patch.For additional information please check the technical referencemanual at:https://www.ti.com/lit/pdf/sprujb4Change-Id: I8b02a6b30e5ea7b1b457cc0a933d8ef232993fa1Co-developed-by: Claude <noreply@anthropic.com>Signed-off-by: Hari Nagalla <hnagalla@ti.com> List of files: /rk3399_ARM-atf/docs/plat/ti-k3low-am62lx.rst Wed, 25 Mar 2026 02:39:14 +0000 Hari Nagalla <hnagalla@ti.com>