| #
c1701c8e |
| 07-Nov-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "ns/spmc_at_el3" into integration
* changes:
feat(sgi): increase sp memmap size
feat(build): include plat header in fdt build
feat(docs): save BL32 image base and size
Merge changes from topic "ns/spmc_at_el3" into integration
* changes:
feat(sgi): increase sp memmap size
feat(build): include plat header in fdt build
feat(docs): save BL32 image base and size in entry point info
feat(arm): save BL32 image base and size in entry point info
show more ...
|
| #
31dcf234 |
| 13-Oct-2023 |
Nishant Sharma <nishant.sharma@arm.com> |
feat(docs): save BL32 image base and size in entry point info
There is no platform function to retrieve the info in the generic code.
Populate the BL32 image base, size and max limit in arg2, arg3 a
feat(docs): save BL32 image base and size in entry point info
There is no platform function to retrieve the info in the generic code.
Populate the BL32 image base, size and max limit in arg2, arg3 and arg4.
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I35527fb41829102083b488a5150c0c707c5ede15
show more ...
|
| #
6f802c44 |
| 02-Nov-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "mp/exceptions" into integration
* changes:
docs(ras): update RAS documentation
docs(el3-runtime): update BL31 exception vector handling
fix(el3-runtime): restrict low
Merge changes from topic "mp/exceptions" into integration
* changes:
docs(ras): update RAS documentation
docs(el3-runtime): update BL31 exception vector handling
fix(el3-runtime): restrict lower el EA handlers in FFH mode
fix(ras): remove RAS_FFH_SUPPORT and introduce FFH_SUPPORT
fix(ras): restrict ENABLE_FEAT_RAS to have only two states
feat(ras): use FEAT_IESB for error synchronization
feat(el3-runtime): modify vector entry paths
show more ...
|
| #
9f9bfd7a |
| 21-Jul-2023 |
Manish Pandey <manish.pandey2@arm.com> |
docs(el3-runtime): update BL31 exception vector handling
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ieae66bafe1cdd253edebecddea156551144a1cc9
|
| #
43a6544f |
| 25-Jul-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "chore(docs): update march utility details" into integration
|
| #
019311e7 |
| 18-Jul-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
chore(docs): update march utility details
commit@7794d6c8f8c44acc14fbdc5ada5965310056be1e added a march utility
but the details were not updated in docs.
Update docs to provide a glimpse of march u
chore(docs): update march utility details
commit@7794d6c8f8c44acc14fbdc5ada5965310056be1e added a march utility
but the details were not updated in docs.
Update docs to provide a glimpse of march utility added.
Change-Id: I696cb9a701a30d7bf36a1ecd38a80d07df1fd551
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
show more ...
|
| #
3995f30c |
| 27-Jun-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "refactor(build): merge march32/64 directives" into integration
|
| #
d4089fb8 |
| 30-May-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
refactor(build): merge march32/64 directives
Both march32-directive and march64-directive eventually generate the
same march option that will passed to compiler.
Merge this two separate directives
refactor(build): merge march32/64 directives
Both march32-directive and march64-directive eventually generate the
same march option that will passed to compiler.
Merge this two separate directives to a common one as march-directive.
Change-Id: I220d2b782eb3b54e13ffd5b6a581d0e6da68756a
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
show more ...
|
| #
bf1e58e7 |
| 16-Jun-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "docs: update PSCI reference" into integration
|
| #
d2e07436 |
| 15-Jun-2023 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes from topic "bk/errata_refactor" into integration
* changes:
feat(cpus): add more errata framework helpers
docs: document the errata framework
|
| #
6a0e8e80 |
| 07-Feb-2023 |
Boyan Karatotev <boyan.karatotev@arm.com> |
docs: document the errata framework
Also add a recommended Procedure Call Standard (PCS) to use inside CPU
files and split everything into sections to make it easier to follow.
Signed-off-by: Boyan
docs: document the errata framework
Also add a recommended Procedure Call Standard (PCS) to use inside CPU
files and split everything into sections to make it easier to follow.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Idd876d8e598b5dfe1193aa3e7375c52f6edf5671
show more ...
|
| #
3be6b4fb |
| 15-Jun-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs: update PSCI reference
PSCI specification reference in the documentation is updated
to point to latest specification and duplicate PSCI references are
removed.
Change-Id: I35ee365f08c557f3017a
docs: update PSCI reference
PSCI specification reference in the documentation is updated
to point to latest specification and duplicate PSCI references are
removed.
Change-Id: I35ee365f08c557f3017af4d51f6d063a7501b27e
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
show more ...
|
| #
7ae96dce |
| 12-Jun-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "chore(bl): add UNALIGNED symbols for TEXT/RODATA" into integration
|
| #
f7d445fc |
| 27-Apr-2023 |
Michal Simek <michal.simek@amd.com> |
chore(bl): add UNALIGNED symbols for TEXT/RODATA
Add symbols to mark end of TEXT/RODATA before page alignment.
Similar change was done by commit 8d69a03f6a7d ("Various
improvements/cleanups on the l
chore(bl): add UNALIGNED symbols for TEXT/RODATA
Add symbols to mark end of TEXT/RODATA before page alignment.
Similar change was done by commit 8d69a03f6a7d ("Various
improvements/cleanups on the linker scripts") for
RO_END/COHERENT_RAM. These symbols help to know how much free
space is in the final binary because of page alignment.
Also show all *UNALIGNED__ symbols via poetry.
For example:
poetry run memory -p zynqmp -b debug
Change-Id: I322beba37dad76be9f4e88ca7e5b3eff2df7d96e
Signed-off-by: Michal Simek <michal.simek@amd.com>
show more ...
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| #
ab23061e |
| 07-Jun-2023 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "bk/clearups" into integration
* changes:
chore(rme): add make rule for SPD=spmd
chore(bl1): remove redundant bl1_arch_next_el_setup
chore(docs): remove control regist
Merge changes from topic "bk/clearups" into integration
* changes:
chore(rme): add make rule for SPD=spmd
chore(bl1): remove redundant bl1_arch_next_el_setup
chore(docs): remove control register setup section
chore(pauth): remove redundant pauth_disable_el3() call
show more ...
|
| #
3f52d599 |
| 30-May-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "docs: fix syntax error in note" into integration
|
| #
be3a4563 |
| 22-May-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "docs: update usage of ARM_ARCH_MAJOR/MINOR" into integration
|
| #
be6484cb |
| 12-May-2023 |
Manish Pandey <manish.pandey2@arm.com> |
docs: update usage of ARM_ARCH_MAJOR/MINOR
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I433488ecbaf7773a9e062223599fb0d3bc892f94
|
| #
24566a3f |
| 12-May-2023 |
Harrison Mutai <harrison.mutai@arm.com> |
docs: fix syntax error in note
Change-Id: Ibd4599c761641431e02778bd65c2696fb886a326
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
|
| #
315f4f8a |
| 09-May-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "docs: update TZC secured DRAM map for FVP and Juno" into integration
|
| #
a52c5251 |
| 07-Mar-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs: update TZC secured DRAM map for FVP and Juno
Updated the documentation to include missing details about the
TZC secured DRAM mapping for the FVP and Juno platforms.
Change-Id: I10e59b9f9686fa
docs: update TZC secured DRAM map for FVP and Juno
Updated the documentation to include missing details about the
TZC secured DRAM mapping for the FVP and Juno platforms.
Change-Id: I10e59b9f9686fa2fef97f89864ebc272b10e5c0b
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
show more ...
|
| #
6c42a736 |
| 14-Mar-2023 |
Boyan Karatotev <boyan.karatotev@arm.com> |
chore(docs): remove control register setup section
It hasn't been updated since 2017 and the documentation around that bit
of code is fairly good so it is redundant to be there.
Signed-off-by: Boya
chore(docs): remove control register setup section
It hasn't been updated since 2017 and the documentation around that bit
of code is fairly good so it is redundant to be there.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Idee4523e97cb6039fae1efae35eda2b45e8f7345
show more ...
|
| #
a4c69581 |
| 15-Mar-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3" into integration
|
| #
42d4d3ba |
| 22-Nov-2022 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3
BL2_AT_EL3 is an overloaded macro which has two uses:
1. When BL2 is entry point into TF-A(no BL1)
2. When BL2 is runnin
refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3
BL2_AT_EL3 is an overloaded macro which has two uses:
1. When BL2 is entry point into TF-A(no BL1)
2. When BL2 is running at EL3 exception level
These two scenarios are not exactly same even though first implicitly
means second to be true. To distinguish between these two use cases we
introduce new macros.
BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2.
Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where
BL2 runs at EL3 (including four world systems).
BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the
repository.
Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
show more ...
|
| #
338dbe2f |
| 22-Feb-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I51c13c52,I3358c51e into integration
* changes:
build: always prefix section names with `.`
build: communicate correct page size to linker
|