| b3ff48ba | 08-Dec-2025 |
Yann Gautier <yann.gautier@st.com> |
docs(maintainers): add Gabriel as clock framework maintainer
Gabriel created this clock framework, first for ST platforms, but it can
be used by others. Adding him as maintainer.
Change-Id: I7af885
docs(maintainers): add Gabriel as clock framework maintainer
Gabriel created this clock framework, first for ST platforms, but it can
be used by others. Adding him as maintainer.
Change-Id: I7af8857def86b8042b9ddd3709f4888df51f6544
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| f396aec8 | 09-Sep-2025 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
feat(cpufeat): add support for FEAT_IDTE3
This patch adds support for FEAT_IDTE3, which introduces support
for handling the trapping of Group 3 and Group 5 (only GMID_EL1)
registers to EL3 (unless t
feat(cpufeat): add support for FEAT_IDTE3
This patch adds support for FEAT_IDTE3, which introduces support
for handling the trapping of Group 3 and Group 5 (only GMID_EL1)
registers to EL3 (unless trapped to EL2). IDTE3 allows EL3 to
modify the view of ID registers for lower ELs, and this capability
is used to disable fields of ID registers tied to disabled features.
The ID registers are initially read as-is and stored in context.
Then, based on the feature enablement status for each world, if a
particular feature is disabled, its corresponding field in the
cached ID register is set to Res0. When lower ELs attempt to read
an ID register, the cached ID register value is returned. This
allows EL3 to prevent lower ELs from accessing feature-specific
system registers that are disabled in EL3, even though the hardware
implements them.
The emulated ID register values are stored primarily in per-world
context, except for certain debug-related ID registers such as
ID_AA64DFR0_EL1 and ID_AA64DFR1_EL1, which are stored in the
cpu_data and are unique to each PE. This is done to support feature
asymmetry that is commonly seen in debug features.
FEAT_IDTE3 traps all Group 3 ID registers in the range
op0 == 3, op1 == 0, CRn == 0, CRm == {2–7}, op2 == {0–7} and the
Group 5 GMID_EL1 register. However, only a handful of ID registers
contain fields used to detect features enabled in EL3. Hence, we
only cache those ID registers, while the rest are transparently
returned as is to the lower EL.
This patch updates the CREATE_FEATURE_FUNCS macro to generate
update_feat_xyz_idreg_field() functions that disable ID register
fields on a per-feature basis. The enabled_worlds scope is used to
disable ID register fields for security states where the feature is
not enabled.
This EXPERIMENTAL feature is controlled by the ENABLE_FEAT_IDTE3
build flag and is currently disabled by default.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I5f998eeab81bb48c7595addc5595313a9ebb96d5
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| 1988ea81 | 22-Oct-2025 |
Olivier Deprez <olivier.deprez@arm.com> |
docs: deprecate SPM_MM build option
Following the ML post [1] deprecating the SPM-MM build option.
[1] https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.org/thread/Z6GAD7OG
docs: deprecate SPM_MM build option
Following the ML post [1] deprecating the SPM-MM build option.
[1] https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.org/thread/Z6GAD7OGKNDPNKECJ63HQZ4XEYUJXTNM/
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ie845335989a6b11382ebe2f32962f534ad1bf8c6
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