dts: stm32: disable ADC2 on stm32mp135f-dk

Remove ADC2 configuration in stm32mp135-dk.dts since OP-TEE does not
use the device.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Revi

dts: stm32: disable ADC2 on stm32mp135f-dk

Remove ADC2 configuration in stm32mp135-dk.dts since OP-TEE does not
use the device.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: default disable DMA at SoC level for stm32mp15 platforms

DMA node in stm32mp15* SoC DTSI files shouldn't be enabled by default,
we don't even have a driver to handle it. Therefore defaul

dts: stm32: default disable DMA at SoC level for stm32mp15 platforms

DMA node in stm32mp15* SoC DTSI files shouldn't be enabled by default,
we don't even have a driver to handle it. Therefore default disable it.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core: fix race in mobj_reg_shm_get_by_cookie()

Until this patch in mobj_reg_shm_get_by_cookie() there's a small window
after cpu_spin_unlock_xrestore() before the reference counter is
increased with

core: fix race in mobj_reg_shm_get_by_cookie()

Until this patch in mobj_reg_shm_get_by_cookie() there's a small window
after cpu_spin_unlock_xrestore() before the reference counter is
increased with mobj_get(). Fix that by calling mobj_get() before
unlocking reg_shm_slist_lock.

Fixes: b96514926b8e ("core: reference count struct mobj")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: caam: skip JR init of CFG_JR_HAB_INDEX

On iMX8M SoC, the HAB requires the JR0 to be set to secure world to
decrypt the kernel image when loading the image in U-Boot.

Before reaching u-boot

drivers: caam: skip JR init of CFG_JR_HAB_INDEX

On iMX8M SoC, the HAB requires the JR0 to be set to secure world to
decrypt the kernel image when loading the image in U-Boot.

Before reaching u-boot, OP-TEE and TF-A set the JR0 to the non-secure
domain that leads to a HAB failure when trying to decrypt the kernel.

To fix the issue, this commit introduces CFG_JR_HAB_INDEX that specifies
which JR the HAB uses. OPTEE will skip the initialization of
CFG_JR_HAB_INDEX and leave it as secure.

It will also disable its usage in the device tree to inform the kernel.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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mk/subdir.mk: introduce srcs_ext-y and srcs_ext_base-y

Introduce two new variables srcs_ext-y and srcs_ext_base-y to deal with
compiling source code outside of this git (optee_os.git).

srcs_ext_bas

mk/subdir.mk: introduce srcs_ext-y and srcs_ext_base-y

Introduce two new variables srcs_ext-y and srcs_ext_base-y to deal with
compiling source code outside of this git (optee_os.git).

srcs_ext_base-y assigns the root directory of the external source files
to compile. srcs_ext-y works as srcs-y except that it's relative to the
$(srcs_ext_base-y) directory.

Introduce the per source file variable oname-<file name>-y to override
the default output object file name. This helps to shorten and make a
more sane name for the output object file name when the source file is
outside optee_os source tree, for instance, a third-party library.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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mk: introduce global-incdirs_ext-y

Introduce the global-incdirs_ext-y variable to deal with including
header files from outside of this git (optee_os.git).

Signed-off-by: Jens Wiklander <jens.wikla

mk: introduce global-incdirs_ext-y

Introduce the global-incdirs_ext-y variable to deal with including
header files from outside of this git (optee_os.git).

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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ta_dev_kit.mk: use spec-srcs and spec-out-dir

The commit cfa34d9afb5c ("Add support for compiling in-tree TAs") added
spec-srcs and spec-out-dir for special handling of user_ta_header.c when
compili

ta_dev_kit.mk: use spec-srcs and spec-out-dir

The commit cfa34d9afb5c ("Add support for compiling in-tree TAs") added
spec-srcs and spec-out-dir for special handling of user_ta_header.c when
compiling in-tree TAs.

However, these variables are just as relevant for out-of-tree TAs
compiled via ta/mk/ta_dev_kit.mk. So as a simplification switch to use
spec-srcs and spec-out-dir in that file too.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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mk/subdir.mk: refactor process-subdir-{srcs-y,gensrcs-helper}

Moves the common parts of the two make macros process-subdir-srcs-y and
process-subdir-gensrcs-helper into a new macro, process-file-var

mk/subdir.mk: refactor process-subdir-{srcs-y,gensrcs-helper}

Moves the common parts of the two make macros process-subdir-srcs-y and
process-subdir-gensrcs-helper into a new macro, process-file-vars.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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libmbedtls: mbedtls_config_uta.h: enable SHA-384 and SHA-512 support

Enable SHA-384 and SHA-512 support for user TAs.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne

libmbedtls: mbedtls_config_uta.h: enable SHA-384 and SHA-512 support

Enable SHA-384 and SHA-512 support for user TAs.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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tee_api_types.h: default alignment for TEE_BigIntFMMContext

Remove the custom alignment from TEE_BigIntFMMContext.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Car

tee_api_types.h: default alignment for TEE_BigIntFMMContext

Remove the custom alignment from TEE_BigIntFMMContext.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: force CFG_DRIVERS_FIREWALL when supporting RIF controllers

When firewall controllers drivers that implements firewall framework
support are embedded such as RISAB or RIFSC, then CFG_D

plat-stm32mp2: force CFG_DRIVERS_FIREWALL when supporting RIF controllers

When firewall controllers drivers that implements firewall framework
support are embedded such as RISAB or RIFSC, then CFG_DRIVERS_FIREWALL
should be forced enabled.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: move firewall dt-bindings include at SoC level

Firewall controllers are present on every variant of stm32mp25 SoCs.
Therefore, move the inclusion of their dt-bindings at SoC level.

Sign

dts: stm32: move firewall dt-bindings include at SoC level

Firewall controllers are present on every variant of stm32mp25 SoCs.
Therefore, move the inclusion of their dt-bindings at SoC level.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add RISAB configurations for the stm32mp257f-ev1 platform

Add the internal memory layout and RIF configuration for the
stm32mp257f-ev1 platform.

Signed-off-by: Gatien Chevallier <gatien

dts: stm32: add RISAB configurations for the stm32mp257f-ev1 platform

Add the internal memory layout and RIF configuration for the
stm32mp257f-ev1 platform.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add RISAB nodes in the stm32mp251 SoC DT file

Add the RISAB1/2/3/4/5/6 and default enable all of them except for the
RISAB6 that protects the VDERAM.

Signed-off-by: Gatien Chevallier <g

dts: stm32: add RISAB nodes in the stm32mp251 SoC DT file

Add the RISAB1/2/3/4/5/6 and default enable all of them except for the
RISAB6 that protects the VDERAM.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: default enable RISAB on stm32mp2 platforms

Default enable RISAB driver for platform stm32mp2.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Ca

plat-stm32mp2: default enable RISAB on stm32mp2 platforms

Default enable RISAB driver for platform stm32mp2.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_risab: add RISAB internal memory firewall driver

This driver implements the RISAB driver. Through RISAB registers, a
trusted compartment, or the compartment to which the page configur

drivers: stm32_risab: add RISAB internal memory firewall driver

This driver implements the RISAB driver. Through RISAB registers, a
trusted compartment, or the compartment to which the page configuration
has been delegated, configures the firewall attributes necessary to
access a page.

Each RISAB is dedicated to a internal memory and can cover 128KBytes of
data, separated in 32 pages of 4 KBytes, containing 8 blocks each.

It is possible to align a RISAB secure and privilege regions
allocations with an ARM Cortex M, which defines in its address space
configurable regions with a 256Bytes granularity. The configuration
would be 512Bytes block-based in order to align the two.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dt-bindings: add stm32mp25 RISAB bindings

Add stm32mp25 specific RISAB device tree bindings. This file contains
device tree contains helpers and RISABPROT macro that is used to
define the RIF config

dt-bindings: add stm32mp25 RISAB bindings

Add stm32mp25 specific RISAB device tree bindings. This file contains
device tree contains helpers and RISABPROT macro that is used to
define the RIF configuration for a RISAB region.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

show more ...

plat-stm32mp2: add RISAB1/2 base addresses in platform configuration

Add RISAB1/2 base addresses in platform configuration.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed

plat-stm32mp2: add RISAB1/2 base addresses in platform configuration

Add RISAB1/2 base addresses in platform configuration.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: add VDERAM SYSCFG support

Adds support for the VDERAM configuration that is present in SYSCFG.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne C

plat-stm32mp2: add VDERAM SYSCFG support

Adds support for the VDERAM configuration that is present in SYSCFG.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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mk: add global-cppflags-y

Add global-cppflags-y as a new sub.mk variable. The content of the
variable is added to the C preprocessor flags passed to all files
compiled in the current submodule, $(sm

mk: add global-cppflags-y

Add global-cppflags-y as a new sub.mk variable. The content of the
variable is added to the C preprocessor flags passed to all files
compiled in the current submodule, $(sm), similarly to how the content
of global-incdirs-y is passed on.

This flag is intended for libraries that in addition to exporting an
include path also need certain defines set.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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Update CHANGELOG for 4.4.0

Update CHANGELOG for 4.4.0 and collect Tested-by tags.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.

Update CHANGELOG for 4.4.0

Update CHANGELOG for 4.4.0 and collect Tested-by tags.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_armv8a)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (vexpress-qemu_virt)
Tested-by: Imre Kis <imre.kis@arm.com> (fvp-ts)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx6dlsabresd)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx6qsabresd)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx6sllevk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx6ulevk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx6ulzevk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx7dsabresd)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx7ulpevk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx8dxlevk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx8mmevk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx8mnevk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx8mqevk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx8mpevk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx8qmmek)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx8ulpevk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx93evk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx91evk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (imx-mx95evk)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1046A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LS1012A-RDB)
Tested-by: Sahil Malhotra <sahil.malhotra@nxp.com> (LX2160A-RDB)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (rockchip-rk3399) (Rockpi4B)
Tested-by: Joakim Bech <joakim.bech@linaro.org> (RPi 3B v1.2)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP)
Tested-by: Etienne Carriere <etienne.carriere@foss.st.com> (stm32mp1-157C_DK2_SCMI)
Tested-by: Etienne Carriere <etienne.carriere@foss.st.com> (stm32mp1-157C_EV1_SCMI)
Tested-by: Etienne Carriere <etienne.carriere@foss.st.com> (stm32mp1-157C_DK2)
Tested-by: Etienne Carriere <etienne.carriere@foss.st.com> (stm32mp1-157C_EV1)
Tested-by: Etienne Carriere <etienne.carriere@foss.st.com> (stm32mp1-157C_ED1)
Tested-by: Etienne Carriere <etienne.carriere@foss.st.com> (stm32mp1-135F_DK)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (rockchip-rk3399, Rockpi4B)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (imx-mx8mqevk)

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ldelf: fix crash when hash-style is sysv

This issue afects binaryes using the sysv style hash table
(-WL,hash-style=sysv)

When the "nbuckets" filed in the hash table (.hash) is set to 0, ldelf
will

ldelf: fix crash when hash-style is sysv

This issue afects binaryes using the sysv style hash table
(-WL,hash-style=sysv)

When the "nbuckets" filed in the hash table (.hash) is set to 0, ldelf
will do out-of-bounds indexing and crash with a data abort. Such a hash
table is strange but GCC 13.3.0 seems to produce them in some cases
anyway.

This fix returns an error is nbuckets is 0 before using the value, and
makes an affected S-EL0 SP binary load fine.

Signed-off-by: Gyorgy Szing <gyorgy.szing@arm.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: stm32_rng: MP15 RNG is non-secure when PRNG is enable

Register stm32_rng device as non-secure when software PRNG is enabled
instead of testing the firewall configuration that is applied fro

drivers: stm32_rng: MP15 RNG is non-secure when PRNG is enable

Register stm32_rng device as non-secure when software PRNG is enabled
instead of testing the firewall configuration that is applied from
stm32mp1_init_final_shres() at driver_init_late initcall level, far
after RNG initialization.

Fixes: d773ec0baf4c ("drivers: stm32_rng: update clock and power management")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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core: imx: disable ELE support on i.MX91 by default

On i.MX91, there is only one MU to communicate with ELE,
which cannot be dedicated on OP-TEE side all the time.
There may be ELE services running

core: imx: disable ELE support on i.MX91 by default

On i.MX91, there is only one MU to communicate with ELE,
which cannot be dedicated on OP-TEE side all the time.
There may be ELE services running on Linux side, which can
cause conflict with OP-TEE.
So disabling ELE by default for now.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: gic: accept GIC version 4 if CFG_ARM_GICV3 is enabled

GIC v4 is backwards compatible with GIC v3, Accept GIC
version 4 if CFG_ARM_GICV3 is enabled.

Signed-off-by: Ziad Elhanafy <ziad.elhanafy

core: gic: accept GIC version 4 if CFG_ARM_GICV3 is enabled

GIC v4 is backwards compatible with GIC v3, Accept GIC
version 4 if CFG_ARM_GICV3 is enabled.

Signed-off-by: Ziad Elhanafy <ziad.elhanafy@arm.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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