core: dynamically linked TAs: fix segment mapping

The way each library segment is assigned a virtual address is incorrect.
It results in interleaved segments. In other words, we may find in
ascendin

core: dynamically linked TAs: fix segment mapping

The way each library segment is assigned a virtual address is incorrect.
It results in interleaved segments. In other words, we may find in
ascending VA order: one segment belonging to library A, then one segment
from library B, then again one segment from library A.
In that context, the concept of a "library load address" is quite
meaningless, which will cause problems when running tools such as
addr2line.

Fix the issue by deriving the load address of a new ELF from the highest
VA in the previous ELF.

Fixes: c27907e1bc5a ("core: arm32: add support for dynamically linked TAs")
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: remove user_ta_elf::is_main

The 'is_main' boolean in struct user_ta_elf is used in a single
function: load_elf_from_store(). At this point we have another way of
determining if the ELF we're l

core: remove user_ta_elf::is_main

The 'is_main' boolean in struct user_ta_elf is used in a single
function: load_elf_from_store(). At this point we have another way of
determining if the ELF we're loading is the main executable or not.
Therefore, user_ta_elf::is_main is not really needed. Remove it.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

Remove license notice from STMicroelectronics files

Since a while the source files license info are defined by SPDX
identifiers. We can safely remove the verbose license text from the
files that are

Remove license notice from STMicroelectronics files

Since a while the source files license info are defined by SPDX
identifiers. We can safely remove the verbose license text from the
files that are owned by either only STMicroelectronics or only both
Linaro and STMicroelectronics.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

util: remove unused macros

After commit 9a8117de1263 ("util: update fallback ADD_OVERFLOW() macro")
and commit ecdedc94e720 ("util: update fallback SUB_OVERFLOW() macro"),
the following macros are n

util: remove unused macros

After commit 9a8117de1263 ("util: update fallback ADD_OVERFLOW() macro")
and commit ecdedc94e720 ("util: update fallback SUB_OVERFLOW() macro"),
the following macros are not used anymore. Remove them.

__INTOF_HALF_MAX_SIGNED(type)
__INTOF_MAX_SIGNED(type)
__INTOF_MIN_SIGNED(type)
__INTOF_MIN(type)
__INTOF_MAX(type)

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core_self_tests.c: add more SUB_OVERFLOW() tests

Adds more SUB_OVERFLOW() tests involving larger than 32-bit types and
mixed types.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed

core_self_tests.c: add more SUB_OVERFLOW() tests

Adds more SUB_OVERFLOW() tests involving larger than 32-bit types and
mixed types.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core_self_tests.c: add more ADD_OVERFLOW() tests

Adds more ADD_OVERFLOW() tests involving larger than 32-bit types and
mixed types.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed

core_self_tests.c: add more ADD_OVERFLOW() tests

Adds more ADD_OVERFLOW() tests involving larger than 32-bit types and
mixed types.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

util: update fallback SUB_OVERFLOW() macro

Updates the fallback SUB_OVERFLOW() macro to better support mixed types
in the arguments.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-b

util: update fallback SUB_OVERFLOW() macro

Updates the fallback SUB_OVERFLOW() macro to better support mixed types
in the arguments.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

util: update fallback ADD_OVERFLOW() macro

Updates the fallback ADD_OVERFLOW() macro to better support mixed types
in the arguments.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-b

util: update fallback ADD_OVERFLOW() macro

Updates the fallback ADD_OVERFLOW() macro to better support mixed types
in the arguments.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

plat-mediatek: support generic RAM layout

Move default secure and non-secure Optee memory locations from
platform_config.h to conf.mk using the generic_ram_layout.

Signed-off-by: Etienne Carriere <

plat-mediatek: support generic RAM layout

Move default secure and non-secure Optee memory locations from
platform_config.h to conf.mk using the generic_ram_layout.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

show more ...

plat-hikey: support generic RAM layout

Move default secure and non-secure Optee memory locations from
platform_config.h to conf.mk using the generic_ram_layout.

Signed-off-by: Etienne Carriere <eti

plat-hikey: support generic RAM layout

Move default secure and non-secure Optee memory locations from
platform_config.h to conf.mk using the generic_ram_layout.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey960)

show more ...

plat-d02: support generic RAM layout

Move default secure and non-secure Optee memory locations from
platform_config.h to conf.mk using the generic_ram_layout.

Signed-off-by: Etienne Carriere <etien

plat-d02: support generic RAM layout

Move default secure and non-secure Optee memory locations from
platform_config.h to conf.mk using the generic_ram_layout.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (D02)

show more ...

plat-stm: support generic RAM layout

Legacy stm platforms build env set CFG_DDR_TEETZ_RESERVED_START/_SIZE
and CFG_CORE_TZSRAM_EMUL_START/_SIZE. This change converts these into
CFG_TZxRAM_START/_SIZ

plat-stm: support generic RAM layout

Legacy stm platforms build env set CFG_DDR_TEETZ_RESERVED_START/_SIZE
and CFG_CORE_TZSRAM_EMUL_START/_SIZE. This change converts these into
CFG_TZxRAM_START/_SIZE and CFG_SHMEM_START/_SIZE from the platform
conf.mk.

Introduce stm platform specific configuration directive
CFG_STM_RSV_DRAM_STARTBYTES to carve out reserved bottom DDR from
REE main memory. Remove CFG_DDR_SECURE_BASE which is no more required.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2120, b2260)

show more ...

core: generic RAM layout

Include mm/generic_ram_layout.h at top of platform_config.h to
to get the TEE_RAM_*, TEE_TA_*, TEE_SHMEM_*, etc... defined from
generic configuration directives.

See descri

core: generic RAM layout

Include mm/generic_ram_layout.h at top of platform_config.h to
to get the TEE_RAM_*, TEE_TA_*, TEE_SHMEM_*, etc... defined from
generic configuration directives.

See description from generic_ram_layout.h head comments.

Suggested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

show more ...

libutils: MIN/MAX macros for assembly code

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>

arm32: stack unwinding for dynamically linked TAs

Update the ELF loader so that TAs that contain multiple ELF binaries
have a valid exception index table (EXIDX). This table is the entry
point for t

arm32: stack unwinding for dynamically linked TAs

Update the ELF loader so that TAs that contain multiple ELF binaries
have a valid exception index table (EXIDX). This table is the entry
point for the call stack unwinding code. When a TA uses shared
libraries, we create a new EXIDX table by joining all the tables found
in each ELF and patching them to account for the new table address.
Information about the ARM unwind tables can be found in [1].

Link: [1] https://wiki.linaro.org/KenWerner/Sandbox/libunwind?action=AttachFile&do=get&target=libunwind-LDS.pdf
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

plat-imx: implement PL310 SMC protocol

When Windows runs in normal world, it expects the PL310 to be initially
disabled, and then invokes SMCs to enable it.
When CFG_PL310_SIP_PROTOCOL=y, the L2 cac

plat-imx: implement PL310 SMC protocol

When Windows runs in normal world, it expects the PL310 to be initially
disabled, and then invokes SMCs to enable it.
When CFG_PL310_SIP_PROTOCOL=y, the L2 cache will be left untouched until
the OS enables it.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>

show more ...

plat-ls: consume CFG_SECONDARY_INIT_CNTFRQ

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>

core: add CFG_SECONDARY_INIT_CNTFRQ

Add configuration option to initialize CNTFRQ on secondary cores
to the same value as the primary core.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
S

core: add CFG_SECONDARY_INIT_CNTFRQ

Add configuration option to initialize CNTFRQ on secondary cores
to the same value as the primary core.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>

show more ...

doc: add slides concerning secure storage, fix layout

Signed-off-by: Michael Brandl <git@fineon.pw>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

ci: shippable: remove deprecated config flags

CFG_PS2MOUSE, CFG_PL050 and CFG_PL111 are gone so remove them from the
Shippable script.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

ci: shippable: remove deprecated config flags

CFG_PS2MOUSE, CFG_PL050 and CFG_PL111 are gone so remove them from the
Shippable script.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

ci: shippable: build with CFG_PCSC_PASSTHRU_READER_DRV=y

Commit 41f869fe7680 ("Fix crash when bumping qemu to 2.12.0") sets
CFG_PCSC_PASSTHRU_READER_DRV=n by default. Adjust .shippable.yml to
enable

ci: shippable: build with CFG_PCSC_PASSTHRU_READER_DRV=y

Commit 41f869fe7680 ("Fix crash when bumping qemu to 2.12.0") sets
CFG_PCSC_PASSTHRU_READER_DRV=n by default. Adjust .shippable.yml to
enable it instead, so that it is still compile-tested.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

ci: shippable: remove redundant line

CFG_WITH_STATS defaults to 'y' so remove the line that sets it
explicitly in .shippable.yml.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Revie

ci: shippable: remove redundant line

CFG_WITH_STATS defaults to 'y' so remove the line that sets it
explicitly in .shippable.yml.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core: fix OOM handling in tee_svc_storage_read_head()

Fixes out of memory handling error in tee_svc_storage_read_head(). Prior
to this all errors from fops->read() was reported as
TEE_ERROR_CORRUPT_

core: fix OOM handling in tee_svc_storage_read_head()

Fixes out of memory handling error in tee_svc_storage_read_head(). Prior
to this all errors from fops->read() was reported as
TEE_ERROR_CORRUPT_OBJECT leading to removal of the object even when the
real problem was temporary memory shortage. This patch reports
TEE_ERROR_OUT_OF_MEMORY from fops->read() correctly while translating
all other errors to TEE_ERROR_CORRUPT_OBJECT.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

core_self_tests:.c: add SUB_OVERFLOW() test

Add a test that fails with GCC 4.9.4 (Linaro GCC 4.9-2017.01) [1] with the
original overflow macros prior to commit 86ab9ffe82c6 ("util: fix fallback
SUB_

core_self_tests:.c: add SUB_OVERFLOW() test

Add a test that fails with GCC 4.9.4 (Linaro GCC 4.9-2017.01) [1] with the
original overflow macros prior to commit 86ab9ffe82c6 ("util: fix fallback
SUB_OVERFLOW() macro").

Link: [1] http://releases.linaro.org/components/toolchain/binaries/4.9-2017.01/arm-linux-gnueabihf/gcc-linaro-4.9.4-2017.01-x86_64_arm-linux-gnueabihf.tar.xz
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

core_self_tests:.c: add ADD_OVERFLOW() test

Add a test that fails with GCC 4.9.4 (Linaro GCC 4.9-2017.01) [1] with the
original overflow macros prior to commit 2b30433772af ("util: fix fallback
ADD_

core_self_tests:.c: add ADD_OVERFLOW() test

Add a test that fails with GCC 4.9.4 (Linaro GCC 4.9-2017.01) [1] with the
original overflow macros prior to commit 2b30433772af ("util: fix fallback
ADD_OVERFLOW() macro").

Link: [1] http://releases.linaro.org/components/toolchain/binaries/4.9-2017.01/arm-linux-gnueabihf/gcc-linaro-4.9.4-2017.01-x86_64_arm-linux-gnueabihf.tar.xz
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...