1/* SPDX-License-Identifier: BSD-2-Clause */ 2/* 3 * Copyright (c) 2016-2017, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30#include <arm32_macros.S> 31#include <arm.h> 32#include <asm-defines.h> 33#include <asm.S> 34#include <keep.h> 35#include <kernel/abort.h> 36#include <kernel/thread_defs.h> 37#include <kernel/unwind.h> 38#include <mm/core_mmu.h> 39#include <sm/optee_smc.h> 40#include <sm/teesmc_opteed.h> 41#include <sm/teesmc_opteed_macros.h> 42 43#include "thread_private.h" 44 45 .macro cmp_spsr_user_mode reg:req 46 /* 47 * We're only testing the lower 4 bits as bit 5 (0x10) 48 * always is set. 49 */ 50 tst \reg, #0x0f 51 .endm 52 53LOCAL_FUNC vector_std_smc_entry , : 54UNWIND( .fnstart) 55UNWIND( .cantunwind) 56 push {r0-r7} 57 mov r0, sp 58 bl thread_handle_std_smc 59 /* 60 * Normally thread_handle_std_smc() should return via 61 * thread_exit(), thread_rpc(), but if thread_handle_std_smc() 62 * hasn't switched stack (error detected) it will do a normal "C" 63 * return. 64 */ 65 pop {r1-r8} 66 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 67 smc #0 68 b . /* SMC should not return */ 69UNWIND( .fnend) 70END_FUNC vector_std_smc_entry 71 72LOCAL_FUNC vector_fast_smc_entry , : 73UNWIND( .fnstart) 74UNWIND( .cantunwind) 75 push {r0-r7} 76 mov r0, sp 77 bl thread_handle_fast_smc 78 pop {r1-r8} 79 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 80 smc #0 81 b . /* SMC should not return */ 82UNWIND( .fnend) 83END_FUNC vector_fast_smc_entry 84 85LOCAL_FUNC vector_fiq_entry , : 86UNWIND( .fnstart) 87UNWIND( .cantunwind) 88 /* Secure Monitor received a FIQ and passed control to us. */ 89 bl thread_check_canaries 90 ldr lr, =thread_nintr_handler_ptr 91 ldr lr, [lr] 92 blx lr 93 mov r1, r0 94 ldr r0, =TEESMC_OPTEED_RETURN_FIQ_DONE 95 smc #0 96 b . /* SMC should not return */ 97UNWIND( .fnend) 98END_FUNC vector_fiq_entry 99 100LOCAL_FUNC vector_cpu_on_entry , : 101UNWIND( .fnstart) 102UNWIND( .cantunwind) 103 ldr lr, =thread_cpu_on_handler_ptr 104 ldr lr, [lr] 105 blx lr 106 mov r1, r0 107 ldr r0, =TEESMC_OPTEED_RETURN_ON_DONE 108 smc #0 109 b . /* SMC should not return */ 110UNWIND( .fnend) 111END_FUNC vector_cpu_on_entry 112 113LOCAL_FUNC vector_cpu_off_entry , : 114UNWIND( .fnstart) 115UNWIND( .cantunwind) 116 ldr lr, =thread_cpu_off_handler_ptr 117 ldr lr, [lr] 118 blx lr 119 mov r1, r0 120 ldr r0, =TEESMC_OPTEED_RETURN_OFF_DONE 121 smc #0 122 b . /* SMC should not return */ 123UNWIND( .fnend) 124END_FUNC vector_cpu_off_entry 125 126LOCAL_FUNC vector_cpu_suspend_entry , : 127UNWIND( .fnstart) 128UNWIND( .cantunwind) 129 ldr lr, =thread_cpu_suspend_handler_ptr 130 ldr lr, [lr] 131 blx lr 132 mov r1, r0 133 ldr r0, =TEESMC_OPTEED_RETURN_SUSPEND_DONE 134 smc #0 135 b . /* SMC should not return */ 136UNWIND( .fnend) 137END_FUNC vector_cpu_suspend_entry 138 139LOCAL_FUNC vector_cpu_resume_entry , : 140UNWIND( .fnstart) 141UNWIND( .cantunwind) 142 ldr lr, =thread_cpu_resume_handler_ptr 143 ldr lr, [lr] 144 blx lr 145 mov r1, r0 146 ldr r0, =TEESMC_OPTEED_RETURN_RESUME_DONE 147 smc #0 148 b . /* SMC should not return */ 149UNWIND( .fnend) 150END_FUNC vector_cpu_resume_entry 151 152LOCAL_FUNC vector_system_off_entry , : 153UNWIND( .fnstart) 154UNWIND( .cantunwind) 155 ldr lr, =thread_system_off_handler_ptr 156 ldr lr, [lr] 157 blx lr 158 mov r1, r0 159 ldr r0, =TEESMC_OPTEED_RETURN_SYSTEM_OFF_DONE 160 smc #0 161 b . /* SMC should not return */ 162UNWIND( .fnend) 163END_FUNC vector_system_off_entry 164 165LOCAL_FUNC vector_system_reset_entry , : 166UNWIND( .fnstart) 167UNWIND( .cantunwind) 168 ldr lr, =thread_system_reset_handler_ptr 169 ldr lr, [lr] 170 blx lr 171 mov r1, r0 172 ldr r0, =TEESMC_OPTEED_RETURN_SYSTEM_RESET_DONE 173 smc #0 174 b . /* SMC should not return */ 175UNWIND( .fnend) 176END_FUNC vector_system_reset_entry 177 178/* 179 * Vector table supplied to ARM Trusted Firmware (ARM-TF) at 180 * initialization. Also used when compiled with the internal monitor, but 181 * the cpu_*_entry and system_*_entry are not used then. 182 * 183 * Note that ARM-TF depends on the layout of this vector table, any change 184 * in layout has to be synced with ARM-TF. 185 */ 186FUNC thread_vector_table , : 187UNWIND( .fnstart) 188UNWIND( .cantunwind) 189 b vector_std_smc_entry 190 b vector_fast_smc_entry 191 b vector_cpu_on_entry 192 b vector_cpu_off_entry 193 b vector_cpu_resume_entry 194 b vector_cpu_suspend_entry 195 b vector_fiq_entry 196 b vector_system_off_entry 197 b vector_system_reset_entry 198UNWIND( .fnend) 199END_FUNC thread_vector_table 200KEEP_PAGER thread_vector_table 201 202FUNC thread_set_abt_sp , : 203UNWIND( .fnstart) 204UNWIND( .cantunwind) 205 mrs r1, cpsr 206 cps #CPSR_MODE_ABT 207 mov sp, r0 208 msr cpsr, r1 209 bx lr 210UNWIND( .fnend) 211END_FUNC thread_set_abt_sp 212 213FUNC thread_set_und_sp , : 214UNWIND( .fnstart) 215UNWIND( .cantunwind) 216 mrs r1, cpsr 217 cps #CPSR_MODE_UND 218 mov sp, r0 219 msr cpsr, r1 220 bx lr 221UNWIND( .fnend) 222END_FUNC thread_set_und_sp 223 224FUNC thread_set_irq_sp , : 225UNWIND( .fnstart) 226UNWIND( .cantunwind) 227 mrs r1, cpsr 228 cps #CPSR_MODE_IRQ 229 mov sp, r0 230 msr cpsr, r1 231 bx lr 232UNWIND( .fnend) 233END_FUNC thread_set_irq_sp 234 235FUNC thread_set_fiq_sp , : 236UNWIND( .fnstart) 237UNWIND( .cantunwind) 238 mrs r1, cpsr 239 cps #CPSR_MODE_FIQ 240 mov sp, r0 241 msr cpsr, r1 242 bx lr 243UNWIND( .fnend) 244END_FUNC thread_set_fiq_sp 245 246/* void thread_resume(struct thread_ctx_regs *regs) */ 247FUNC thread_resume , : 248UNWIND( .fnstart) 249UNWIND( .cantunwind) 250 add r12, r0, #(13 * 4) /* Restore registers r0-r12 later */ 251 252 cps #CPSR_MODE_SYS 253 ldm r12!, {sp, lr} 254 255 cps #CPSR_MODE_SVC 256 ldm r12!, {r1, sp, lr} 257 msr spsr_fsxc, r1 258 259 ldm r12, {r1, r2} 260 261 /* 262 * Switching to some other mode than SVC as we need to set spsr in 263 * order to return into the old state properly and it may be SVC 264 * mode we're returning to. 265 */ 266 cps #CPSR_MODE_ABT 267 cmp_spsr_user_mode r2 268 mov lr, r1 269 msr spsr_fsxc, r2 270 ldm r0, {r0-r12} 271 movnes pc, lr 272 b eret_to_user_mode 273UNWIND( .fnend) 274END_FUNC thread_resume 275 276/* 277 * Disables IRQ and FIQ and saves state of thread in fiq mode which has 278 * the banked r8-r12 registers, returns original CPSR. 279 */ 280LOCAL_FUNC thread_save_state_fiq , : 281UNWIND( .fnstart) 282UNWIND( .cantunwind) 283 mov r9, lr 284 285 /* 286 * Uses stack for temporary storage, while storing needed 287 * context in the thread context struct. 288 */ 289 290 mrs r8, cpsr 291 292 cpsid aif /* Disable Async abort, IRQ and FIQ */ 293 294 push {r4-r7} 295 push {r0-r3} 296 297 mrs r6, cpsr /* Save current CPSR */ 298 299 bl thread_get_ctx_regs 300 301 pop {r1-r4} /* r0-r3 pushed above */ 302 stm r0!, {r1-r4} 303 pop {r1-r4} /* r4-r7 pushed above */ 304 stm r0!, {r1-r4} 305 306 cps #CPSR_MODE_SYS 307 stm r0!, {r8-r12} 308 stm r0!, {sp, lr} 309 310 cps #CPSR_MODE_SVC 311 mrs r1, spsr 312 stm r0!, {r1, sp, lr} 313 314 /* back to fiq mode */ 315 orr r6, r6, #ARM32_CPSR_FIA /* Disable Async abort, IRQ and FIQ */ 316 msr cpsr, r6 /* Restore mode */ 317 318 mov r0, r8 /* Return original CPSR */ 319 bx r9 320UNWIND( .fnend) 321END_FUNC thread_save_state_fiq 322 323/* 324 * Disables IRQ and FIQ and saves state of thread, returns original 325 * CPSR. 326 */ 327LOCAL_FUNC thread_save_state , : 328UNWIND( .fnstart) 329UNWIND( .cantunwind) 330 push {r12, lr} 331 /* 332 * Uses stack for temporary storage, while storing needed 333 * context in the thread context struct. 334 */ 335 336 mrs r12, cpsr 337 338 cpsid aif /* Disable Async abort, IRQ and FIQ */ 339 340 push {r4-r7} 341 push {r0-r3} 342 343 mov r5, r12 /* Save CPSR in a preserved register */ 344 mrs r6, cpsr /* Save current CPSR */ 345 346 bl thread_get_ctx_regs 347 348 pop {r1-r4} /* r0-r3 pushed above */ 349 stm r0!, {r1-r4} 350 pop {r1-r4} /* r4-r7 pushed above */ 351 stm r0!, {r1-r4} 352 stm r0!, {r8-r11} 353 354 pop {r12, lr} 355 stm r0!, {r12} 356 357 cps #CPSR_MODE_SYS 358 stm r0!, {sp, lr} 359 360 cps #CPSR_MODE_SVC 361 mrs r1, spsr 362 stm r0!, {r1, sp, lr} 363 364 orr r6, r6, #ARM32_CPSR_FIA /* Disable Async abort, IRQ and FIQ */ 365 msr cpsr, r6 /* Restore mode */ 366 367 mov r0, r5 /* Return original CPSR */ 368 bx lr 369UNWIND( .fnend) 370END_FUNC thread_save_state 371 372FUNC thread_std_smc_entry , : 373UNWIND( .fnstart) 374UNWIND( .cantunwind) 375 /* Pass r0-r7 in a struct thread_smc_args */ 376 push {r0-r7} 377 mov r0, sp 378 bl __thread_std_smc_entry 379 /* 380 * Load the returned r0-r3 into preserved registers and skip the 381 * "returned" r4-r7 since they will not be returned to normal 382 * world. 383 */ 384 pop {r4-r7} 385 add sp, #(4 * 4) 386 387 /* Disable interrupts before switching to temporary stack */ 388 cpsid aif 389 bl thread_get_tmp_sp 390 mov sp, r0 391 392 bl thread_state_free 393 394 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 395 mov r1, r4 396 mov r2, r5 397 mov r3, r6 398 mov r4, r7 399 smc #0 400 b . /* SMC should not return */ 401UNWIND( .fnend) 402END_FUNC thread_std_smc_entry 403 404 405/* void thread_rpc(uint32_t rv[THREAD_RPC_NUM_ARGS]) */ 406FUNC thread_rpc , : 407/* 408 * r0-r2 are used to pass parameters to normal world 409 * r0-r5 are used to pass return vaule back from normal world 410 * 411 * note that r3 is used to pass "resume information", that is, which 412 * thread it is that should resume. 413 * 414 * Since the this function is following AAPCS we need to preserve r4-r5 415 * which are otherwise modified when returning back from normal world. 416 */ 417UNWIND( .fnstart) 418 push {r4-r5, lr} 419UNWIND( .save {r4-r5, lr}) 420 push {r0} 421UNWIND( .save {r0}) 422 423 bl thread_save_state 424 mov r4, r0 /* Save original CPSR */ 425 426 /* 427 * Switch to temporary stack and SVC mode. Save CPSR to resume into. 428 */ 429 bl thread_get_tmp_sp 430 ldr r5, [sp] /* Get pointer to rv[] */ 431 cps #CPSR_MODE_SVC /* Change to SVC mode */ 432 mov sp, r0 /* Switch to tmp stack */ 433 434 mov r0, #THREAD_FLAGS_COPY_ARGS_ON_RETURN 435 mov r1, r4 /* CPSR to restore */ 436 ldr r2, =.thread_rpc_return 437 bl thread_state_suspend 438 mov r4, r0 /* Supply thread index */ 439 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 440 ldm r5, {r1-r3} /* Load rv[] into r0-r2 */ 441 smc #0 442 b . /* SMC should not return */ 443 444.thread_rpc_return: 445 /* 446 * At this point has the stack pointer been restored to the value 447 * it had when thread_save_state() was called above. 448 * 449 * Jumps here from thread_resume above when RPC has returned. The 450 * IRQ and FIQ bits are restored to what they where when this 451 * function was originally entered. 452 */ 453 pop {r12} /* Get pointer to rv[] */ 454 stm r12, {r0-r5} /* Store r0-r5 into rv[] */ 455 pop {r4-r5, pc} 456UNWIND( .fnend) 457END_FUNC thread_rpc 458KEEP_PAGER thread_rpc 459 460FUNC thread_init_vbar , : 461UNWIND( .fnstart) 462 /* Set vector (VBAR) */ 463 ldr r0, =thread_vect_table 464 write_vbar r0 465 bx lr 466UNWIND( .fnend) 467END_FUNC thread_init_vbar 468KEEP_PAGER thread_init_vbar 469 470/* 471 * Below are low level routines handling entry and return from user mode. 472 * 473 * thread_enter_user_mode() saves all that registers user mode can change 474 * so kernel mode can restore needed registers when resuming execution 475 * after the call to thread_enter_user_mode() has returned. 476 * thread_enter_user_mode() doesn't return directly since it enters user 477 * mode instead, it's thread_unwind_user_mode() that does the 478 * returning by restoring the registers saved by thread_enter_user_mode(). 479 * 480 * There's three ways for thread_enter_user_mode() to return to caller, 481 * user TA calls utee_return, user TA calls utee_panic or through an abort. 482 * 483 * Calls to utee_return or utee_panic are handled as: 484 * thread_svc_handler() -> tee_svc_handler() -> tee_svc_do_call() which 485 * calls syscall_return() or syscall_panic(). 486 * 487 * These function calls returns normally except thread_svc_handler() which 488 * which is an exception handling routine so it reads return address and 489 * SPSR to restore from the stack. syscall_return() and syscall_panic() 490 * changes return address and SPSR used by thread_svc_handler() to instead of 491 * returning into user mode as with other syscalls it returns into 492 * thread_unwind_user_mode() in kernel mode instead. When 493 * thread_svc_handler() returns the stack pointer at the point where 494 * thread_enter_user_mode() left it so this is where 495 * thread_unwind_user_mode() can operate. 496 * 497 * Aborts are handled in a similar way but by thread_abort_handler() 498 * instead, when the pager sees that it's an abort from user mode that 499 * can't be handled it updates SPSR and return address used by 500 * thread_abort_handler() to return into thread_unwind_user_mode() 501 * instead. 502 */ 503 504/* 505 * uint32_t __thread_enter_user_mode(unsigned long a0, unsigned long a1, 506 * unsigned long a2, unsigned long a3, unsigned long user_sp, 507 * unsigned long user_func, unsigned long spsr, 508 * uint32_t *exit_status0, uint32_t *exit_status1) 509 * 510 */ 511FUNC __thread_enter_user_mode , : 512UNWIND( .fnstart) 513UNWIND( .cantunwind) 514 /* 515 * Save all registers to allow syscall_return() to resume execution 516 * as if this function would have returned. This is also used in 517 * syscall_panic(). 518 * 519 * If stack usage of this function is changed 520 * thread_unwind_user_mode() has to be updated. 521 */ 522 push {r4-r12,lr} 523 524 ldr r4, [sp, #(10 * 0x4)] /* user stack pointer */ 525 ldr r5, [sp, #(11 * 0x4)] /* user function */ 526 ldr r6, [sp, #(12 * 0x4)] /* spsr */ 527 528 /* 529 * Save old user sp and set new user sp. 530 */ 531 cps #CPSR_MODE_SYS 532 mov r7, sp 533 mov sp, r4 534 cps #CPSR_MODE_SVC 535 push {r7,r8} 536 537 /* Prepare user mode entry via eret_to_user_mode */ 538 cpsid aif 539 msr spsr_fsxc, r6 540 mov lr, r5 541 542 b eret_to_user_mode 543UNWIND( .fnend) 544END_FUNC __thread_enter_user_mode 545 546/* 547 * void thread_unwind_user_mode(uint32_t ret, uint32_t exit_status0, 548 * uint32_t exit_status1); 549 * See description in thread.h 550 */ 551FUNC thread_unwind_user_mode , : 552UNWIND( .fnstart) 553UNWIND( .cantunwind) 554 ldr ip, [sp, #(15 * 0x4)] /* &ctx->panicked */ 555 str r1, [ip] 556 ldr ip, [sp, #(16 * 0x4)] /* &ctx->panic_code */ 557 str r2, [ip] 558 559 /* Restore old user sp */ 560 pop {r4,r7} 561 cps #CPSR_MODE_SYS 562 mov sp, r4 563 cps #CPSR_MODE_SVC 564 565 pop {r4-r12,pc} /* Match the push in thread_enter_user_mode()*/ 566UNWIND( .fnend) 567END_FUNC thread_unwind_user_mode 568 569 .macro maybe_restore_mapping 570 /* 571 * This macro is a bit hard to read due to all the ifdefs, 572 * we're testing for two different configs which makes four 573 * different combinations. 574 * 575 * - With LPAE, and then some extra code if with 576 * CFG_CORE_UNMAP_CORE_AT_EL0 577 * - Without LPAE, and then some extra code if with 578 * CFG_CORE_UNMAP_CORE_AT_EL0 579 */ 580 581 /* 582 * At this point we can't rely on any memory being writable 583 * yet, so we're using TPIDRPRW to store r0, and if with 584 * LPAE TPIDRURO to store r1 too. 585 */ 586 write_tpidrprw r0 587#if defined(CFG_CORE_UNMAP_CORE_AT_EL0) || defined(CFG_WITH_LPAE) 588 write_tpidruro r1 589#endif 590 591#ifdef CFG_WITH_LPAE 592 read_ttbr0_64bit r0, r1 593 tst r1, #BIT(TTBR_ASID_SHIFT - 32) 594 beq 11f 595 596#ifdef CFG_CORE_UNMAP_CORE_AT_EL0 597 /* 598 * Update the mapping to use the full kernel mode mapping. 599 * Since the translation table could reside above 4GB we'll 600 * have to use 64-bit arithmetics. 601 */ 602 subs r0, r0, #CORE_MMU_L1_TBL_OFFSET 603 sbc r1, r1, #0 604#endif 605 bic r1, r1, #BIT(TTBR_ASID_SHIFT - 32) 606 write_ttbr0_64bit r0, r1 607 isb 608 609#else /*!CFG_WITH_LPAE*/ 610 read_contextidr r0 611 tst r0, #1 612 beq 11f 613 614 /* Update the mapping to use the full kernel mode mapping. */ 615 bic r0, r0, #1 616 write_contextidr r0 617 isb 618#ifdef CFG_CORE_UNMAP_CORE_AT_EL0 619 read_ttbr1 r0 620 sub r0, r0, #CORE_MMU_L1_TBL_OFFSET 621 write_ttbr1 r0 622 isb 623#endif 624 625#endif /*!CFG_WITH_LPAE*/ 626 627#ifdef CFG_CORE_UNMAP_CORE_AT_EL0 628 ldr r0, =thread_user_kcode_offset 629 ldr r0, [r0] 630 read_vbar r1 631 add r1, r1, r0 632 write_vbar r1 633 isb 634 635 11: /* 636 * The PC is adjusted unconditionally to guard against the 637 * case there was an FIQ just before we did the "cpsid aif". 638 */ 639 ldr r0, =22f 640 bx r0 641 22: 642#else 643 11: 644#endif 645 read_tpidrprw r0 646#if defined(CFG_CORE_UNMAP_CORE_AT_EL0) || defined(CFG_WITH_LPAE) 647 read_tpidruro r1 648#endif 649 .endm 650 651/* The handler of native interrupt. */ 652.macro native_intr_handler mode:req 653 cpsid aif 654 maybe_restore_mapping 655 656 /* 657 * FIQ and IRQ have a +4 offset for lr compared to preferred return 658 * address 659 */ 660 sub lr, lr, #4 661 662 /* 663 * We're always saving {r0-r3}. In IRQ mode we're saving r12 also. 664 * In FIQ mode we're saving the banked fiq registers {r8-r12} FIQ 665 * because the secure monitor doesn't save those. The treatment of 666 * the banked fiq registers is somewhat analogous to the lazy save 667 * of VFP registers. 668 */ 669 .ifc \mode\(),fiq 670 push {r0-r3, r8-r12, lr} 671 .else 672 push {r0-r3, r12, lr} 673 .endif 674 675 bl thread_check_canaries 676 ldr lr, =thread_nintr_handler_ptr 677 ldr lr, [lr] 678 blx lr 679 680 mrs r0, spsr 681 cmp_spsr_user_mode r0 682 683 .ifc \mode\(),fiq 684 pop {r0-r3, r8-r12, lr} 685 .else 686 pop {r0-r3, r12, lr} 687 .endif 688 689 movnes pc, lr 690 b eret_to_user_mode 691.endm 692 693/* The handler of foreign interrupt. */ 694.macro foreign_intr_handler mode:req 695 cpsid aif 696 maybe_restore_mapping 697 698 sub lr, lr, #4 699 push {lr} 700 push {r12} 701 702 .ifc \mode\(),fiq 703 bl thread_save_state_fiq 704 .else 705 bl thread_save_state 706 .endif 707 708 mov r0, #THREAD_FLAGS_EXIT_ON_FOREIGN_INTR 709 mrs r1, spsr 710 pop {r12} 711 pop {r2} 712 blx thread_state_suspend 713 mov r4, r0 /* Supply thread index */ 714 715 /* 716 * Switch to SVC mode and copy current stack pointer as it already 717 * is the tmp stack. 718 */ 719 mov r0, sp 720 cps #CPSR_MODE_SVC 721 mov sp, r0 722 723 ldr r0, =TEESMC_OPTEED_RETURN_CALL_DONE 724 ldr r1, =OPTEE_SMC_RETURN_RPC_FOREIGN_INTR 725 mov r2, #0 726 mov r3, #0 727 /* r4 is already filled in above */ 728 smc #0 729 b . /* SMC should not return */ 730.endm 731 732 .section .text.thread_vect_table 733 .align 5 734FUNC thread_vect_table , : 735UNWIND( .fnstart) 736UNWIND( .cantunwind) 737 b . /* Reset */ 738 b thread_und_handler /* Undefined instruction */ 739 b thread_svc_handler /* System call */ 740 b thread_pabort_handler /* Prefetch abort */ 741 b thread_dabort_handler /* Data abort */ 742 b . /* Reserved */ 743 b thread_irq_handler /* IRQ */ 744 b thread_fiq_handler /* FIQ */ 745 746thread_und_handler: 747 cpsid aif 748 maybe_restore_mapping 749 strd r0, r1, [sp, #THREAD_CORE_LOCAL_R0] 750 mrs r1, spsr 751 tst r1, #CPSR_T 752 subne lr, lr, #2 753 subeq lr, lr, #4 754 mov r0, #ABORT_TYPE_UNDEF 755 b thread_abort_common 756 757thread_dabort_handler: 758 cpsid aif 759 maybe_restore_mapping 760 strd r0, r1, [sp, #THREAD_CORE_LOCAL_R0] 761 sub lr, lr, #8 762 mov r0, #ABORT_TYPE_DATA 763 b thread_abort_common 764 765thread_pabort_handler: 766 cpsid aif 767 maybe_restore_mapping 768 strd r0, r1, [sp, #THREAD_CORE_LOCAL_R0] 769 sub lr, lr, #4 770 mov r0, #ABORT_TYPE_PREFETCH 771 772thread_abort_common: 773 /* 774 * At this label: 775 * cpsr is in mode undef or abort 776 * sp is still pointing to struct thread_core_local belonging to 777 * this core. 778 * {r0, r1} are saved in struct thread_core_local pointed to by sp 779 * {r2-r11, ip} are untouched. 780 * r0 holds the first argument for abort_handler() 781 */ 782 783 /* 784 * Update core local flags. 785 * flags = (flags << THREAD_CLF_SAVED_SHIFT) | THREAD_CLF_ABORT; 786 */ 787 ldr r1, [sp, #THREAD_CORE_LOCAL_FLAGS] 788 lsl r1, r1, #THREAD_CLF_SAVED_SHIFT 789 orr r1, r1, #THREAD_CLF_ABORT 790 791 /* 792 * Select stack and update flags accordingly 793 * 794 * Normal case: 795 * If the abort stack is unused select that. 796 * 797 * Fatal error handling: 798 * If we're already using the abort stack as noted by bit 799 * (THREAD_CLF_SAVED_SHIFT + THREAD_CLF_ABORT_SHIFT) in the flags 800 * field we're selecting the temporary stack instead to be able to 801 * make a stack trace of the abort in abort mode. 802 * 803 * r1 is initialized as a temporary stack pointer until we've 804 * switched to system mode. 805 */ 806 tst r1, #(THREAD_CLF_ABORT << THREAD_CLF_SAVED_SHIFT) 807 orrne r1, r1, #THREAD_CLF_TMP /* flags |= THREAD_CLF_TMP; */ 808 str r1, [sp, #THREAD_CORE_LOCAL_FLAGS] 809 ldrne r1, [sp, #THREAD_CORE_LOCAL_TMP_STACK_VA_END] 810 ldreq r1, [sp, #THREAD_CORE_LOCAL_ABT_STACK_VA_END] 811 812 /* 813 * Store registers on stack fitting struct thread_abort_regs 814 * start from the end of the struct 815 * {r2-r11, ip} 816 * Load content of previously saved {r0-r1} and stores 817 * it up to the pad field. 818 * After this is only {usr_sp, usr_lr} missing in the struct 819 */ 820 stmdb r1!, {r2-r11, ip} /* Push on the selected stack */ 821 ldrd r2, r3, [sp, #THREAD_CORE_LOCAL_R0] 822 /* Push the original {r0-r1} on the selected stack */ 823 stmdb r1!, {r2-r3} 824 mrs r3, spsr 825 /* Push {pad, spsr, elr} on the selected stack */ 826 stmdb r1!, {r2, r3, lr} 827 828 cps #CPSR_MODE_SYS 829 str lr, [r1, #-4]! 830 str sp, [r1, #-4]! 831 mov sp, r1 832 833 bl abort_handler 834 835 mov ip, sp 836 ldr sp, [ip], #4 837 ldr lr, [ip], #4 838 839 /* 840 * Even if we entered via CPSR_MODE_UND, we are returning via 841 * CPSR_MODE_ABT. It doesn't matter as lr and spsr are assigned 842 * here. 843 */ 844 cps #CPSR_MODE_ABT 845 ldm ip!, {r0, r1, lr} /* r0 is pad */ 846 msr spsr_fsxc, r1 847 848 /* Update core local flags */ 849 ldr r0, [sp, #THREAD_CORE_LOCAL_FLAGS] 850 lsr r0, r0, #THREAD_CLF_SAVED_SHIFT 851 str r0, [sp, #THREAD_CORE_LOCAL_FLAGS] 852 853 cmp_spsr_user_mode r1 854 ldm ip, {r0-r11, ip} 855 movnes pc, lr 856 b eret_to_user_mode 857 /* end thread_abort_common */ 858 859thread_svc_handler: 860 cpsid aif 861 862 maybe_restore_mapping 863 864 push {r0-r7, lr} 865 mrs r0, spsr 866 push {r0} 867 mov r0, sp 868 bl tee_svc_handler 869 cpsid aif /* In case something was unmasked */ 870 pop {r0} 871 msr spsr_fsxc, r0 872 cmp_spsr_user_mode r0 873 pop {r0-r7, lr} 874 movnes pc, lr 875 b eret_to_user_mode 876 /* end thread_svc_handler */ 877 878thread_fiq_handler: 879#if defined(CFG_ARM_GICV3) 880 foreign_intr_handler fiq 881#else 882 native_intr_handler fiq 883#endif 884 /* end thread_fiq_handler */ 885 886thread_irq_handler: 887#if defined(CFG_ARM_GICV3) 888 native_intr_handler irq 889#else 890 foreign_intr_handler irq 891#endif 892 /* end thread_irq_handler */ 893 894 /* 895 * Returns to user mode. 896 * Expects to be jumped to with lr pointing to the user space 897 * address to jump to and spsr holding the desired cpsr. Async 898 * abort, irq and fiq should be masked. 899 */ 900eret_to_user_mode: 901 write_tpidrprw r0 902#if defined(CFG_CORE_UNMAP_CORE_AT_EL0) || defined(CFG_WITH_LPAE) 903 write_tpidruro r1 904#endif 905 906#ifdef CFG_CORE_UNMAP_CORE_AT_EL0 907 ldr r0, =thread_user_kcode_offset 908 ldr r0, [r0] 909 read_vbar r1 910 sub r1, r1, r0 911 write_vbar r1 912 isb 913 914 /* Jump into the reduced mapping before the full mapping is removed */ 915 ldr r1, =1f 916 sub r1, r1, r0 917 bx r1 9181: 919#endif /*CFG_CORE_UNMAP_CORE_AT_EL0*/ 920 921#ifdef CFG_WITH_LPAE 922 read_ttbr0_64bit r0, r1 923#ifdef CFG_CORE_UNMAP_CORE_AT_EL0 924 add r0, r0, #CORE_MMU_L1_TBL_OFFSET 925#endif 926 /* switch to user ASID */ 927 orr r1, r1, #BIT(TTBR_ASID_SHIFT - 32) 928 write_ttbr0_64bit r0, r1 929 isb 930#else /*!CFG_WITH_LPAE*/ 931#ifdef CFG_CORE_UNMAP_CORE_AT_EL0 932 read_ttbr1 r0 933 add r0, r0, #CORE_MMU_L1_TBL_OFFSET 934 write_ttbr1 r0 935 isb 936#endif 937 read_contextidr r0 938 orr r0, r0, #BIT(0) 939 write_contextidr r0 940 isb 941#endif /*!CFG_WITH_LPAE*/ 942 943 read_tpidrprw r0 944#if defined(CFG_CORE_UNMAP_CORE_AT_EL0) || defined(CFG_WITH_LPAE) 945 read_tpidruro r1 946#endif 947 948 movs pc, lr 949UNWIND( .fnend) 950END_FUNC thread_vect_table 951