1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2016, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #ifndef ARM32_H 31 #define ARM32_H 32 33 #include <sys/cdefs.h> 34 #include <stdint.h> 35 #include <util.h> 36 37 #define CORTEX_A7_PART_NUM 0xC07 38 #define CORTEX_A8_PART_NUM 0xC08 39 #define CORTEX_A9_PART_NUM 0xC09 40 #define CORTEX_A15_PART_NUM 0xC0F 41 #define CORTEX_A17_PART_NUM 0xC0E 42 #define CORTEX_A57_PART_NUM 0xD07 43 #define CORTEX_A72_PART_NUM 0xD08 44 #define CORTEX_A73_PART_NUM 0xD09 45 #define CORTEX_A75_PART_NUM 0xD0A 46 47 #define MIDR_PRIMARY_PART_NUM_SHIFT 4 48 #define MIDR_PRIMARY_PART_NUM_WIDTH 12 49 50 #define MIDR_IMPLEMENTER_SHIFT 24 51 #define MIDR_IMPLEMENTER_WIDTH 8 52 #define MIDR_IMPLEMENTER_ARM 0x41 53 54 #define CPSR_MODE_MASK ARM32_CPSR_MODE_MASK 55 #define CPSR_MODE_USR ARM32_CPSR_MODE_USR 56 #define CPSR_MODE_FIQ ARM32_CPSR_MODE_FIQ 57 #define CPSR_MODE_IRQ ARM32_CPSR_MODE_IRQ 58 #define CPSR_MODE_SVC ARM32_CPSR_MODE_SVC 59 #define CPSR_MODE_MON ARM32_CPSR_MODE_MON 60 #define CPSR_MODE_ABT ARM32_CPSR_MODE_ABT 61 #define CPSR_MODE_UND ARM32_CPSR_MODE_UND 62 #define CPSR_MODE_SYS ARM32_CPSR_MODE_SYS 63 64 #define CPSR_T ARM32_CPSR_T 65 #define CPSR_F_SHIFT ARM32_CPSR_F_SHIFT 66 #define CPSR_F ARM32_CPSR_F 67 #define CPSR_I ARM32_CPSR_I 68 #define CPSR_A ARM32_CPSR_A 69 #define CPSR_FIA ARM32_CPSR_FIA 70 #define CPSR_IT_MASK ARM32_CPSR_IT_MASK 71 #define CPSR_IT_MASK1 ARM32_CPSR_IT_MASK1 72 #define CPSR_IT_MASK2 ARM32_CPSR_IT_MASK2 73 74 #define SCR_NS BIT32(0) 75 #define SCR_IRQ BIT32(1) 76 #define SCR_FIQ BIT32(2) 77 #define SCR_EA BIT32(3) 78 #define SCR_FW BIT32(4) 79 #define SCR_AW BIT32(5) 80 #define SCR_NET BIT32(6) 81 #define SCR_SCD BIT32(7) 82 #define SCR_HCE BIT32(8) 83 #define SCR_SIF BIT32(9) 84 85 #define SCTLR_M BIT32(0) 86 #define SCTLR_A BIT32(1) 87 #define SCTLR_C BIT32(2) 88 #define SCTLR_CP15BEN BIT32(5) 89 #define SCTLR_SW BIT32(10) 90 #define SCTLR_Z BIT32(11) 91 #define SCTLR_I BIT32(12) 92 #define SCTLR_V BIT32(13) 93 #define SCTLR_RR BIT32(14) 94 #define SCTLR_HA BIT32(17) 95 #define SCTLR_WXN BIT32(19) 96 #define SCTLR_UWXN BIT32(20) 97 #define SCTLR_FI BIT32(21) 98 #define SCTLR_VE BIT32(24) 99 #define SCTLR_EE BIT32(25) 100 #define SCTLR_NMFI BIT32(26) 101 #define SCTLR_TRE BIT32(28) 102 #define SCTLR_AFE BIT32(29) 103 #define SCTLR_TE BIT32(30) 104 105 #define ACTLR_SMP BIT32(6) 106 107 #define NSACR_CP10 BIT32(10) 108 #define NSACR_CP11 BIT32(11) 109 #define NSACR_NSD32DIS BIT32(14) 110 #define NSACR_NSASEDIS BIT32(15) 111 #define NSACR_NS_L2ERR BIT32(17) 112 #define NSACR_NS_SMP BIT32(18) 113 114 #define CPACR_ASEDIS BIT32(31) 115 #define CPACR_D32DIS BIT32(30) 116 #define CPACR_CP(co_proc, access) SHIFT_U32((access), ((co_proc) * 2)) 117 #define CPACR_CP_ACCESS_DENIED 0x0 118 #define CPACR_CP_ACCESS_PL1_ONLY 0x1 119 #define CPACR_CP_ACCESS_FULL 0x3 120 121 122 #define DACR_DOMAIN(num, perm) SHIFT_U32((perm), ((num) * 2)) 123 #define DACR_DOMAIN_PERM_NO_ACCESS 0x0 124 #define DACR_DOMAIN_PERM_CLIENT 0x1 125 #define DACR_DOMAIN_PERM_MANAGER 0x3 126 127 #define PAR_F BIT32(0) 128 #define PAR_SS BIT32(1) 129 #define PAR_LPAE BIT32(11) 130 #define PAR_PA_SHIFT 12 131 #define PAR32_PA_MASK (BIT32(20) - 1) 132 #define PAR64_PA_MASK (BIT64(28) - 1) 133 134 /* 135 * TTBCR has different register layout if LPAE is enabled or not. 136 * TTBCR.EAE == 0 => LPAE is not enabled 137 * TTBCR.EAE == 1 => LPAE is enabled 138 */ 139 #define TTBCR_EAE BIT32(31) 140 141 /* When TTBCR.EAE == 0 */ 142 #define TTBCR_PD0 BIT32(4) 143 #define TTBCR_PD1 BIT32(5) 144 145 /* When TTBCR.EAE == 1 */ 146 #define TTBCR_T0SZ_SHIFT 0 147 #define TTBCR_EPD0 BIT32(7) 148 #define TTBCR_IRGN0_SHIFT 8 149 #define TTBCR_ORGN0_SHIFT 10 150 #define TTBCR_SH0_SHIFT 12 151 #define TTBCR_T1SZ_SHIFT 16 152 #define TTBCR_A1 BIT32(22) 153 #define TTBCR_EPD1 BIT32(23) 154 #define TTBCR_IRGN1_SHIFT 24 155 #define TTBCR_ORGN1_SHIFT 26 156 #define TTBCR_SH1_SHIFT 28 157 158 /* Normal memory, Inner/Outer Non-cacheable */ 159 #define TTBCR_XRGNX_NC 0x0 160 /* Normal memory, Inner/Outer Write-Back Write-Allocate Cacheable */ 161 #define TTBCR_XRGNX_WB 0x1 162 /* Normal memory, Inner/Outer Write-Through Cacheable */ 163 #define TTBCR_XRGNX_WT 0x2 164 /* Normal memory, Inner/Outer Write-Back no Write-Allocate Cacheable */ 165 #define TTBCR_XRGNX_WBWA 0x3 166 167 /* Non-shareable */ 168 #define TTBCR_SHX_NSH 0x0 169 /* Outer Shareable */ 170 #define TTBCR_SHX_OSH 0x2 171 /* Inner Shareable */ 172 #define TTBCR_SHX_ISH 0x3 173 174 #define TTBR_ASID_MASK 0xff 175 #define TTBR_ASID_SHIFT 48 176 177 178 #define FSR_LPAE BIT32(9) 179 #define FSR_WNR BIT32(11) 180 181 /* Valid if FSR.LPAE is 1 */ 182 #define FSR_STATUS_MASK (BIT32(6) - 1) 183 184 /* Valid if FSR.LPAE is 0 */ 185 #define FSR_FS_MASK (BIT32(10) | (BIT32(4) - 1)) 186 187 #ifndef ASM 188 static inline uint32_t read_mpidr(void) 189 { 190 uint32_t mpidr; 191 192 asm volatile ("mrc p15, 0, %[mpidr], c0, c0, 5" 193 : [mpidr] "=r" (mpidr) 194 ); 195 196 return mpidr; 197 } 198 199 static inline uint32_t read_sctlr(void) 200 { 201 uint32_t sctlr; 202 203 asm volatile ("mrc p15, 0, %[sctlr], c1, c0, 0" 204 : [sctlr] "=r" (sctlr) 205 ); 206 207 return sctlr; 208 } 209 210 static inline void write_sctlr(uint32_t sctlr) 211 { 212 asm volatile ("mcr p15, 0, %[sctlr], c1, c0, 0" 213 : : [sctlr] "r" (sctlr) 214 ); 215 } 216 217 static inline uint32_t read_cpacr(void) 218 { 219 uint32_t cpacr; 220 221 asm volatile ("mrc p15, 0, %[cpacr], c1, c0, 2" 222 : [cpacr] "=r" (cpacr) 223 ); 224 225 return cpacr; 226 } 227 228 static inline void write_cpacr(uint32_t cpacr) 229 { 230 asm volatile ("mcr p15, 0, %[cpacr], c1, c0, 2" 231 : : [cpacr] "r" (cpacr) 232 ); 233 } 234 235 static inline void write_ttbr0(uint32_t ttbr0) 236 { 237 asm volatile ("mcr p15, 0, %[ttbr0], c2, c0, 0" 238 : : [ttbr0] "r" (ttbr0) 239 ); 240 } 241 242 static inline void write_ttbr0_64bit(uint64_t ttbr0) 243 { 244 asm volatile ("mcrr p15, 0, %Q[ttbr0], %R[ttbr0], c2" 245 : : [ttbr0] "r" (ttbr0) 246 ); 247 } 248 249 static inline uint32_t read_ttbr0(void) 250 { 251 uint32_t ttbr0; 252 253 asm volatile ("mrc p15, 0, %[ttbr0], c2, c0, 0" 254 : [ttbr0] "=r" (ttbr0) 255 ); 256 257 return ttbr0; 258 } 259 260 static inline uint64_t read_ttbr0_64bit(void) 261 { 262 uint64_t ttbr0; 263 264 asm volatile ("mrrc p15, 0, %Q[ttbr0], %R[ttbr0], c2" 265 : [ttbr0] "=r" (ttbr0) 266 ); 267 268 return ttbr0; 269 } 270 271 static inline void write_ttbr1(uint32_t ttbr1) 272 { 273 asm volatile ("mcr p15, 0, %[ttbr1], c2, c0, 1" 274 : : [ttbr1] "r" (ttbr1) 275 ); 276 } 277 278 static inline void write_ttbr1_64bit(uint64_t ttbr1) 279 { 280 asm volatile ("mcrr p15, 1, %Q[ttbr1], %R[ttbr1], c2" 281 : : [ttbr1] "r" (ttbr1) 282 ); 283 } 284 285 static inline uint32_t read_ttbr1(void) 286 { 287 uint32_t ttbr1; 288 289 asm volatile ("mrc p15, 0, %[ttbr1], c2, c0, 1" 290 : [ttbr1] "=r" (ttbr1) 291 ); 292 293 return ttbr1; 294 } 295 296 297 static inline void write_ttbcr(uint32_t ttbcr) 298 { 299 asm volatile ("mcr p15, 0, %[ttbcr], c2, c0, 2" 300 : : [ttbcr] "r" (ttbcr) 301 ); 302 } 303 304 static inline uint32_t read_ttbcr(void) 305 { 306 uint32_t ttbcr; 307 308 asm volatile ("mrc p15, 0, %[ttbcr], c2, c0, 2" 309 : [ttbcr] "=r" (ttbcr) 310 ); 311 312 return ttbcr; 313 } 314 315 static inline void write_dacr(uint32_t dacr) 316 { 317 asm volatile ("mcr p15, 0, %[dacr], c3, c0, 0" 318 : : [dacr] "r" (dacr) 319 ); 320 } 321 322 static inline uint32_t read_ifar(void) 323 { 324 uint32_t ifar; 325 326 asm volatile ("mrc p15, 0, %[ifar], c6, c0, 2" 327 : [ifar] "=r" (ifar) 328 ); 329 330 return ifar; 331 } 332 333 static inline uint32_t read_dfar(void) 334 { 335 uint32_t dfar; 336 337 asm volatile ("mrc p15, 0, %[dfar], c6, c0, 0" 338 : [dfar] "=r" (dfar) 339 ); 340 341 return dfar; 342 } 343 344 static inline uint32_t read_dfsr(void) 345 { 346 uint32_t dfsr; 347 348 asm volatile ("mrc p15, 0, %[dfsr], c5, c0, 0" 349 : [dfsr] "=r" (dfsr) 350 ); 351 352 return dfsr; 353 } 354 355 static inline uint32_t read_ifsr(void) 356 { 357 uint32_t ifsr; 358 359 asm volatile ("mrc p15, 0, %[ifsr], c5, c0, 1" 360 : [ifsr] "=r" (ifsr) 361 ); 362 363 return ifsr; 364 } 365 366 static inline void write_scr(uint32_t scr) 367 { 368 asm volatile ("mcr p15, 0, %[scr], c1, c1, 0" 369 : : [scr] "r" (scr) 370 ); 371 } 372 373 static inline void isb(void) 374 { 375 asm volatile ("isb"); 376 } 377 378 static inline void dsb(void) 379 { 380 asm volatile ("dsb"); 381 } 382 383 static inline void dsb_ish(void) 384 { 385 asm volatile ("dsb ish"); 386 } 387 388 static inline void dsb_ishst(void) 389 { 390 asm volatile ("dsb ishst"); 391 } 392 393 static inline void dmb(void) 394 { 395 asm volatile ("dmb"); 396 } 397 398 static inline void sev(void) 399 { 400 asm volatile ("sev"); 401 } 402 403 static inline void wfe(void) 404 { 405 asm volatile ("wfe"); 406 } 407 408 /* Address translate privileged write translation (current state secure PL1) */ 409 static inline void write_ats1cpw(uint32_t va) 410 { 411 asm volatile ("mcr p15, 0, %0, c7, c8, 1" : : "r" (va)); 412 } 413 414 static inline void write_ats1cpr(uint32_t va) 415 { 416 asm volatile ("mcr p15, 0, %0, c7, c8, 0" : : "r" (va)); 417 } 418 419 static inline void write_ats1cpuw(uint32_t va) 420 { 421 asm volatile ("mcr p15, 0, %0, c7, c8, 3" : : "r" (va)); 422 } 423 424 static inline void write_ats1cpur(uint32_t va) 425 { 426 asm volatile ("mcr p15, 0, %0, c7, c8, 2" : : "r" (va)); 427 } 428 429 static inline uint32_t read_par32(void) 430 { 431 uint32_t val; 432 433 asm volatile ("mrc p15, 0, %0, c7, c4, 0" : "=r" (val)); 434 return val; 435 } 436 437 #ifdef CFG_WITH_LPAE 438 static inline uint64_t read_par64(void) 439 { 440 uint64_t val; 441 442 asm volatile ("mrrc p15, 0, %Q0, %R0, c7" : "=r" (val)); 443 return val; 444 } 445 #endif 446 447 static inline void write_tlbimvaais(uint32_t mva) 448 { 449 asm volatile ("mcr p15, 0, %[mva], c8, c3, 3" 450 : : [mva] "r" (mva) 451 ); 452 } 453 454 static inline void write_mair0(uint32_t mair0) 455 { 456 asm volatile ("mcr p15, 0, %[mair0], c10, c2, 0" 457 : : [mair0] "r" (mair0) 458 ); 459 } 460 461 static inline void write_prrr(uint32_t prrr) 462 { 463 /* 464 * Same physical register as MAIR0. 465 * 466 * When an implementation includes the Large Physical Address 467 * Extension, and address translation is using the Long-descriptor 468 * translation table formats, MAIR0 replaces the PRRR 469 */ 470 write_mair0(prrr); 471 } 472 473 static inline void write_mair1(uint32_t mair1) 474 { 475 asm volatile ("mcr p15, 0, %[mair1], c10, c2, 1" 476 : : [mair1] "r" (mair1) 477 ); 478 } 479 480 static inline void write_nmrr(uint32_t nmrr) 481 { 482 /* 483 * Same physical register as MAIR1. 484 * 485 * When an implementation includes the Large Physical Address 486 * Extension, and address translation is using the Long-descriptor 487 * translation table formats, MAIR1 replaces the NMRR 488 */ 489 write_mair1(nmrr); 490 } 491 492 static inline uint32_t read_contextidr(void) 493 { 494 uint32_t contextidr; 495 496 asm volatile ("mrc p15, 0, %[contextidr], c13, c0, 1" 497 : [contextidr] "=r" (contextidr) 498 ); 499 500 return contextidr; 501 } 502 503 static inline void write_contextidr(uint32_t contextidr) 504 { 505 asm volatile ("mcr p15, 0, %[contextidr], c13, c0, 1" 506 : : [contextidr] "r" (contextidr) 507 ); 508 } 509 510 static inline uint32_t read_cpsr(void) 511 { 512 uint32_t cpsr; 513 514 asm volatile ("mrs %[cpsr], cpsr" 515 : [cpsr] "=r" (cpsr) 516 ); 517 return cpsr; 518 } 519 520 static inline void write_cpsr(uint32_t cpsr) 521 { 522 asm volatile ("msr cpsr_fsxc, %[cpsr]" 523 : : [cpsr] "r" (cpsr) 524 ); 525 } 526 527 static inline uint32_t read_spsr(void) 528 { 529 uint32_t spsr; 530 531 asm volatile ("mrs %[spsr], spsr" 532 : [spsr] "=r" (spsr) 533 ); 534 return spsr; 535 } 536 537 static inline uint32_t read_actlr(void) 538 { 539 uint32_t actlr; 540 541 asm volatile ("mrc p15, 0, %[actlr], c1, c0, 1" 542 : [actlr] "=r" (actlr) 543 ); 544 545 return actlr; 546 } 547 548 static inline void write_actlr(uint32_t actlr) 549 { 550 asm volatile ("mcr p15, 0, %[actlr], c1, c0, 1" 551 : : [actlr] "r" (actlr) 552 ); 553 } 554 555 static inline uint32_t read_nsacr(void) 556 { 557 uint32_t nsacr; 558 559 asm volatile ("mrc p15, 0, %[nsacr], c1, c1, 2" 560 : [nsacr] "=r" (nsacr) 561 ); 562 563 return nsacr; 564 } 565 566 static inline void write_nsacr(uint32_t nsacr) 567 { 568 asm volatile ("mcr p15, 0, %[nsacr], c1, c1, 2" 569 : : [nsacr] "r" (nsacr) 570 ); 571 } 572 573 static inline uint64_t read_cntpct(void) 574 { 575 uint64_t val; 576 577 asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (val)); 578 return val; 579 } 580 581 static inline uint32_t read_cntfrq(void) 582 { 583 uint32_t frq; 584 585 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq)); 586 return frq; 587 } 588 589 static inline void write_cntfrq(uint32_t frq) 590 { 591 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (frq)); 592 } 593 594 static inline uint32_t read_cntkctl(void) 595 { 596 uint32_t cntkctl; 597 598 asm volatile("mrc p15, 0, %0, c14, c1, 0" : "=r" (cntkctl)); 599 return cntkctl; 600 } 601 602 static inline void write_cntkctl(uint32_t cntkctl) 603 { 604 asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl)); 605 } 606 607 static __always_inline uint32_t read_pc(void) 608 { 609 uint32_t val; 610 611 asm volatile ("adr %0, ." : "=r" (val)); 612 return val; 613 } 614 615 static __always_inline uint32_t read_sp(void) 616 { 617 uint32_t val; 618 619 asm volatile ("mov %0, sp" : "=r" (val)); 620 return val; 621 } 622 623 static __always_inline uint32_t read_lr(void) 624 { 625 uint32_t val; 626 627 asm volatile ("mov %0, lr" : "=r" (val)); 628 return val; 629 } 630 631 static __always_inline uint32_t read_fp(void) 632 { 633 uint32_t val; 634 635 asm volatile ("mov %0, fp" : "=r" (val)); 636 return val; 637 } 638 639 static __always_inline uint32_t read_r7(void) 640 { 641 uint32_t val; 642 643 asm volatile ("mov %0, r7" : "=r" (val)); 644 return val; 645 } 646 647 /* Register read/write functions for GICC registers by using system interface */ 648 static inline uint32_t read_icc_ctlr(void) 649 { 650 uint32_t v; 651 652 asm volatile ("mrc p15,0,%0,c12,c12,4" : "=r" (v)); 653 return v; 654 } 655 656 static inline void write_icc_ctlr(uint32_t v) 657 { 658 asm volatile ("mcr p15,0,%0,c12,c12,4" : : "r" (v)); 659 } 660 661 static inline void write_icc_pmr(uint32_t v) 662 { 663 asm volatile ("mcr p15,0,%0,c4,c6,0" : : "r" (v)); 664 } 665 666 static inline uint32_t read_icc_iar0(void) 667 { 668 uint32_t v; 669 670 asm volatile ("mrc p15,0,%0,c12,c8,0" : "=r" (v)); 671 return v; 672 } 673 674 static inline void write_icc_eoir0(uint32_t v) 675 { 676 asm volatile ("mcr p15,0,%0,c12,c8,1" : : "r" (v)); 677 } 678 679 static inline uint64_t read_pmu_ccnt(void) 680 { 681 uint32_t val; 682 683 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r"(val)); 684 return val; 685 } 686 687 static inline void wfi(void) 688 { 689 asm volatile("wfi"); 690 } 691 #endif /*ASM*/ 692 693 #endif /*ARM32_H*/ 694