| 0fd85dcd | 18-Jan-2022 |
Clement Faure <clement.faure@nxp.com> |
ci: azure: build imx-mx8ulpevk platform
Add the i.MX8ULP platform to the build list.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome@forissier.org> |
| e62c30da | 31-May-2021 |
Clement Faure <clement.faure@nxp.com> |
drivers: caam: add imx8ulp CAAM HAL
Add imx8ulp CAAM HAL functions.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome@forissier.org> |
| 9781fbd2 | 31-May-2021 |
Clement Faure <clement.faure@nxp.com> |
core: imx: add support for i.MX8ULP
Add support for i.MX8ULP platform.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome@forissier.org> |
| 3f45afc3 | 19-Jan-2022 |
Clement Faure <clement.faure@nxp.com> |
drivers: caam: disable the use of interrupts for some platforms
On some i.MX platforms, all CAAM JRs share the same line of interrupts. To avoid conflicts with the other job ring owners, skip the en
drivers: caam: disable the use of interrupts for some platforms
On some i.MX platforms, all CAAM JRs share the same line of interrupts. To avoid conflicts with the other job ring owners, skip the enable/disable of job ring interruptions in OP-TEE CAAM driver.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome@forissier.org>
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| ace4d69d | 20-Jan-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: use a paged scattered array for DT drivers list
Fixes macro DEFINE_DT_DRIVER() to use SCATTERED_ARRAY_DEFINE_PG_ITEM() that defines a pageable resources whereas SCATTERED_ARRAY_DEFINE_ITEM() a
core: use a paged scattered array for DT drivers list
Fixes macro DEFINE_DT_DRIVER() to use SCATTERED_ARRAY_DEFINE_PG_ITEM() that defines a pageable resources whereas SCATTERED_ARRAY_DEFINE_ITEM() assumes array and its dependencies must be linked in the rodata_init section. Indeed DT driver probing is done after pager is initialized.
Fixes: 61bdedea9452 ("core: define DT drivers using scattered arrays") Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome@forissier.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| c212a6ee | 17-Jan-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
crypto: drivers: se050: ecc sign/verify padding
Pad small messages with zeroes during sign/verify.
Fixes xtest pkcs11_1019.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Acked-by: Etienn
crypto: drivers: se050: ecc sign/verify padding
Pad small messages with zeroes during sign/verify.
Fixes xtest pkcs11_1019.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 1a0e267a | 19-Jan-2022 |
Sahil Malhotra <sahil.malhotra@nxp.com> |
core: plat-ls: ls1028a: fix uart address
Fix UART0_BASE address for LS1028 platform
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com> Acked-by: Jerome Forissier <jerome@forissier.org> |
| 86010d2a | 18-Jan-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
drivers: crypto: se050: build Plug-and-Trust using the TEE makefiles
Building the Plug-and-Trust library required building OP-TEE first in order to get some architecture specific definitions. This m
drivers: crypto: se050: build Plug-and-Trust using the TEE makefiles
Building the Plug-and-Trust library required building OP-TEE first in order to get some architecture specific definitions. This makes the integration with yocto metas unnecessarily complex.
The following commit simplifies the build sequence: the user would need to clone the Plug-and-Trust tree [1] to an accessible location in the filesystem and then build OP-TEE as usual passing the path to the Plug-and-Trust tree in CFG_NXP_SE05X_PLUG_AND_TRUST.
[1] https://github.com/foundriesio/plug-and-trust.git
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Reviewed-by: Jerome Forissier <jerome@forissier.org>
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| d50ff941 | 19-Jan-2022 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
mk/subdir.mk: handle repositories outside the OP-TEE tree
The tags incdirs_ext and subdirs_ext allows specifying paths outside the current tree.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.
mk/subdir.mk: handle repositories outside the OP-TEE tree
The tags incdirs_ext and subdirs_ext allows specifying paths outside the current tree.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Reviewed-by: Jerome Forissier <jerome@forissier.org>
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| 05c007f2 | 05-Jan-2022 |
Donald Chan <hoiho@amazon.com> |
scripts/sign_encrypt.py: Support signing TAs using AWS KMS
This adds support for signing trusted applications (TAs) using a customer owned AWS KMS asymmetric key.
When the option to --key points to
scripts/sign_encrypt.py: Support signing TAs using AWS KMS
This adds support for signing trusted applications (TAs) using a customer owned AWS KMS asymmetric key.
When the option to --key points to a valid Amazon Resource Name (ARN), the signing operation will be delegated to AWS KMS. IAM credentials are provided via environment variables.
Requires boto3 to work correctly.
Acked-by: Jerome Forissier <jerome@forissier.org> Signed-off-by: Donald Chan <hoiho@amazon.com>
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| c689b8ee | 19-Jan-2022 |
Jelle Sels <jelle.sels@arm.com> |
core: spmc: Fix flags and tag in retrieve request
Inside check_retrieve_request() the flags and tag where swapped. Store them in the correct variable.
Fixes: de66193d9849 ("core: FF-A: ADD FFA_MEM_
core: spmc: Fix flags and tag in retrieve request
Inside check_retrieve_request() the flags and tag where swapped. Store them in the correct variable.
Fixes: de66193d9849 ("core: FF-A: ADD FFA_MEM_RETRIEVE for SPs") Signed-off-by: Jelle Sels <jelle.sels@arm.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 8f3a1455 | 18-Jan-2022 |
Patrick Delaunay <patrick.delaunay@foss.st.com> |
plat-stm32mp1: allow non-secure to read DDR registers
Changes stm32mp1 ETZPC configuration to allow non-secure read access to DDRCTRL and DDRPHYC interface register. This change will be needed by ne
plat-stm32mp1: allow non-secure to read DDR registers
Changes stm32mp1 ETZPC configuration to allow non-secure read access to DDRCTRL and DDRPHYC interface register. This change will be needed by next U-Boot release v2022.04 since merge of [1] in order to dynamically compute the DDR size.
Link: [1] https://source.denx.de/u-boot/u-boot/-/commit/d72e7bbe7c2841f161848d57b723495a731d0121 Acked-by: Jerome Forissier <jerome@forissier.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| b18c00f4 | 18-Jan-2022 |
Clement Faure <clement.faure@nxp.com> |
ci: azure: build imx-mx8dxlevk platform
Add the i.MX8DXL platform to the build list
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome@forissier.org> |
| 2a7ffe2f | 28-Feb-2020 |
Silvano di Ninno <silvano.dininno@nxp.com> |
core: imx: add support for i.MX8DXL
Add the i.MX 8DXL SoC support.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> Acked-by: Jerome Forissier <jerome@forissier.org> |
| 8280ec5d | 13-Mar-2020 |
Silvano di Ninno <silvano.dininno@nxp.com> |
core: imx: crypto_conf: change CAAM default job ring for mscale platforms
Change the default CAAM job ring index from 0 to 2 for the following platforms: * imx8mmevk * imx8mnevk * imx8mpevk * im
core: imx: crypto_conf: change CAAM default job ring for mscale platforms
Change the default CAAM job ring index from 0 to 2 for the following platforms: * imx8mmevk * imx8mnevk * imx8mpevk * imx8mqevk It leaves JR0 available for the HAB to authenticate and decrypt boot images.
Fixes: 2d7a8964 ("driver: implement CAAM driver") Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome@forissier.org>
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| 9567aeeb | 14-Jan-2022 |
Clement Faure <clement.faure@nxp.com> |
drivers: imx_wdog: fix compilation warning on watchdog driver
$ make PLATFORM=imx-mx7ulpevk CFG_DT=n core/drivers/imx_wdog.c:42:13: warning: ext_reset_output defined but not used [-Wunused-variable]
drivers: imx_wdog: fix compilation warning on watchdog driver
$ make PLATFORM=imx-mx7ulpevk CFG_DT=n core/drivers/imx_wdog.c:42:13: warning: ext_reset_output defined but not used [-Wunused-variable] 42 | static bool ext_reset_output; | ^~~~~~~~~~~~~~~~
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome@forissier.org>
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| c54ad22a | 17-Jan-2022 |
Clement Faure <clement.faure@nxp.com> |
drivers: imx_wdog: fix compilation watchdog driver on mx7ulp
Define WDOG_BASE and WDOG_SIZE value for mx7ulp platform.
$ make PLATFORM=imx-mx7ulpevk CFG_DT=n core/drivers/imx_wdog.c:151:42: error:
drivers: imx_wdog: fix compilation watchdog driver on mx7ulp
Define WDOG_BASE and WDOG_SIZE value for mx7ulp platform.
$ make PLATFORM=imx-mx7ulpevk CFG_DT=n core/drivers/imx_wdog.c:151:42: error: WDOG_BASE undeclared here (not in a function); did you mean WDOG_CS? 151 | register_phys_mem_pgdir(MEM_AREA_IO_SEC, WDOG_BASE, CORE_MMU_PGDIR_SIZE); |
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome@forissier.org>
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| 42e17e72 | 25-Oct-2021 |
Clement Faure <clement.faure@nxp.com> |
core: imx: enable the CAAM on imx8q platforms
Enabled the CAAM on the following platforms: * imx8qm * imx8qxp
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jero
core: imx: enable the CAAM on imx8q platforms
Enabled the CAAM on the following platforms: * imx8qm * imx8qxp
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome@forissier.org>
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| 833c7e36 | 13-Mar-2020 |
Remi Koman <remi.koman@nxp.com> |
drivers: caam: fix aligned buffer allocation for DMA
For aligned memory buffer and DMA CAAM access, the allocated buffer size must be rounded up to a certain value depending of the DMA behaviour on
drivers: caam: fix aligned buffer allocation for DMA
For aligned memory buffer and DMA CAAM access, the allocated buffer size must be rounded up to a certain value depending of the DMA behaviour on the platform. For the imx8qm/qxp, the allocated aligned buffer size must be rounded up to 4 bytes.
Signed-off-by: Remi Koman <remi.koman@nxp.com> Acked-by: Jerome Forissier <jerome@forissier.org>
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| 96ae1d34 | 25-Oct-2021 |
Clement Faure <clement.faure@nxp.com> |
core: imx: set CAAM configuration for imx8q platforms
Define the JR block size, JR index and the JR interruption number for the following platforms: * imx8qm * imx8qxp
Signed-off-by: Clement Faur
core: imx: set CAAM configuration for imx8q platforms
Define the JR block size, JR index and the JR interruption number for the following platforms: * imx8qm * imx8qxp
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome@forissier.org>
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| 6b651796 | 17-Nov-2021 |
Etienne Carriere <etienne.carriere@linaro.org> |
drivers: clk: move stm32mp1 clock driver to clock drivers directory
Moves stm32mp15 clock driver to core/drivers/clk and adds configuration switch CFG_STM32MP15_CLK to embed or not the driver. Platf
drivers: clk: move stm32mp1 clock driver to clock drivers directory
Moves stm32mp15 clock driver to core/drivers/clk and adds configuration switch CFG_STM32MP15_CLK to embed or not the driver. Platform stm32mp1 mandates CFG_STM32MP15_CLK=y.
Reviewed-by: Lionel Debieve <lionel.debieve@foss.st.com> Acked-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 551cc4e3 | 03-Dec-2021 |
Etienne Carriere <etienne.carriere@linaro.org> |
plat-stm32mp1: mandate generic clock driver support
Changes stm32mp1 platform to mandate use of the generic clock driver (CFG_DRVIERS_CLK=y). The platform clock driver implementation is updated to r
plat-stm32mp1: mandate generic clock driver support
Changes stm32mp1 platform to mandate use of the generic clock driver (CFG_DRVIERS_CLK=y). The platform clock driver implementation is updated to remove all implementation related to when CFG_DRVIERS_CLK is disabled.
CFG_DRIVERS_CLK_DT must be disabled if there is no embedded DTB for that platform.
Reviewed-by: Lionel Debieve <lionel.debieve@foss.st.com> Acked-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 5709a67c | 30-Oct-2021 |
Etienne Carriere <etienne.carriere@linaro.org> |
plat-stm32mp1: register to clock framework
Changes stm32mp1 clock driver to register clocks in the clk framework upon CFG_DRIVERS_CLK=y. CFG_DRIVERS_CLK=y mandates CFG_EMBED_DTB=y for that platform.
plat-stm32mp1: register to clock framework
Changes stm32mp1 clock driver to register clocks in the clk framework upon CFG_DRIVERS_CLK=y. CFG_DRIVERS_CLK=y mandates CFG_EMBED_DTB=y for that platform.
When CFG_DRIVERS_CLK=y, static array stm32mp1_clk[] holds all registered clock instances, relating to either a clock gate referred in array stm32mp1_clk_gate[] and an always on clock from array stm32mp1_clk_on[].
Defines local helper functions clock_id_to_gate_index() and clock_id_to_always_on_index() to convert generic clock references into a platform local clock identifier that is the index of the target clock in its relative clock references array.
When CFG_DRIVERS_CLK is disabled, stm32mp1 clock legacy functions stm32_clock_*() call local clock driver. When CFG_DRIVERS_CLK=y, they call the generic clock API functions clk_*(). These platform clock legacy functions are preserved since used in platform specific functions implementation.
To optimize unpaged memory footprint, only few clock names are embedded and only upon debug trace level and only required clk_ops operators are linked in an unpaged memory section.
Acked-by: Lionel Debieve <lionel.debieve@foss.st.com> Acked-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 61487fe8 | 14-Jan-2022 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: link: platform can define pager dummy resources
Allows platform to define paged and init dummy resources to allows platform specific resources to be linked in unpaged memory sections without p
core: link: platform can define pager dummy resources
Allows platform to define paged and init dummy resources to allows platform specific resources to be linked in unpaged memory sections without propagating their unpaged constraint to the resources they depend on.
Platform should implement source files link_dummies_paged.c and/or link_dummies_init.c from their platform directory when needed.
Acked-by: Jerome Forissier <jerome@forissier.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| c78b2c66 | 17-Nov-2021 |
Etienne Carriere <etienne.carriere@linaro.org> |
drivers: add reset controller framework
Adds a common reset controller framework rstctrl for interfacing reset controllers exposed by a platform.
Reset controller consumers can act on relate reset
drivers: add reset controller framework
Adds a common reset controller framework rstctrl for interfacing reset controllers exposed by a platform.
Reset controller consumers can act on relate reset level with rstctrl_assert(), rstctrl_deassert() and friends.
Reset controller consumers can claim exclusive access to the reset level woth rstctrl_get_exclusive(), rstctrl_put_exclusive().
Reset controller provider drivers call rstctrl_register_provider() to allow other drivers to get a reset control reference from a devicetree reference. Reset controller driver are identified with type DT_DRIVER_RSTCTRL.
A reset controller provider exposes struct rstctrl instances made of an opaque private reference (a private data pointer or an unsigned integer identifier), an reset controller operators reference and the exclusive claim state.
Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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