1# 1GB and 512MB DDR targets do not locate secure DDR at the same place. 2flavor_dts_file-157A_DK1 = stm32mp157a-dk1.dts 3flavor_dts_file-157C_DK2 = stm32mp157c-dk2.dts 4flavor_dts_file-157C_ED1 = stm32mp157c-ed1.dts 5flavor_dts_file-157C_EV1 = stm32mp157c-ev1.dts 6 7flavorlist-cryp-512M = $(flavor_dts_file-157C_DK2) 8 9flavorlist-no_cryp-512M = $(flavor_dts_file-157A_DK1) 10 11flavorlist-cryp-1G = $(flavor_dts_file-157C_ED1) \ 12 $(flavor_dts_file-157C_EV1) 13 14flavorlist-no_cryp = $(flavorlist-no_cryp-512M) 15 16flavorlist-512M = $(flavorlist-cryp-512M) \ 17 $(flavorlist-no_cryp-512M) 18 19flavorlist-1G = $(flavorlist-cryp-1G) 20 21ifneq ($(PLATFORM_FLAVOR),) 22ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 23$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 24endif 25CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 26endif 27 28ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_cryp)),) 29$(call force,CFG_STM32_CRYP,n) 30endif 31 32include core/arch/arm/cpu/cortex-a7.mk 33 34$(call force,CFG_BOOT_SECONDARY_REQUEST,y) 35$(call force,CFG_DRIVERS_CLK_FIXED,n) 36$(call force,CFG_GIC,y) 37$(call force,CFG_INIT_CNTVOFF,y) 38$(call force,CFG_PSCI_ARM32,y) 39$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 40$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 41$(call force,CFG_SM_PLATFORM_HANDLER,y) 42$(call force,CFG_WITH_SOFTWARE_PRNG,y) 43 44ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),) 45CFG_TZDRAM_START ?= 0xde000000 46CFG_SHMEM_START ?= 0xdfe00000 47CFG_DRAM_SIZE ?= 0x20000000 48endif 49 50CFG_TZSRAM_START ?= 0x2ffc0000 51CFG_TZSRAM_SIZE ?= 0x0003f000 52CFG_STM32MP1_SCMI_SHM_BASE ?= 0x2ffff000 53CFG_STM32MP1_SCMI_SHM_SIZE ?= 0x00001000 54CFG_TZDRAM_START ?= 0xfe000000 55CFG_TZDRAM_SIZE ?= 0x01e00000 56CFG_SHMEM_START ?= 0xffe00000 57CFG_SHMEM_SIZE ?= 0x00200000 58CFG_DRAM_SIZE ?= 0x40000000 59 60CFG_TEE_CORE_NB_CORE ?= 2 61CFG_WITH_PAGER ?= y 62CFG_WITH_LPAE ?= y 63CFG_MMAP_REGIONS ?= 23 64CFG_DTB_MAX_SIZE ?= (256 * 1024) 65 66ifeq ($(CFG_EMBED_DTB_SOURCE_FILE),) 67# Some drivers mandate DT support 68$(call force,CFG_DRIVERS_CLK_DT,n) 69$(call force,CFG_STM32_CRYP,n) 70$(call force,CFG_STM32_GPIO,n) 71$(call force,CFG_STM32_I2C,n) 72$(call force,CFG_STPMIC1,n) 73$(call force,CFG_STM32MP1_SCMI_SIP,n) 74$(call force,CFG_SCMI_PTA,n) 75endif 76 77CFG_STM32_BSEC ?= y 78CFG_STM32_CRYP ?= y 79CFG_STM32_ETZPC ?= y 80CFG_STM32_GPIO ?= y 81CFG_STM32_I2C ?= y 82CFG_STM32_RNG ?= y 83CFG_STM32_UART ?= y 84CFG_STPMIC1 ?= y 85CFG_TZC400 ?= y 86 87ifeq ($(CFG_STPMIC1),y) 88$(call force,CFG_STM32_I2C,y) 89$(call force,CFG_STM32_GPIO,y) 90endif 91 92# if any crypto driver is enabled, enable the crypto-framework layer 93ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP),y) 94$(call force,CFG_STM32_CRYPTO_DRIVER,y) 95endif 96 97# Platform specific configuration 98CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y 99 100# SiP/OEM service for non-secure world 101CFG_STM32_BSEC_SIP ?= y 102CFG_STM32MP1_SCMI_SIP ?= y 103ifeq ($(CFG_STM32MP1_SCMI_SIP),y) 104$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_STM32MP1_SCMI_SIP) 105$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y,Mandated by CFG_STM32MP1_SCMI_SIP) 106endif 107 108# Default enable SCMI PTA support 109CFG_SCMI_PTA ?= y 110ifeq ($(CFG_SCMI_PTA),y) 111$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_SCMI_PTA) 112$(call force,CFG_SCMI_MSG_SMT_THREAD_ENTRY,y,Mandated by CFG_SCMI_PTA) 113endif 114 115CFG_SCMI_MSG_DRIVERS ?= n 116ifeq ($(CFG_SCMI_MSG_DRIVERS),y) 117$(call force,CFG_SCMI_MSG_CLOCK,y) 118$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y) 119$(call force,CFG_SCMI_MSG_SMT,y) 120$(call force,CFG_SCMI_MSG_VOLTAGE_DOMAIN,y) 121endif 122 123# Default enable some test facitilites 124CFG_TEE_CORE_EMBED_INTERNAL_TESTS ?= y 125CFG_WITH_STATS ?= y 126 127# Default disable some support for pager memory size constraint 128ifeq ($(CFG_WITH_PAGER),y) 129CFG_TEE_CORE_DEBUG ?= n 130CFG_UNWIND ?= n 131CFG_LOCKDEP ?= n 132CFG_CORE_ASLR ?= n 133CFG_TA_BGET_TEST ?= n 134endif 135 136# Non-secure UART and GPIO/pinctrl for the output console 137CFG_WITH_NSEC_GPIOS ?= y 138CFG_WITH_NSEC_UARTS ?= y 139# UART instance used for early console (0 disables early console) 140CFG_STM32_EARLY_CONSOLE_UART ?= 4 141