core: mm: move mobj_dyn_shm.c to mm

To enable RISC-V platforms to utilize dynamic shared memory,
relocate the non-architecture-specific mobj_dyn_shm.c to the
mm directory.

Signed-off-by: Alvin Chan

core: mm: move mobj_dyn_shm.c to mm

To enable RISC-V platforms to utilize dynamic shared memory,
relocate the non-architecture-specific mobj_dyn_shm.c to the
mm directory.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: pm: sam: improve the access of variables in "at91_pm_data"

Flush the TLB before accessing variables in "at91_pm_data".
Preload the variables before using.

Signed-off-by: Tony Han <tony.han

drivers: pm: sam: improve the access of variables in "at91_pm_data"

Flush the TLB before accessing variables in "at91_pm_data".
Preload the variables before using.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: pm: sam: add code for enable/disable sama7g5 DRAM self-refresh mode

Add the header file "sama7-ddr.h" for sama7g5 DRAM controller.
Add 2 macros for enable and disable sama7g5 DRAM self-refr

drivers: pm: sam: add code for enable/disable sama7g5 DRAM self-refresh mode

Add the header file "sama7-ddr.h" for sama7g5 DRAM controller.
Add 2 macros for enable and disable sama7g5 DRAM self-refresh mode.
Enable self-refresh mode before entering the low-power modes and
disable it after exiting the low-power modes.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: pm: sam: add code for the phy of sama7g5 dram controller

Add and initilate the variable for the start address of sama7g5
dram controller phy.

Signed-off-by: Tony Han <tony.han@microchip.co

drivers: pm: sam: add code for the phy of sama7g5 dram controller

Add and initilate the variable for the start address of sama7g5
dram controller phy.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: kernel: Remove unused ta_time_offs in user_ta_ctx

It seems that "ta_time_offs" member is unused now. Thus, remove it from
user_ta_ctx structure.

Signed-off-by: Alvin Chang <alvinga@andestech.

core: kernel: Remove unused ta_time_offs in user_ta_ctx

It seems that "ta_time_offs" member is unused now. Thus, remove it from
user_ta_ctx structure.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: se05x: Add SCP03 keys for SE052F2

Add SCP03 default keys for SE052F2 to support OEFID 0xB501

Variant Identifier (OEF ID): B501
12NC : 9354 551 73118
Type Numb

drivers: crypto: se05x: Add SCP03 keys for SE052F2

Add SCP03 default keys for SE052F2 to support OEFID 0xB501

Variant Identifier (OEF ID): B501
12NC : 9354 551 73118
Type Number : SE052F2HN2/Z019H
Orderable Part Number : SE052F2HN2/Z019HJ

Signed-off-by: Chandni Sabharwal <chandni.sabharwal@gallagher.com>
Acked-by: Jorge Ramirez-Ortiz <jorge@foundries.io>

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drivers: pm: sam: add code for sama7g5 LPM (Low-power Mode) pad

Set LPM pad high/low through SHDW_CR register.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklan

drivers: pm: sam: add code for sama7g5 LPM (Low-power Mode) pad

Set LPM pad high/low through SHDW_CR register.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: pm: sam: add code for save/restore sama7g5 MCK1..4 settings

Add 2 macros for save and restore sama7g5 MCK1..4 settings.
Save MCK1..4 settings before entering the low-power modes and restore

drivers: pm: sam: add code for save/restore sama7g5 MCK1..4 settings

Add 2 macros for save and restore sama7g5 MCK1..4 settings.
Save MCK1..4 settings before entering the low-power modes and restore
the settings after exiting the low-power modes.
During the low-power mode MCK1..4 use CSS=MAINCK and DIV=1.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: pm: sam: add support for checking sama7g5 MCK1..4 ready

sama5d2 has only MCK0 clock.
sama7g5 has MCK0,1,..., MCK4 clocks.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wi

drivers: pm: sam: add support for checking sama7g5 MCK1..4 ready

sama5d2 has only MCK0 clock.
sama7g5 has MCK0,1,..., MCK4 clocks.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: pm: sam: update PLLA enable/disable macros for sama7g5

Update macro "at91_plla_disable" and "at91_plla_enable" for sama7g5 PLLA.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by:

drivers: pm: sam: update PLLA enable/disable macros for sama7g5

Update macro "at91_plla_disable" and "at91_plla_enable" for sama7g5 PLLA.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-hikey: make DRAM0_SIZE and DRAM0_SIZE_NSEC configurable

DRAM0_SIZE is now defined as CFG_TZDRAM_START, allowing
for dynamic configuration.

DRAM0_SIZE_NSEC is modified to calculate the size rel

plat-hikey: make DRAM0_SIZE and DRAM0_SIZE_NSEC configurable

DRAM0_SIZE is now defined as CFG_TZDRAM_START, allowing
for dynamic configuration.

DRAM0_SIZE_NSEC is modified to calculate the size relative
to DRAM0_BASE.

Signed-off-by: Wen Bin <a1231512a@163.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ltc: Fix building with mbedtls

Fix building OP-TEE with:

make PLATFORM=vexpress \
PLATFORM_FLAVOR=juno \
CFG_CRYPTOLIB_NAME=mbedtls \
CFG_CRYPTOLIB_DIR=lib/libmbedtls
...
core/

core: ltc: Fix building with mbedtls

Fix building OP-TEE with:

make PLATFORM=vexpress \
PLATFORM_FLAVOR=juno \
CFG_CRYPTOLIB_NAME=mbedtls \
CFG_CRYPTOLIB_DIR=lib/libmbedtls
...
core/lib/libtomcrypt/aes_accel.c: In function ‘aes_ctr_encrypt_nblocks’:
core/lib/libtomcrypt/aes_accel.c:182:21: error: ‘CTR_COUNTER_LITTLE_ENDIAN’ undeclared (first use in this function)
182 | if (mode == CTR_COUNTER_LITTLE_ENDIAN) {

Signed-off-by: Jacob Kroon <jacobkr@axis.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: firewall: add firewall framework

Add a generic firewall controller framework. The goal of this framework
is to offer access control and configuration APIs, that are implemented
in the firewall

core: firewall: add firewall framework

Add a generic firewall controller framework. The goal of this framework
is to offer access control and configuration APIs, that are implemented
in the firewall controllers drivers, to the firewall consumers. This
framework requires an embedded device tree.

A firewall controller is an access controller [1]. It should register
itself as a provider to the framework. Firewall controllers have the
possibility to populate their bus according to defined firewall accesses
defined in the "access-controllers" property in each of the device's
node.

Any device that consumes one or more firewall should refer it/them in
their "access-controllers" property. Arguments can be passed along with
the phandle of the firewall controller(s).

Link: https://patchwork.kernel.org/project/linux-media/patch/20240105130404.301172-2-gatien.chevallier@foss.st.com/ [1]
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: clk: sam: add definition for sama7g5 PMC_CPU_CKR register

The offset of "PMC CPU Clock Register" for sama7g5 is different from
the one for sama5d2.

Signed-off-by: Tony Han <tony.han@microc

drivers: clk: sam: add definition for sama7g5 PMC_CPU_CKR register

The offset of "PMC CPU Clock Register" for sama7g5 is different from
the one for sama5d2.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: pm: sam: update the count of PCK clock for sama7g5

Add definition "AT91_PMC_PCK_COUNT", in sama7g5 there're 8 PCK clocks
and for sama5d2 there're 4 PCK clocks.

Signed-off-by: Tony Han <ton

drivers: pm: sam: update the count of PCK clock for sama7g5

Add definition "AT91_PMC_PCK_COUNT", in sama7g5 there're 8 PCK clocks
and for sama5d2 there're 4 PCK clocks.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: pm: sam: configure the wakeup sources for sama7g5

Rename the names of functions for adding the configuration of sama7g5
wakeup sources.
Add and configure the wakeup sources for sama7g5.

Si

drivers: pm: sam: configure the wakeup sources for sama7g5

Rename the names of functions for adding the configuration of sama7g5
wakeup sources.
Add and configure the wakeup sources for sama7g5.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: pm: sam: change memory area type to coherent for mapping SRAM

Mapping with memory area type MEM_AREA_TEE_RAM would enable cacheable
attribute, it might cause abort in same cases. Here chang

drivers: pm: sam: change memory area type to coherent for mapping SRAM

Mapping with memory area type MEM_AREA_TEE_RAM would enable cacheable
attribute, it might cause abort in same cases. Here change the memory
area type to MEM_AREA_TEE_COHERENT to map SRAM with non-cacheable
attribute to avoid the aborts in the low-power process.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: pm: sam: enable running code for low-power out of SRAM

Configure regions with write permission with not forced to
XN (Execute-never) attribute when implementation includes
the Virtualizatio

drivers: pm: sam: enable running code for low-power out of SRAM

Configure regions with write permission with not forced to
XN (Execute-never) attribute when implementation includes
the Virtualization Extensions.

Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: plat-mediatek: fix enforcement of SWRNG configuration on MT7988

Small fix: $(call force,CFG_WITH_SOFTWARE_PRNG,Y) should be lowercase
'y' so that the conditional check in core/crypto/sub.mk in

core: plat-mediatek: fix enforcement of SWRNG configuration on MT7988

Small fix: $(call force,CFG_WITH_SOFTWARE_PRNG,Y) should be lowercase
'y' so that the conditional check in core/crypto/sub.mk includes
the correct source file rng_fortuna.c instead of rng_hw.c, which is
unimplemented for this platform and causes build failure.

Fixes: 58dbe3dff530 ("plat-mediatek: add support for MT7988 SoC")
Signed-off-by: Charles Herz <herzc@umich.edu>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: interrupts: fix inline comment typo on DT property name

Fix DT property named "interrupts-extended", mistakenly named
"extended-interrupts" in interrupt API function inline description
comment

core: interrupts: fix inline comment typo on DT property name

Fix DT property named "interrupts-extended", mistakenly named
"extended-interrupts" in interrupt API function inline description
comments.

Fixes: 33a0c8350ac1 ("core: interrupt: registering interrupt providers")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: kernel: use explicit unsigned int type in condvar

Replace unsigned with unsigned int as type of struct condvar::spin_lock.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Revie

core: kernel: use explicit unsigned int type in condvar

Replace unsigned with unsigned int as type of struct condvar::spin_lock.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: kernel: fix include order in spinlock.h

Fix order of #include directives in spinlock.h.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.fo

core: kernel: fix include order in spinlock.h

Fix order of #include directives in spinlock.h.

Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: hisilicon: Update header files location

The header files in core/drivers/crypto/hisilicon/includes
are only used by the source files in core/drivers/crypto/hisilicon,
so move the he

drivers: crypto: hisilicon: Update header files location

The header files in core/drivers/crypto/hisilicon/includes
are only used by the source files in core/drivers/crypto/hisilicon,
so move the header file from core/drivers/crypto/hisilicon/include
to core/drivers/crypto/hisilicon/.

Signed-off-by: leisen <leisen1@huawei.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: hisilicon:Add HASH and HMAC algorithm

Add HASH and HMAC algorithm by SEC, and support SHA1,
SHA224, SHA256, SHA384, SHA512, MD5, SM3, and HMAC
algorithms based on these algorithms.

drivers: crypto: hisilicon:Add HASH and HMAC algorithm

Add HASH and HMAC algorithm by SEC, and support SHA1,
SHA224, SHA256, SHA384, SHA512, MD5, SM3, and HMAC
algorithms based on these algorithms.

Signed-off-by: leisen <leisen1@huawei.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: remove assertions on device handlers

Remove assertions added by the commit referred below. They are useless
since the handlers are registered only if the related device (stm32_cryp

drivers: crypto: remove assertions on device handlers

Remove assertions added by the commit referred below. They are useless
since the handlers are registered only if the related device (stm32_cryp
or stm32_saes) has its driver successfully probed. These assertion also
prevent enabling both CFG_STM32_SAES and CFG_STM32_CRYP for a platform
which is a valid configuration for when we rely on the DT to state
which of both is enabled.

Fixes: 03de2c7bb316 ("drivers: crypto: stm32_saes: fallback to software on 192bit AES keys")
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>

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