| 28c10f9e | 17-Jun-2024 |
Gabriel Fernandez <gabriel.fernandez@foss.st.com> |
clk: stm32mp25: Introduce STM32MP25 clocks platform
This driver is based on clk-stm32-core API to manage STM32 gates, dividers and muxes.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st
clk: stm32mp25: Introduce STM32MP25 clocks platform
This driver is based on clk-stm32-core API to manage STM32 gates, dividers and muxes.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 0de0b5e2 | 16-Apr-2024 |
Gabriel Fernandez <gabriel.fernandez@foss.st.com> |
dt-bindings: add the STM32MP2 clock and reset bindings
Add the associated bindings for device tree and drivers.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Acked-by: Etienne Ca
dt-bindings: add the STM32MP2 clock and reset bindings
Add the associated bindings for device tree and drivers.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 11ece294 | 10-Dec-2021 |
Gabriel Fernandez <gabriel.fernandez@foss.st.com> |
plat-stm32mp2: add rcc helper function
Add dedicate include file for RCC to add helper function.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Etienne Carriere <etie
plat-stm32mp2: add rcc helper function
Add dedicate include file for RCC to add helper function.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 9b87942a | 03-Jun-2024 |
Gabriel Fernandez <gabriel.fernandez@foss.st.com> |
plat-stm32mp2: sysconfig: add Safe Reset functionality
Add possibility to manage safely master IP reset. This is managed in SYSCFG safe reset control register (SYSCFG_SAFERSTCR)
Signed-off-by: Gabr
plat-stm32mp2: sysconfig: add Safe Reset functionality
Add possibility to manage safely master IP reset. This is managed in SYSCFG safe reset control register (SYSCFG_SAFERSTCR)
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| ef7785ad | 17-Mar-2022 |
Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> |
plat-stm32mp2: add stm32mp25 sysconfig driver
Driver to manage system configuration (sysconf) registers the sysconf are identified by an ID to be able to be adapted for DT.
Signed-off-by: Arnaud Po
plat-stm32mp2: add stm32mp25 sysconfig driver
Driver to manage system configuration (sysconf) registers the sysconf are identified by an ID to be able to be adapted for DT.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| e2d9f64a | 19-Jun-2024 |
Gabriel Fernandez <gabriel.fernandez@foss.st.com> |
plat-stm32mp2: conf: enable shared io driver
Default enable shared io driver for platform stm32mp2.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Etienne Carriere <e
plat-stm32mp2: conf: enable shared io driver
Default enable shared io driver for platform stm32mp2.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| f15052a2 | 21-Jun-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: mm: add CFG_PGT_CACHE_ENTRIES
Add CFG_PGT_CACHE_ENTRIES to allow platforms to customize the page table cache size. This is needed for example when a platform is to support very large TAs of se
core: mm: add CFG_PGT_CACHE_ENTRIES
Add CFG_PGT_CACHE_ENTRIES to allow platforms to customize the page table cache size. This is needed for example when a platform is to support very large TAs of several dozen of Mbytes of private memory (code/data).
Move PGT_CACHE_SIZE macro definition from pgt_cache.h to pgt_cache.c since it is used only in that source file.
By the way, fix pgt_cache.h layout to have header files includes first followed by macro definitions.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 86ee543b | 07-Mar-2024 |
Sami Tolvanen <samitolvanen@google.com> |
core: pass TEE_ATTR_RSA_OAEP_MGF_HASH to RSA-OAEP implementations
OP-TEE currently doesn't support using a different hash for MGF1 with RSA-OAEP. However, this is required for AOSP compatibility (e.
core: pass TEE_ATTR_RSA_OAEP_MGF_HASH to RSA-OAEP implementations
OP-TEE currently doesn't support using a different hash for MGF1 with RSA-OAEP. However, this is required for AOSP compatibility (e.g. in EncryptionOperationsTest.RsaOaepWithMGFDigestSuccess [1]).
Pass the MGF1 attribute to crypto implementations. Note that only libtomcrypt supports this feature at the moment, so other implementations will either fail or fall back to libtomcrypt when passed a different MGF1 hash.
Link: https://android.googlesource.com/platform/hardware/interfaces/+/refs/heads/main/security/keymint/aidl/vts/functional/KeyMintTest.cpp#5552 [1] Signed-off-by: Sami Tolvanen <samitolvanen@google.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| b432ec14 | 13-Jun-2024 |
Tony Han <tony.han@microchip.com> |
plat-sam: register CPU OPP clock for SCMI usage
Add the definitinon for 'AT91_SCMI_CLK_CPU_OPP'. When the CPU OPP clock is available, add it to SCMI clock list.
Signed-off-by: Tony Han <tony.han@mi
plat-sam: register CPU OPP clock for SCMI usage
Add the definitinon for 'AT91_SCMI_CLK_CPU_OPP'. When the CPU OPP clock is available, add it to SCMI clock list.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 265f4754 | 13-Jun-2024 |
Tony Han <tony.han@microchip.com> |
drivers: clk: sam: add the implement of CPU OPP clock
Register CPU OPP clock with the following operations: - set_rate: call the operation of its parent - get_rates_array: return the rates got fro
drivers: clk: sam: add the implement of CPU OPP clock
Register CPU OPP clock with the following operations: - set_rate: call the operation of its parent - get_rates_array: return the rates got from DT. Skip CPU OPP clock register when OPP is not supported.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| f496f2c4 | 13-Jun-2024 |
Tony Han <tony.han@microchip.com> |
plat-sam: prepare for CPU OPP (Operating Performance Points) support
Initialize clock rates array by parsing the device tree.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Etienne Carr
plat-sam: prepare for CPU OPP (Operating Performance Points) support
Initialize clock rates array by parsing the device tree.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 932a3e11 | 13-May-2024 |
Tony Han <tony.han@microchip.com> |
dts: at91: add assigned-clock settings for sama7g5 qspi0
Assign QSPI0's clock to SYSPLL GCK 133MHz.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Etienne Carriere <etienne.carriere@fos
dts: at91: add assigned-clock settings for sama7g5 qspi0
Assign QSPI0's clock to SYSPLL GCK 133MHz.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 1677a7fb | 18-Jun-2024 |
Gavin Liu <gavin.liu@mediatek.com> |
plat-mediatek: add support to extend MAX_XLAT_TABLE
When using the reserved virtual memory space, it is necessary to increase MAX_XLAT_TABLE based on its size.
Signed-off-by: Gavin Liu <gavin.liu@m
plat-mediatek: add support to extend MAX_XLAT_TABLE
When using the reserved virtual memory space, it is necessary to increase MAX_XLAT_TABLE based on its size.
Signed-off-by: Gavin Liu <gavin.liu@mediatek.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 7ae15736 | 18-Jun-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: ree_fs: fix dirfile handle refcount
The counter ree_fs_dirh_refcount is used to determine when ree_fs_dirh should be free, not as a guarantee that ree_fs_dirh is still valid. This wasn't the a
core: ree_fs: fix dirfile handle refcount
The counter ree_fs_dirh_refcount is used to determine when ree_fs_dirh should be free, not as a guarantee that ree_fs_dirh is still valid. This wasn't the assumption in ree_fs_readdir_rpc(), ree_fs_closedir_rpc(), and ree_fs_opendir_rpc(). So fix that by using get_dirh() in ree_fs_readdir_rpc as needed.
Reported-by: Gavin Liu <gavin.liu@mediatek.com> Closes: https://github.com/OP-TEE/optee_os/issues/6895 Fixes: ace6039fd434 ("core: REE_FS: refcount dirfile handle") Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 47d5e6cb | 14-Jun-2024 |
Jerome Forissier <jerome.forissier@linaro.org> |
libutils, zlib: fix Clang warnings
Clang 18.1.6 reports the following warnings:
CC out/arm/ldelf-lib/libutils/isoc/bget_malloc.o In file included from lib/libutils/isoc/bget_malloc.c:127:
libutils, zlib: fix Clang warnings
Clang 18.1.6 reports the following warnings:
CC out/arm/ldelf-lib/libutils/isoc/bget_malloc.o In file included from lib/libutils/isoc/bget_malloc.c:127: lib/libutils/isoc/bget.c:607:7: warning: a function definition without a prototype is deprecated in all versions of C and is not supported in C23 [-Wdeprecated-non-prototype] 607 | void *bget(requested_align, hdr_size, requested_size, poolset) | ^
And same with lib/zlib/{adler32.c,inffast.c,inflate.c,zutil.c}.
In addition, zutil.c causes:
CC out/arm/core/lib/zlib/zutil.o core/lib/zlib/zutil.c:28:33: warning: a function declaration without a prototype is deprecated in all versions of C [-Wstrict-prototypes] 28 | const char * ZEXPORT zlibVersion() | ^ | void
Add -Wno-deprecated-non-prototype to libutils' bget_malloc.c to silence the first series, and simply remove -Wstrict-prototypes (added by default by mk/compile.mk) when building zlib.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Joakim Bech <joakim.bech@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| dc9fd53b | 14-Jun-2024 |
Jerome Forissier <jerome.forissier@linaro.org> |
arm64.h: fix compile error with Clang
Clang 18.1.6 fails to compile OP-TEE OS with the following error:
CC out/arm/core/arch/arm/kernel/vfp.o In file included from core/arch/arm/kernel/vfp
arm64.h: fix compile error with Clang
Clang 18.1.6 fails to compile OP-TEE OS with the following error:
CC out/arm/core/arch/arm/kernel/vfp.o In file included from core/arch/arm/kernel/vfp.c:6: In file included from core/arch/arm/include/arm.h:137: core/arch/arm/include/arm64.h:455:1: error: expected readable system register 455 | DEFINE_U32_REG_READWRITE_FUNCS(fpcr) | ^ core/arch/arm/include/arm64.h:436:3: note: expanded from macro 'DEFINE_U32_REG_READWRITE_FUNCS' 436 | DEFINE_U32_REG_READ_FUNC(reg) \ | ^ core/arch/arm/include/arm64.h:430:3: note: expanded from macro 'DEFINE_U32_REG_READ_FUNC' 430 | DEFINE_REG_READ_FUNC_(reg, uint32_t, reg) | ^ core/arch/arm/include/arm64.h:417:15: note: expanded from macro 'DEFINE_REG_READ_FUNC_' 417 | asm volatile("mrs %0, " #asmreg : "=r" (val64)); \ | ^ <inline asm>:1:10: note: instantiated into assembly here 1 | mrs x8, fpcr | ^
...and similar ones for fpcr write, as well as fpsr read and write.
Clang 12.0.0 does not have any problem with this code which makes me think that it's a Clang/LLVM issue.
Work around the problem by using the coded system register identifiers S3_3_c4_c4_0 and S3_3_c4_c4_1 instead of fpcr and fpsr, respectively. The values 3-3-4-4-0 and 3-3-4-4-1 are taken from the Arm ARM sections C.5.2.8 and C.5.2.9.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Joakim Bech <joakim.bech@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 956c2d50 | 12-Jun-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: fix race condition on TA/PTA/StMM context loading
Fix race condition on creation of a context for single instance TAs, PTAs or StMM application. Such race condition could occur and lead to dup
core: fix race condition on TA/PTA/StMM context loading
Fix race condition on creation of a context for single instance TAs, PTAs or StMM application. Such race condition could occur and lead to duplicated contexts if connected close enough that they are created after tee_ta_init_session() calls tee_ta_init_session_with_context() and before the context are added in the centralized context list.
This is realized by keeping tee_ta_mutex held while tee_ctxes list is looked up for matching a context or a new context is added into that list with its .is_initializing field activated. For that purpose user TA and StMM application initialization function are split in 2 functions, the 2nd one used to finalizes the context creation started in the 1st function.
By the way, add inline description comments and fix indentation issues in uaer_ta.h and remove the inline comment in pseudo_ta.c that refers to TA loading whereas the function relates to PTA contexts creation.
Closes: https://github.com/OP-TEE/optee_os/issues/6801 Suggested-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 30730d67 | 13-Jun-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: add mutex_is_locked() helper function
Add mutex_is_locked() helper function to return whether a mutex is locked or not. This helper function must be use with care since it does not guarantee t
core: add mutex_is_locked() helper function
Add mutex_is_locked() helper function to return whether a mutex is locked or not. This helper function must be use with care since it does not guarantee that the mutex is held by the executing thread.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| fee55718 | 14-May-2024 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: make is_initializing field a generic service context
Replace fields is_initializing from struct user_mode_ctx and struct stmm_ctx with a common new field is_initialing in generic struct tee_ta
core: make is_initializing field a generic service context
Replace fields is_initializing from struct user_mode_ctx and struct stmm_ctx with a common new field is_initialing in generic struct tee_ta_ctx so that it can be used in generic context loading functions for contexts which initialization is done with tee_ta_mutex released.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| eaee88fb | 30-May-2024 |
Harsimran Singh Tungal <harsimransingh.tungal@arm.com> |
core: plat-corstone1000: Remove MMCOMM buffer address
Remove MMCOMM buffer address and mapping, as it is not being used anymore
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
core: plat-corstone1000: Remove MMCOMM buffer address
Remove MMCOMM buffer address and mapping, as it is not being used anymore
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Emekcan Aras <emekcan.aras@arm.com>
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| fdf696b7 | 12-Jun-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: rename tee_mm_shm to core_virt_shm_pool
Rename tee_mm_shm to core_virt_shm_pool to make it clear that it handles virtual memory allocations for shared memory.
Signed-off-by: Jens Wiklander <j
core: rename tee_mm_shm to core_virt_shm_pool
Rename tee_mm_shm to core_virt_shm_pool to make it clear that it handles virtual memory allocations for shared memory.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 9b0ee59d | 12-Jun-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: rename tee_mm_vcore to core_virt_mem_pool
Rename tee_mm_vcore to core_virt_mem_pool to make it clear that it handles virtual memory allocations.
Signed-off-by: Jens Wiklander <jens.wiklander@
core: rename tee_mm_vcore to core_virt_mem_pool
Rename tee_mm_vcore to core_virt_mem_pool to make it clear that it handles virtual memory allocations.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 99e1ad26 | 12-Jun-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: move tee_mm_{sec_ddr,vcore,shm}
Move tee_mm_sec_ddr, tee_mm_vcore, and tee_mm_shm into core/mm/core_mmu.c.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Foriss
core: move tee_mm_{sec_ddr,vcore,shm}
Move tee_mm_sec_ddr, tee_mm_vcore, and tee_mm_shm into core/mm/core_mmu.c.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| c5e3e79f | 10-Jun-2024 |
Sungbae Yoo <sungbaey@nvidia.com> |
core: kernel: change DT getters to use manifest DT
This change get_dt() and get_secure_dt() to use manifest DT as an alternative if there is no embedded DT or external DT.
Signed-off-by: Sungbae Yo
core: kernel: change DT getters to use manifest DT
This change get_dt() and get_secure_dt() to use manifest DT as an alternative if there is no embedded DT or external DT.
Signed-off-by: Sungbae Yoo <sungbaey@nvidia.com> Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 4bc2c5f0 | 10-Jun-2024 |
Sungbae Yoo <sungbaey@nvidia.com> |
core: kernel: move manifest DT functions to dt.c
This moves functions to handle manifest DT, used as a SP (secure partition) manifest via FF-A interface, to core/kernel/dt.c and their definitions to
core: kernel: move manifest DT functions to dt.c
This moves functions to handle manifest DT, used as a SP (secure partition) manifest via FF-A interface, to core/kernel/dt.c and their definitions to dt.h. manifest DT is dependent with CORE_FFA that depends on CFG_DT, as the same as dt.c.
Signed-off-by: Sungbae Yoo <sungbaey@nvidia.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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