plat-stm: rename memory definition name

Rename following memory area definition name, according
to the one used in vexpress:
CFG_DDR_START into DRAM0_BASE
CFG_DDR_SIZE

plat-stm: rename memory definition name

Rename following memory area definition name, according
to the one used in vexpress:
CFG_DDR_START into DRAM0_BASE
CFG_DDR_SIZE into DRAM0_SIZE
CFG_DDR1_START into DRAM1_BASE
CFG_DDR1_SIZE into DRAM1_SIZE
CFG_DDR_ARM_ARMTZ_START into CFG_SHMEM_START
CFG_DDR_ARM_ARMTZ_SIZE into CFG_SHMEM_SIZE
CFG_DDR_ARMTZ_ONLY_START into TZDRAM_BASE
CFG_DDR_ARMTZ_ONLY_SIZE into TZDRAM_SIZE

Signed-off-by: Pascal Brand <pascal.brand@st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm: make stacks cache line aligned

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.or

plat-stm: make stacks cache line aligned

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)

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arm32: remove memmap_notinit bookkeeping

Removes the bookkeeping of whether memory map has been initialized or
not using the memmap_notinit variable. Memory map is always initialized
before any core

arm32: remove memmap_notinit bookkeeping

Removes the bookkeeping of whether memory map has been initialized or
not using the memmap_notinit variable. Memory map is always initialized
before any core_va2pa() or core_pa2va() is performed so the bookkeeping
doesn't do much good.

The variable was updated with caches disabled while other CPUs might have
caches enabled. This can result in unexpected problems.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno)
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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plat-vexpress: make stacks cache line aligned

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

arm32: paging of TEE Core optionally enabled

plat-vexpress-*:
* Optionally enable paging with CFG_WITH_PAGER=y
* Uses fake SRAM when paging is enabled
* Supports partitioning OP-TEE binary in unpage

arm32: paging of TEE Core optionally enabled

plat-vexpress-*:
* Optionally enable paging with CFG_WITH_PAGER=y
* Uses fake SRAM when paging is enabled
* Supports partitioning OP-TEE binary in unpaged, init and pagable areas

plat-stm:
* Displays an error message if compiled with CFG_WITH_PAGER=y

arm32:
* Replaces legacy paging support with new paging support
* Removes unused tee_pager_unpg.c

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP, Juno)
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform - Check the code without the pager is not broken).

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plat-vexpress: linking supports pagable tee.bin

* Adds scripts to create a pagable tee.bin
* Updates link script and link.mk to support pagable tee.bin
* Binary format of tee.bin is changed from a r

plat-vexpress: linking supports pagable tee.bin

* Adds scripts to create a pagable tee.bin
* Updates link script and link.mk to support pagable tee.bin
* Binary format of tee.bin is changed from a raw format to a header
followed by the binary data as described by the header. This requires
updates in ARM-TF OP-TEE Dispatcher and QEMU virt bios.

fvp:
* Changes OP-TEE load address to start of TZDRAM_BASE

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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plat-vexpress: Clean D-cache on reset_primary exit

Cleans and invalidates D-cache when primary CPU has initialized
and is ready to exit to normal world.

Signed-off-by: Jens Wiklander <jens.wiklande

plat-vexpress: Clean D-cache on reset_primary exit

Cleans and invalidates D-cache when primary CPU has initialized
and is ready to exit to normal world.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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arm32: clear junk in UL1 table

Clears junk in UL1 translation table when setting mapping for a TA in
tee_mmu_set_ctx().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal

arm32: clear junk in UL1 table

Clears junk in UL1 translation table when setting mapping for a TA in
tee_mmu_set_ctx().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU virt)

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provide hash_sha256_check()

Adds hash_sha256_check() to the tee_crypt_provider interface to be
used by pager and early initialization code where the complete crypto
library might not be available.

provide hash_sha256_check()

Adds hash_sha256_check() to the tee_crypt_provider interface to be
used by pager and early initialization code where the complete crypto
library might not be available.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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plat-stm: separate sections

Puts functions and data into separate sections

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: P

plat-stm: separate sections

Puts functions and data into separate sections

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)

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plat-vexpress: separate sections

Puts functions and data into separate sections

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU

plat-vexpress: separate sections

Puts functions and data into separate sections

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU virt and FVP)
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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arm32: assembly routines in separate sections

Moves some assembly routines into separate sections. This helps the garbage
collecting with the linker when separating what's must be unpaged from the
r

arm32: assembly routines in separate sections

Moves some assembly routines into separate sections. This helps the garbage
collecting with the linker when separating what's must be unpaged from the
rest of the code. The garbage collector in the linker works on dependencies
between sections.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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tee_mm: remove legacy TEE_MM_POOL_PAGED define

Removes the legacy TEE_MM_POOL_PAGED define and unsused code
associated with it.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by

tee_mm: remove legacy TEE_MM_POOL_PAGED define

Removes the legacy TEE_MM_POOL_PAGED define and unsused code
associated with it.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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plat-vexpress: reorganize boot for paging

Reorganizes the boot functions to keep primary and secondary boot path
more separated as a preparation for the pager.

Signed-off-by: Jens Wiklander <jens.w

plat-vexpress: reorganize boot for paging

Reorganizes the boot functions to keep primary and secondary boot path
more separated as a preparation for the pager.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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arm32: move call to teecore_init_ta_ram()

Moves call to teecore_init_ta_ram() from init_teecore() to be called
directly from platform initialization routines. It's needed later when
the pager alloc

arm32: move call to teecore_init_ta_ram()

Moves call to teecore_init_ta_ram() from init_teecore() to be called
directly from platform initialization routines. It's needed later when
the pager allocates secure DDR to store that backing pages. We don't want
to call init_teecore() until the pager is fully initialized because
init_teecore() pulls in many dependencies.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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plat-vexpress: clean memory configuration

* Cleans the memory configuration for plat-vexpress to make it easier
to add fake and real SRAM.
* Uses common functions to check if a buffer intersects o

plat-vexpress: clean memory configuration

* Cleans the memory configuration for plat-vexpress to make it easier
to add fake and real SRAM.
* Uses common functions to check if a buffer intersects or is inside
a memory area
* Increases number of cores from 4 to 8 for FVP flavor to support Base
model better.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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arm32: make all TLB invalidations inner sharable

* Makes all TLB invalidations inner sharable
* Removes deprecated TLB invalidations

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Review

arm32: make all TLB invalidations inner sharable

* Makes all TLB invalidations inner sharable
* Removes deprecated TLB invalidations

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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arm32: split and enhance core_init_mmu()

* Splits core_init_mmu() into two functions, core_init_mmu_tables() called
by primary CPU to create the translation tables and core_init_mmu_regs()
calle

arm32: split and enhance core_init_mmu()

* Splits core_init_mmu() into two functions, core_init_mmu_tables() called
by primary CPU to create the translation tables and core_init_mmu_regs()
called by each CPU to initialize MMU register settings.
* Adds option to map certain areas in a level 2 translation table instead
of only level 1 mapping. Allocation of the level 2 translation tables
is implemented in platform specific code, a weak function is provided
in case the platform doesn't implement/need the function.
* Adds L2 translation table for STM and Vexpress.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU virt platform)

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arm32: add thread_init_per_cpu()

Adds a thread_init_per_cpu() function that should be called instead of
thread_init_handlers() by the secondary CPUs. The primary CPU should first
call thread_init_ha

arm32: add thread_init_per_cpu()

Adds a thread_init_per_cpu() function that should be called instead of
thread_init_handlers() by the secondary CPUs. The primary CPU should first
call thread_init_handlers() and then thread_init_per_cpu().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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merge tee_pager*.c and tee_pager*.h files

* Merges tee_pager_unpg.c and tee_pager.c into tee_pager.c
* Merges tee_pager_unpg.h and tee_pager.h into tee_pager.h
* Removes some legacy dummy macros
* R

merge tee_pager*.c and tee_pager*.h files

* Merges tee_pager_unpg.c and tee_pager.c into tee_pager.c
* Merges tee_pager_unpg.h and tee_pager.h into tee_pager.h
* Removes some legacy dummy macros
* Replaces some while(1) with panic()

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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libtomcrypt: the len parameter of hash.final() is the max size

To be consistent with the behavior of crypto_ops.mac.final(), do not fail if
the length passed to crypto_ops.hash.final() is larger tha

libtomcrypt: the len parameter of hash.final() is the max size

To be consistent with the behavior of crypto_ops.mac.final(), do not fail if
the length passed to crypto_ops.hash.final() is larger than the hash size.

Also, use TEE_MAX_HASH_SIZE instead of defining another macro (MAX_DIGEST).

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core/arm32: add traces in case of user TA abort

TA manager and TA mmu layer have specific trace handlers for TA aborts:
- dumping TA info.
- dumping TA mapping info.

Generic helper uuid2str().

Sig

core/arm32: add traces in case of user TA abort

TA manager and TA mmu layer have specific trace handlers for TA aborts:
- dumping TA info.
- dumping TA mapping info.

Generic helper uuid2str().

Signed-off-by: Pascal Brand <pascal.brand@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)

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Cosmetics fixes

Signed-off-by: Pascal Brand <pascal.brand@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

Fix memory leak in tee_svc_cryp_derive_key()

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (QEMU virt)
Reviewed-by: Jens Wik

Fix memory leak in tee_svc_cryp_derive_key()

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (QEMU virt)
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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Fix compile errors for core_self_tests.c

* Fixes compile errors when compiling core_self_tests.c with
debug prints
* Reduces allocation and alignment sizes in memalign() tests to work
with a sma

Fix compile errors for core_self_tests.c

* Fixes compile errors when compiling core_self_tests.c with
debug prints
* Reduces allocation and alignment sizes in memalign() tests to work
with a smaller heap.
* Checks that returned buffers has required alignment

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU virt and FVP)
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)

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