plat-vexpress: clean memory configuration

* Cleans the memory configuration for plat-vexpress to make it easier
to add fake and real SRAM.
* Uses common functions to check if a buffer intersects o

plat-vexpress: clean memory configuration

* Cleans the memory configuration for plat-vexpress to make it easier
to add fake and real SRAM.
* Uses common functions to check if a buffer intersects or is inside
a memory area
* Increases number of cores from 4 to 8 for FVP flavor to support Base
model better.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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arm32: make all TLB invalidations inner sharable

* Makes all TLB invalidations inner sharable
* Removes deprecated TLB invalidations

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Review

arm32: make all TLB invalidations inner sharable

* Makes all TLB invalidations inner sharable
* Removes deprecated TLB invalidations

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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arm32: split and enhance core_init_mmu()

* Splits core_init_mmu() into two functions, core_init_mmu_tables() called
by primary CPU to create the translation tables and core_init_mmu_regs()
calle

arm32: split and enhance core_init_mmu()

* Splits core_init_mmu() into two functions, core_init_mmu_tables() called
by primary CPU to create the translation tables and core_init_mmu_regs()
called by each CPU to initialize MMU register settings.
* Adds option to map certain areas in a level 2 translation table instead
of only level 1 mapping. Allocation of the level 2 translation tables
is implemented in platform specific code, a weak function is provided
in case the platform doesn't implement/need the function.
* Adds L2 translation table for STM and Vexpress.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU virt platform)

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arm32: add thread_init_per_cpu()

Adds a thread_init_per_cpu() function that should be called instead of
thread_init_handlers() by the secondary CPUs. The primary CPU should first
call thread_init_ha

arm32: add thread_init_per_cpu()

Adds a thread_init_per_cpu() function that should be called instead of
thread_init_handlers() by the secondary CPUs. The primary CPU should first
call thread_init_handlers() and then thread_init_per_cpu().

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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merge tee_pager*.c and tee_pager*.h files

* Merges tee_pager_unpg.c and tee_pager.c into tee_pager.c
* Merges tee_pager_unpg.h and tee_pager.h into tee_pager.h
* Removes some legacy dummy macros
* R

merge tee_pager*.c and tee_pager*.h files

* Merges tee_pager_unpg.c and tee_pager.c into tee_pager.c
* Merges tee_pager_unpg.h and tee_pager.h into tee_pager.h
* Removes some legacy dummy macros
* Replaces some while(1) with panic()

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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libtomcrypt: the len parameter of hash.final() is the max size

To be consistent with the behavior of crypto_ops.mac.final(), do not fail if
the length passed to crypto_ops.hash.final() is larger tha

libtomcrypt: the len parameter of hash.final() is the max size

To be consistent with the behavior of crypto_ops.mac.final(), do not fail if
the length passed to crypto_ops.hash.final() is larger than the hash size.

Also, use TEE_MAX_HASH_SIZE instead of defining another macro (MAX_DIGEST).

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core/arm32: add traces in case of user TA abort

TA manager and TA mmu layer have specific trace handlers for TA aborts:
- dumping TA info.
- dumping TA mapping info.

Generic helper uuid2str().

Sig

core/arm32: add traces in case of user TA abort

TA manager and TA mmu layer have specific trace handlers for TA aborts:
- dumping TA info.
- dumping TA mapping info.

Generic helper uuid2str().

Signed-off-by: Pascal Brand <pascal.brand@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)

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Cosmetics fixes

Signed-off-by: Pascal Brand <pascal.brand@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

Fix memory leak in tee_svc_cryp_derive_key()

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (QEMU virt)
Reviewed-by: Jens Wik

Fix memory leak in tee_svc_cryp_derive_key()

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (QEMU virt)
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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Fix compile errors for core_self_tests.c

* Fixes compile errors when compiling core_self_tests.c with
debug prints
* Reduces allocation and alignment sizes in memalign() tests to work
with a sma

Fix compile errors for core_self_tests.c

* Fixes compile errors when compiling core_self_tests.c with
debug prints
* Reduces allocation and alignment sizes in memalign() tests to work
with a smaller heap.
* Checks that returned buffers has required alignment

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU virt and FVP)
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)

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bugfix cache_maintenance_l1() range selection

Bugfix for cache_maintenance_l1() which did the cache operation also
on the word following the specified area.

Signed-off-by: Jens Wiklander <jens.wikl

bugfix cache_maintenance_l1() range selection

Bugfix for cache_maintenance_l1() which did the cache operation also
on the word following the specified area.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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arm32.h: make all asm statements volatile

The compiler can sometimes discard asm statements as an optimization,
adding volatile prevents that.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.o

arm32.h: make all asm statements volatile

The compiler can sometimes discard asm statements as an optimization,
adding volatile prevents that.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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thread: fix reported lr from undef-abort

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

Clean syscall handling

* Implements a svc handler suitable to supply as a handler for
thread_svc_handler.
* Removes hardcoded call to tee_svc_sycall in
thread_svc_handler.
* Removes duplicated c

Clean syscall handling

* Implements a svc handler suitable to supply as a handler for
thread_svc_handler.
* Removes hardcoded call to tee_svc_sycall in
thread_svc_handler.
* Removes duplicated code for unwinding of stack after
tee_svc_enter_user_mode() replacing it with a single
tee_svc_unwind_enter_user_mode()

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU virt and FVP)
Reviewed-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)

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Align compilation flag optee_os/optee_test(teetest)

Add plat-stm: use -mfloat-abi=soft
to fix VFP register register arguments error during testsuite linking.
It defines GCC to generate output contai

Align compilation flag optee_os/optee_test(teetest)

Add plat-stm: use -mfloat-abi=soft
to fix VFP register register arguments error during testsuite linking.
It defines GCC to generate output containing library calls for floating-point operations.
optee_test(teetest) is statically linked with new client/linux driver so far.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
Signed-off-by: Cedric Chaumont <cedric.chaumont@st.com>

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Select cryptographic algorithms at compile time

Allows to disable some cryptographic algorithms by setting make variables
at build time (either from the environment, the command line or by editing
c

Select cryptographic algorithms at compile time

Allows to disable some cryptographic algorithms by setting make variables
at build time (either from the environment, the command line or by editing
core/lib/libtomcrypt/sub.mk).

For example:
$ make ... CFG_CRYPTO=n
$ make ... CFG_CRYPTO_DES=n

This can reduce the size of the TEE binary as well as its memory footprint:

$ make -j9 PLATFORM=vexpress-qemu_virt DEBUG= all mem_usage
$ grep RAM out/arm32-plat-vexpress/core/tee.mem_usage
RAM Usage 7DF00000 - 7DF39280 size 00039280 229 KiB 58 pages
$ du -h out/arm32-plat-vexpress/core/tee.bin
164K out/arm32-plat-vexpress/core/tee.bin

$ make -j9 PLATFORM=vexpress-qemu_virt DEBUG= CFG_CRYPTO=n all mem_usage
$ grep RAM out/arm32-plat-vexpress/core/tee.mem_usage
RAM Usage 7DF00000 - 7DF1D280 size 0001D280 117 KiB 30 pages
$ du -h out/arm32-plat-vexpress/core/tee.bin
104K out/arm32-plat-vexpress/core/tee.bin

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (QEMU virt, FVP)
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)

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MAC operations now supports NULL arguments

MAC algorithms support NULL arguments and zero length strings.

Note that the fix consists in a change of API in the internal crypto
interface. This change

MAC operations now supports NULL arguments

MAC algorithms support NULL arguments and zero length strings.

Note that the fix consists in a change of API in the internal crypto
interface. This change make hash_ops and mac_ops look the same in terms of
update and final step

Signed-off-by: Pascal Brand <pascal.brand@st.com>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm: clean tz init and l2 init/enable

Useless config of read-only reg SCU_CONFIG.

L2 FLZW feature: must be set in core after L2 is configured
and enable. TZ inits default not set core FLZ. L2

plat-stm: clean tz init and l2 init/enable

Useless config of read-only reg SCU_CONFIG.

L2 FLZW feature: must be set in core after L2 is configured
and enable. TZ inits default not set core FLZ. L2 enable
sets core FLZ.

Rename PL310_WAY_SIZE into PL310_LINE_SIZE.

Reviewed-on: https://gerrit.st.com/17060
Reviewed-by: Etienne CARRIERE <etienne.carriere@st.com>
Tested-by: Etienne CARRIERE <etienne.carriere@st.com>
Reviewed-by: Pascal BRAND <pascal.brand@st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
Signed-off-by: Pascal Brand <pascal.brand@st.com>

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plat-stm: set L2 prefetch offset to 7

Reviewed-on: https://gerrit.st.com/17052
Reviewed-by: Etienne CARRIERE <etienne.carriere@st.com>
Tested-by: Etienne CARRIERE <etienne.carriere@st.com>
Reviewed-

plat-stm: set L2 prefetch offset to 7

Reviewed-on: https://gerrit.st.com/17052
Reviewed-by: Etienne CARRIERE <etienne.carriere@st.com>
Tested-by: Etienne CARRIERE <etienne.carriere@st.com>
Reviewed-by: Pascal BRAND <pascal.brand@st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

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plat-stm: fix TA L1 table handling

bugz: https://bugzilla.bri.st.com/show_bug.cgi?id=6613

There is only 1 mmu table effectively used to map TAs: one
1 at mapped at a given time.

SEC_TA_MMU_TTB_FLD

plat-stm: fix TA L1 table handling

bugz: https://bugzilla.bri.st.com/show_bug.cgi?id=6613

There is only 1 mmu table effectively used to map TAs: one
1 at mapped at a given time.

SEC_TA_MMU_TTB_FLD must be aligned, with an alignment constraint
defined from number of 1MB section entries in the user mapping.

SEC_TA_MMU_TTB_FLD could be allocated at run time.

Cleanup linker file: remove useless CTX_MEM and optimize a bit
stacks and mmu tables location.

Reviewed-on: https://gerrit.st.com/17038
Tested-by: Etienne CARRIERE <etienne.carriere@st.com>
Reviewed-by: Pascal BRAND <pascal.brand@st.com>
Reviewed-by: Etienne CARRIERE <etienne.carriere@st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

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plat-stm: L2CC_MUTEX implementation

Signed-off-by: Pascal Brand <pascal.brand@st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

Move bget to libutils replacing dlmalloc

* Moves bget to libutils replacing dlmalloc as kernel memory allocator
* Restores the code formatting of bget.{c,h} to the original state as
parts of the c

Move bget to libutils replacing dlmalloc

* Moves bget to libutils replacing dlmalloc as kernel memory allocator
* Restores the code formatting of bget.{c,h} to the original state as
parts of the current code was unreadable
* Adds malloc_add_pool() to make use of previously unused memory
* Moves call to malloc_init() into platform specific code
* Restores MDBG into working condition
* Adds memalign function to bget.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU virt platform)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (FVP)
Reviewed-by: Etienne Carriere <etienne.carriere@st.com>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)

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Make function tee_cryp_init() generic

Signed-off-by: Pascal Brand <pascal.brand@st.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

Fixes in trace refactoring

- Deprecates ATAMSG
- trace_ext.c is arm32 specific
- tee_kta_trace.h and trace_ta.h are generic
- Default level is now 1 (was 2)

Signed-off-by: Pascal Brand <pascal.bran

Fixes in trace refactoring

- Deprecates ATAMSG
- trace_ext.c is arm32 specific
- tee_kta_trace.h and trace_ta.h are generic
- Default level is now 1 (was 2)

Signed-off-by: Pascal Brand <pascal.brand@st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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Clean cache_l1 and cache_l2 maintenance

L1 cache maintenance is using Virtual Memory, whereas cache L2 maintenance
uses Physical Memory

Signed-off-by: Pascal Brand <pascal.brand@st.com>
Reviewed-by

Clean cache_l1 and cache_l2 maintenance

L1 cache maintenance is using Virtual Memory, whereas cache L2 maintenance
uses Physical Memory

Signed-off-by: Pascal Brand <pascal.brand@st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)

show more ...