struct tee_ta_ctx: remove rw_data*

Removes rw_data and tw_data_usage elements in struct tee_ta_ctx as
they are not used any longer.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewe

struct tee_ta_ctx: remove rw_data*

Removes rw_data and tw_data_usage elements in struct tee_ta_ctx as
they are not used any longer.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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arm32: Adds LPAE support

Enables use of Large Physical Address Extension (LPAE) with
CFG_WITH_LPAE=y

To facilitate both the old V7 and the new LPAE translation tables an
abstraction layer has been

arm32: Adds LPAE support

Enables use of Large Physical Address Extension (LPAE) with
CFG_WITH_LPAE=y

To facilitate both the old V7 and the new LPAE translation tables an
abstraction layer has been added to avoid direct manipulations of the
translation tables.

Both V7 and LPAE implementation uses TEX remapping (SCTLR.TRE = 1) and
enables access flags (SCTLR.AFE = 1). This is a change in the V7 code
base as those bits where 0 before. There are two reason for this change:
1."From the introduction of the Large Physical Address Extension, ARM
deprecates any use of the AP[2:0] scheme for defining MMU access
permissions. This deprecation applies to software for all ARMv7-A
implementations, regardless of whether they include the Large
Physical Address Extension."
2. With SCTLR.TRE = 1 and SCTLR.AFE = 1 V7 and LPAE implementations uses
the same way of specifying access permissions and memory attributes.

Currently only supported on plat-vexpress.

Bugfix v7 config: sets NOS bit in TTBRx registers

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP Base model)
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)

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[plat-stm] fix/disable cache FullZeroLineWrite support

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
Reviewed-by: Etienne C

[plat-stm] fix/disable cache FullZeroLineWrite support

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
Reviewed-by: Etienne CARRIERE <etienne.carriere@st.com>
Tested-by: Pascal BRAND <pascal.brand@st.com>
Reviewed-by: Pascal BRAND <pascal.brand@st.com>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

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Persistent Object Sharing Rules adjust with respect to GP v1.1

This patch implements this part of the GlobalPlatform Internal Core API v1.1

Multiple handles may be opened on the same object simulta

Persistent Object Sharing Rules adjust with respect to GP v1.1

This patch implements this part of the GlobalPlatform Internal Core API v1.1

Multiple handles may be opened on the same object simultaneously using
the functions TEE_OpenPersistentObject or TEE_CreatePersistentObject,
but sharing MUST be explicitly allowed. More precisely, at any one
time the following constraints apply: If more than one handle is opened
on the same object, and if any of these object handles was opened with
the flag TEE_DATA_FLAG_ACCESS_READ, then all the object handles MUST have
been opened with the flag TEE_DATA_FLAG_SHARE_READ. There is a corresponding
constraint with the flags TEE_DATA_FLAG_ACCESS_WRITE and
TEE_DATA_FLAG_SHARE_WRITE. Accessing an object with write-meta rights is
exclusive and can never be shared.

When one of the functions TEE_OpenPersistentObject or
TEE_CreatePersistentObject is called and if opening the object would violate
these constraints, then the function returns the return code
TEE_ERROR_ACCESS_CONFLICT.

Fix #174

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Suggested-by: xlyu <jpmhesheit@gmail.com>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (QEMU)
Signed-off-by: Pascal Brand <pascal.brand@st.com>

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crypto API: make sure TEE_Attribute parameters are readable

Fixes https://github.com/OP-TEE/optee_os/issues/161.

Services that take a TEE_Attribute array for input must check that the
memory is rea

crypto API: make sure TEE_Attribute parameters are readable

Fixes https://github.com/OP-TEE/optee_os/issues/161.

Services that take a TEE_Attribute array for input must check that the
memory is readable before using it. This is accomplished by
check_attr_read_access(), which is either called directly by the system
service or by tee_svc_cryp_check_attr(). Buffers pointed to by 'reference'
attributes are also validated.
Then, it is no longer necessary to check accessibility in other
functions such as tee_svc_cryp_obj_store_attr_raw().

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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Internal API extension on Cache Operations

Following extensions are introduced:
- TEE_CacheClean()
- TEE_CacheFlush()
- TEE_CacheInvalidate()

Reviewed-by: Jerome Forissier <jerome.foris

Internal API extension on Cache Operations

Following extensions are introduced:
- TEE_CacheClean()
- TEE_CacheFlush()
- TEE_CacheInvalidate()

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
Signed-off-by: Pascal Brand <pascal.brand@st.com>

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Fix information leakage in key generator

When generating keys we are using the RNG available for the particular
platform in use. For some reason we always or'ed a bit in the last byte,
which means t

Fix information leakage in key generator

When generating keys we are using the RNG available for the particular
platform in use. For some reason we always or'ed a bit in the last byte,
which means that we leak information. Leaking information like this is
considered as a security flaw and therefore we have removed the line
setting this bit.

Fix #178

Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: Joakim Bech <joakim.bech@linaro.org> (QEMU)
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

show more ...

RSA decode in constant time

This is a cherry-pick of the libtomcrypt pull-request
https://github.com/libtom/libtomcrypt/pull/57

As pointed by Herve Sibert, verification has been kept non-constant t

RSA decode in constant time

This is a cherry-pick of the libtomcrypt pull-request
https://github.com/libtom/libtomcrypt/pull/57

As pointed by Herve Sibert, verification has been kept non-constant time
in this patch.

Excerpt from original libtomcrypt pull-request:
as proposed in RFC 3447 only one error return code is used when there are
errors while decoding the pkcs#1 format.
also, all steps are executed and only the "output" is skipped if something
went wrong.

Sorry this could break backwards compatibility, since there's no more
BUFFER_OVERFLOW messaging.
Former error-handling code could also be affected because now there's only
OK as return code in cases where "res" is also set to '1'.

Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)
Tested-by: Pascal Brand <pascal.brand@linaro.org> (QEMU)
Signed-off-by: Pascal Brand <pascal.brand@st.com>

show more ...

Fix user TA trace issue

Definition of the global "trace_level" variable has been
moved from the libutil to a TA file (user_ta_header.c).
This allows to initialize it with the correct value/level
CFG

Fix user TA trace issue

Definition of the global "trace_level" variable has been
moved from the libutil to a TA file (user_ta_header.c).
This allows to initialize it with the correct value/level
CFG_TEE_TA_LOG_LEVEL when the TA code is compiled.
Same trace level is now applied at all TA code and associated
libraries: libutee/libutils/libmpa.

Change-Id: Id6bda7f0611f78fe7ad3ee6b61193f4b80aba94d
Signed-off-by: Jean-Michel Delorme <jean-michel.delorme@st.com>
Reviewed-on: https://gerrit.st.com/22472
Reviewed-by: Emmanuel MICHEL <emmanuel.michel@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)

show more ...

arm32 pager: remove unused functions

Removes unused tee_pager_unhide_all_pages() and tee_pager_unmap()

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerom

arm32 pager: remove unused functions

Removes unused tee_pager_unhide_all_pages() and tee_pager_unmap()

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

show more ...

core/arm32: support PL310 lockdown at TEE boot

Add routine arm_cl2_lockgit allways() that enable lock on all d/i ways.

Add config switch CFG_PL310_LOCKED. If set, at TEE boot, PL310 L2 cache
is ful

core/arm32: support PL310 lockdown at TEE boot

Add routine arm_cl2_lockgit allways() that enable lock on all d/i ways.

Add config switch CFG_PL310_LOCKED. If set, at TEE boot, PL310 L2 cache
is fully locked and invalidated. Once TZ as booted, NSec inherits from
a pre-configured L2 cache, pre-enable, but bypassed as all ways are
locked. If NSec wants to benefit from L2 cache, it shall unlock all
d/i ways.
Default setup: CFG_PL310_LOCKED is not defined. Linux may not integrate
the outercache unlock sequence at l2x0 inits.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)

Reviewed-on: https://gerrit.st.com/17088
Reviewed-by: Etienne CARRIERE <etienne.carriere@st.com>
Tested-by: Pascal BRAND <pascal.brand@st.com>
Reviewed-by: Pascal BRAND <pascal.brand@st.com>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

show more ...

[plat-stm] cache_maintenance_l2() performed on given area

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Br

[plat-stm] cache_maintenance_l2() performed on given area

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

show more ...

Refactored version of cache_maintenance_l2() functions

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand

Refactored version of cache_maintenance_l2() functions

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

show more ...

Disable TEX Remap before enable MMU

- Add write_ats1cpw() and read_par() for page description debug
- Clear TEX bit beofre enable MMU

Signed-off-by: SY Chiu <sy.chiu@linaro.org>
Reviewed-by: Jens W

Disable TEX Remap before enable MMU

- Add write_ats1cpw() and read_par() for page description debug
- Clear TEX bit beofre enable MMU

Signed-off-by: SY Chiu <sy.chiu@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: SY Chiu <sy.chiu@linaro.org> (QEMU)
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)

show more ...

sunxi: fix parallel build errors

Fixes https://github.com/OP-TEE/optee_os/issues/181.

plat-sunxi/link.mk uses CPP to generate its core linker script.
Commit a3911433960a ("core: get value of CFG_ v

sunxi: fix parallel build errors

Fixes https://github.com/OP-TEE/optee_os/issues/181.

plat-sunxi/link.mk uses CPP to generate its core linker script.
Commit a3911433960a ("core: get value of CFG_ variables directly from
generated/conf.h") has modified the core CPP flags to include conf.h
automatically, so one must make sure that this file exists when the linker
script is generated. This is done by adding a dependency on $(conf-file).

The vexpress platforms also lack the dependency, but the bug won't show
because of other dependencies which cause conf.h to be generated anyways.

PLATFORM=stm is fine because it does not use CPP.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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SE API: Change configuration to be prefixed with CFG_*

Signed-off-by: SY Chiu <sy.chiu@linaro.org>
Tested-by: SY Chiu <sy.chiu@linaro.org> (Modified QEMU + jcardsim)

SE API: hide private interfaces

- Split each headers into module.h and module_priv.h, move the methods that
is only used internally by SE implementation to module_priv.h, and export
module_priv.

SE API: hide private interfaces

- Split each headers into module.h and module_priv.h, move the methods that
is only used internally by SE implementation to module_priv.h, and export
module_priv.h to rest of TEE Core
- Added new include path to se_api_self_tests.c for which needs to include
private headers
- Split aid.c and apdu.c from iso7816.c. Originally they have to be wriiten in
the same file since they share some private data structures. Now, the
private data structure can be shared via private headers.
- Split reader.c from manager.c for the same reason above.

Signed-off-by: SY Chiu <sy.chiu@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: SY Chiu <sy.chiu@linaro.org> (Modified QEMU + jcardsim)

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SE API: implment lubutee and svc handler

- Implemented tee_se_service
- Rename tee_se_reader_handle to tee_se_reader_proxy
to avoid confuse with libutee
- Implemented SE API(tee_internal_se_api.h)

SE API: implment lubutee and svc handler

- Implemented tee_se_service
- Rename tee_se_reader_handle to tee_se_reader_proxy
to avoid confuse with libutee
- Implemented SE API(tee_internal_se_api.h) in libutee
- Implemented svc handler for SE API
- rename protocol.[ch] to iso7816.[ch]
- prefix aid_* with "tee_se_"
- add an option to enable/disable se_api_self_tests

Signed-off-by: SY Chiu <sy.chiu@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: SY Chiu <sy.chiu@linaro.org> (Modified QEMU + jcardsim)

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SE API: Session, Protocol and Channel implementation

- Implement Session which maintains the connection between TA and a
specific SE Reader
- Implement ISO7816 transport layer protocol, and Channe

SE API: Session, Protocol and Channel implementation

- Implement Session which maintains the connection between TA and a
specific SE Reader
- Implement ISO7816 transport layer protocol, and Channel management
- Implement Utilities to handle AID(ISO7816-3) and APDU(ISO7816-4)
- Brunch of self tests to velidate functionality of each module

Signed-off-by: SY Chiu <sy.chiu@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: SY Chiu <sy.chiu@linaro.org> (Modified QEMU + jcardsim)

show more ...

SE API: SE Manager and Reader implementation

- Introduce an interface for developers to write reader driver
(core/include/tee/se/reader/interface.h)
- A sample reader driver implementation: PC/SC

SE API: SE Manager and Reader implementation

- Introduce an interface for developers to write reader driver
(core/include/tee/se/reader/interface.h)
- A sample reader driver implementation: PC/SC passthru reader
(core/tee/se/reader/passthru_reader)
- Currently supported machine is qemu-virt (compile with --with-pcsc-passthru)
- A selftest STA is included to test the functionality of SE Reader
(core/arch/arm32/sta/se_api_self_tests.c)
- To enable SE API, add "WITH_SE_API := y" in your platform config

Signed-off-by: SY Chiu <sy.chiu@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: SY Chiu <sy.chiu@linaro.org> (Modified QEMU + jcardsim)

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Introduce a Linux style initcall mechanism

To use it, simply add something like:

service_init(server_init_callback);

The callback regsitered will be invoked at the end of init_teecore().
Now we ha

Introduce a Linux style initcall mechanism

To use it, simply add something like:

service_init(server_init_callback);

The callback regsitered will be invoked at the end of init_teecore().
Now we have 2 priority service_init and driver_init. The callback
regsitered in service level will be invoked first.

Signed-off-by: SY Chiu <sy.chiu@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: SY Chiu <sy.chiu@linaro.org> (QEMU)

show more ...

SHA-1 ARMv8 crypto extension implementation

* Adds a ARMv8 crypto extension based SHA-1 implementation for LTC.
* Crypto extension based SHA-1 implementation is enabled for
plat-vexpress-juno.

Si

SHA-1 ARMv8 crypto extension implementation

* Adds a ARMv8 crypto extension based SHA-1 implementation for LTC.
* Crypto extension based SHA-1 implementation is enabled for
plat-vexpress-juno.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno)
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM platform)

show more ...

SHA-256 ARMv8 crypto extension implementation

* Adds a ARMv8 crypto extension based SHA-256 implementation for LTC.
* Crypto extension based SHA-256 implementation is enabled for
plat-vexpress-ju

SHA-256 ARMv8 crypto extension implementation

* Adds a ARMv8 crypto extension based SHA-256 implementation for LTC.
* Crypto extension based SHA-256 implementation is enabled for
plat-vexpress-juno.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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arm32: support for VFP/NEON operations.

CFG_WITH_VFP=y enables use of VFP/NEON by context switching VFP state on
demand.

plat-vexpress: specific initialization of CPACR to allow CP10 and CP11
acces

arm32: support for VFP/NEON operations.

CFG_WITH_VFP=y enables use of VFP/NEON by context switching VFP state on
demand.

plat-vexpress: specific initialization of CPACR to allow CP10 and CP11
access to allow usage of VFP/NEON operations.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

show more ...

plat-vexpress: config nsacr

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>