Rename libtomcrypt_with_optimize_size in CFG_CRYPTO_SIZE_OPTIMIZATION

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-b

Rename libtomcrypt_with_optimize_size in CFG_CRYPTO_SIZE_OPTIMIZATION

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

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arm: sm: [bugfix] save/restore fiq core registers

Currently there's a security problem with the FIQ registers for armv7
targets, both with leaking information and that normal world can change
stack

arm: sm: [bugfix] save/restore fiq core registers

Currently there's a security problem with the FIQ registers for armv7
targets, both with leaking information and that normal world can change
stack pointer for FIQ mode. This patch fixes this problem.

Saves and restores FIQ core registers (spsr, sp, lr) when switching
secre/non-secure state.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (modified QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Minimal OP-TEE without user TAs

Hide all user TA related code under CFG_WITH_USER_TA. When compiled
with:
CFG_WITH_USER_TA=n
CFG_CRYPTO=n
CFG_ENC_FS=n
CFG_SE_API=n
CFG_PCSC_PASSTHRU_READER_DRV=n

Sk

Minimal OP-TEE without user TAs

Hide all user TA related code under CFG_WITH_USER_TA. When compiled
with:
CFG_WITH_USER_TA=n
CFG_CRYPTO=n
CFG_ENC_FS=n
CFG_SE_API=n
CFG_PCSC_PASSTHRU_READER_DRV=n

Skips building in static TA tests for features not enabled.

The size of OP-TEE is reduced to one third of its original size.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU xtest 1001)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Introduce CFG_CRYPTO_WITH_CE

CFG_CRYPTO_WITH_CE is inroduced in this patch, and fixes
CFG_CRYPTO=n CFG_ARM64_core=n compilation issue on HiKey and Juno.

CFG_CRYPTO_WITH_CE indicates Crypto Engine a

Introduce CFG_CRYPTO_WITH_CE

CFG_CRYPTO_WITH_CE is inroduced in this patch, and fixes
CFG_CRYPTO=n CFG_ARM64_core=n compilation issue on HiKey and Juno.

CFG_CRYPTO_WITH_CE indicates Crypto Engine acceleration can be
used. CFG_CRYPTO_xxx_CE configuration variables are automatically
set, according to other configuration variables (CFG_ARM32_core or
CFG-ARM64_core, SHA and AES available).

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

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Remove unused syscalls

A number of syscalls which are now unused have been removed:
- TEE_SCN_DUMMY
- TEE_SCN_DUMMY_7ARGS
- TEE_SCN_GET_PROPERTY_OBSOLETE

This breaks binary compatibility

Reviewed-

Remove unused syscalls

A number of syscalls which are now unused have been removed:
- TEE_SCN_DUMMY
- TEE_SCN_DUMMY_7ARGS
- TEE_SCN_GET_PROPERTY_OBSOLETE

This breaks binary compatibility

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

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Remove TEE_ARRAY_SIZE definition

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

core: remove unused core_pa2va_helper()

Removes the unused deprecated function core_pa2va_helper().

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.

core: remove unused core_pa2va_helper()

Removes the unused deprecated function core_pa2va_helper().

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: deprecate old address translation functions

Deprecates the old address translation functions and removes their
wrapper macros. All calls to the deprecated functions are replaced with
calls to

core: deprecate old address translation functions

Deprecates the old address translation functions and removes their
wrapper macros. All calls to the deprecated functions are replaced with
calls to the new translation functions instead.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add new address translation functions

Adds two new functions for address translations, virt_to_phys() and
phys_to_virt() that eventually will replace all other such functions.

Reviewed-by: Pa

core: add new address translation functions

Adds two new functions for address translations, virt_to_phys() and
phys_to_virt() that eventually will replace all other such functions.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm64.h add registers for address translation

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@lina

arm64.h add registers for address translation

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm32.h add PAR 32 and 64-bit register

Adds functions and defines for PAR 32 and 64-bit register.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.or

arm32.h add PAR 32 and 64-bit register

Adds functions and defines for PAR 32 and 64-bit register.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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fix: Add fault type to crash dump

Fixes previous f2930adaf8a10f2a6154ae21ec991ce7133fde82 "Add fault type
to crash dump" to only interpret fault_descr for data and prefetch abort
to avoid asserting

fix: Add fault type to crash dump

Fixes previous f2930adaf8a10f2a6154ae21ec991ce7133fde82 "Add fault type
to crash dump" to only interpret fault_descr for data and prefetch abort
to avoid asserting if fault_descr is 0 for LPAE.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU with LPAE)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Add fault type to crash dump

Currently, when a data or instruction abort occurs in a TA, the crash
dump does not clearly show the fault type (translation/permission/
alignment fault). This commit pr

Add fault type to crash dump

Currently, when a data or instruction abort occurs in a TA, the crash
dump does not clearly show the fault type (translation/permission/
alignment fault). This commit prints out the fault type for all faults.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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qemu_armv8a: use VIRT_SECURE_MEM as secure memory

Redefine secure memory as defined by VIRT_SECURE_MEM in QEMU

Secure SRAM is used by ARM-TF as 0x0e000000..0x0f000000
Define TZDRAM_BASE to 0x0e1000

qemu_armv8a: use VIRT_SECURE_MEM as secure memory

Redefine secure memory as defined by VIRT_SECURE_MEM in QEMU

Secure SRAM is used by ARM-TF as 0x0e000000..0x0f000000
Define TZDRAM_BASE to 0x0e100000 (size 0x00f00000)

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU armv8a)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: don't clear current session before RPC

As the translation tables used to create user TA mapping are assigned
per thread there's no need to clear current session before RPC and
restore it when

core: don't clear current session before RPC

As the translation tables used to create user TA mapping are assigned
per thread there's no need to clear current session before RPC and
restore it when the RPC has returned.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: new OPTEE_MSG interface

* Changes to a new OPTEE_MSG interface to work with the generic TEE driver.
* Removes TEESMC64_* defines as the TEESMC32_* functions are enhanced to
take 64bit values

core: new OPTEE_MSG interface

* Changes to a new OPTEE_MSG interface to work with the generic TEE driver.
* Removes TEESMC64_* defines as the TEESMC32_* functions are enhanced to
take 64bit values where required in pairs of 32bit registers instead.
* Changes open session meta information to be passed in two value
parameters instead of one memref.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM)
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm32: CFG_WITH_PAGER and CFG_TEE_GDB_BOOT are incompatible

The pager and GDB boot configurations assign different meanings to the
r0 register when entering the _start function. Therefore, they must

arm32: CFG_WITH_PAGER and CFG_TEE_GDB_BOOT are incompatible

The pager and GDB boot configurations assign different meanings to the
r0 register when entering the _start function. Therefore, they must not
be enabled at the same time.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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Introduce CFLAGS32 and CFLAGS64

Previously, compile.mk and gcc.mk were using $(CFLAGS) which cannot
properly handle 32-bit and 64-bit compiles. This commit introduces
CFLAGS32 and CFLAGS64 instead,

Introduce CFLAGS32 and CFLAGS64

Previously, compile.mk and gcc.mk were using $(CFLAGS) which cannot
properly handle 32-bit and 64-bit compiles. This commit introduces
CFLAGS32 and CFLAGS64 instead, which are set to $(CFLAGS) by defaut
for convenience.

For each submodule (core, ta_arm32, ta_arm64) a new internal variable
is defined in the architecture makefile (core/arch/arm/arm.mk):
arch-bits-$(sm). Its value is either 32 or 64. This can later be used
to reference the proper CFLAGS.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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libtomcrypt: ASN1/DER fixes

- Synchronization with LibTomCrypt from
origin/develop branch
(commit 4a3b53dbee4bca1f151d9a64e9584a4c8152f0b1)

- Only "src/pk/asn1/der" directory has been synchroni

libtomcrypt: ASN1/DER fixes

- Synchronization with LibTomCrypt from
origin/develop branch
(commit 4a3b53dbee4bca1f151d9a64e9584a4c8152f0b1)

- Only "src/pk/asn1/der" directory has been synchronized

- Additional changes over synchronization:
Several default case added in switch case condition
when missing.

Signed-off-by: Philippe PAGE <philippe.page@st.com>
Reviewed-by: Etienne CARRIERE <etienne.carriere@st.com>
Tested-by: Etienne CARRIERE <etienne.carriere@st.com>

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Properties: Adding Microsoft specific property

As an example on how to add vendor specific properties,
the microsoft specific property is added.

Original pull-request is
https://github.com/OP-T

Properties: Adding Microsoft specific property

As an example on how to add vendor specific properties,
the microsoft specific property is added.

Original pull-request is
https://github.com/OP-TEE/optee_os/pull/460

Suggested-by: Paul Swan <paswan@microsoft.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (QEMU)
Signed-off-by: Pascal Brand <pascal.brand@st.com>

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Properties: prepare to add vendor specific properties

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

thread: add thread_get_id_may_fail() function

Adds thread_get_id_may_fail() which is used by trace_ext_get_thread_id()
to add the thread id for debug prints.

Reviewed-by: Pascal Brand <pascal.brand

thread: add thread_get_id_may_fail() function

Adds thread_get_id_may_fail() which is used by trace_ext_get_thread_id()
to add the thread id for debug prints.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: deal with large init part

When init + hashes part is very large it may overlay source and
destination range. Change to copy init + hash as memmove instead of
memcpy.

Reviewed-by: Pascal

core: arm: deal with large init part

When init + hashes part is very large it may overlay source and
destination range. Change to copy init + hash as memmove instead of
memcpy.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: always dsb prior to tlb invalidation

Always does an DSB prior to TLB invalidation.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linar

core: arm: always dsb prior to tlb invalidation

Always does an DSB prior to TLB invalidation.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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pager: print detailed error on unknown addresses

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>