core: arm: mm: v7: use mm->va to locate the entry of ttb

Use mm->va to locate the entry of ttb, we should not use
mm->pa, because va may be not the same with pa.

Signed-off-by: Peng Fan <van.freeni

core: arm: mm: v7: use mm->va to locate the entry of ttb

Use mm->va to locate the entry of ttb, we should not use
mm->pa, because va may be not the same with pa.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arch: arm correct mme.va initialization

mme.va should be initialized using map[n].va, but not map[n].pa.

Now map[n].pa can make all work, because we use 1 to 1 mapping with
virtual address sa

core: arch: arm correct mme.va initialization

mme.va should be initialized using map[n].va, but not map[n].pa.

Now map[n].pa can make all work, because we use 1 to 1 mapping with
virtual address same to physical address.

Later, we need to implement that virtual address not equal to physical
address to avoid address conflicting with user ta address and optee os
kernel address(<= 64M).

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm: mm: v7: panic when va conficts with KMAP address space

If mm->va is smaller that 64M and bigger that 32M, mm->va
conflicts with KMAP address space

Some SoCs have devices at low addresses, so w

arm: mm: v7: panic when va conficts with KMAP address space

If mm->va is smaller that 64M and bigger that 32M, mm->va
conflicts with KMAP address space

Some SoCs have devices at low addresses, so we need to map at
least those devices at a virtual address which isn't the same
as the physical.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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RPMB: tee_rpmb_write_blk(): allocate buffers once

Allocate shared memory buffers once for the write loop instead of
repeatedly allocating and freeing them. The previous code was needed
due to a bug/

RPMB: tee_rpmb_write_blk(): allocate buffers once

Allocate shared memory buffers once for the write loop instead of
repeatedly allocating and freeing them. The previous code was needed
due to a bug/limitation in optee_linudriver [1]. Now that we are using
the "generic driver", the code can be optimized.

[1] https://github.com/OP-TEE/optee_linuxdriver/issues/40

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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pager: replace mm element of struct tee_pager_area

Replaces the mm element of struct tee_pager_area with base and size
instead to avoid needing a matching mm for every area.

Reviewed-by: Pascal Bra

pager: replace mm element of struct tee_pager_area

Replaces the mm element of struct tee_pager_area with base and size
instead to avoid needing a matching mm for every area.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Pascal Brand <pascal.brand@linaro.org> (STM)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, Juno)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: rename TEE_MATTR_PHYS_BLOCK

Renames TEE_MATTR_PHYS_BLOCK to TEE_MATTR_HIDDEN_DIRTY_BLOCK.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@lin

core: rename TEE_MATTR_PHYS_BLOCK

Renames TEE_MATTR_PHYS_BLOCK to TEE_MATTR_HIDDEN_DIRTY_BLOCK.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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pager: don't use TEE_MATTR_PHYS_BLOCK

Don't use TEE_MATTR_PHYS_BLOCK to keep track of physical address of a
struct tee_pager_pmem page, read it from the aliased mapping which
always is available and

pager: don't use TEE_MATTR_PHYS_BLOCK

Don't use TEE_MATTR_PHYS_BLOCK to keep track of physical address of a
struct tee_pager_pmem page, read it from the aliased mapping which
always is available and doesn't change.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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pager: optimize alias table lookup

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: support mapping user TAs with 4k pages

Maps user TAs with small pages (aka 4k pages) if
CFG_SMALL_PAGE_USER_TA = y
If pager is active the translation tables are allocated using
tee_pager_reque

core: support mapping user TAs with 4k pages

Maps user TAs with small pages (aka 4k pages) if
CFG_SMALL_PAGE_USER_TA = y
If pager is active the translation tables are allocated using
tee_pager_request_zi() to only use the physical page when needed.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm: refactor core_mmu*

Refactors core_mmu* to let LPAE and V7 compat table code share some
code for mapping a TA.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander

arm: refactor core_mmu*

Refactors core_mmu* to let LPAE and V7 compat table code share some
code for mapping a TA.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm: fix traces when booting

On plat-stm, traces IP is initialized by Non Secure world.
Hence no traces can be output while in the booting process.

Reviewed-by: Jens Wiklander <jens.wiklander@

plat-stm: fix traces when booting

On plat-stm, traces IP is initialized by Non Secure world.
Hence no traces can be output while in the booting process.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

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plat-stm: remove unused code

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

core: fix build error with CFG_TEE_CORE_DEBUG=y

Fixes build error when CFG_TEE_CORE_DEBUG=y and CFG_WITH_PAGER=y are set
by adding ing CORE_MMU_PGDIR_SIZE and CORE_MMU_PGDIR_MASK.

Reviewed-by: Pasc

core: fix build error with CFG_TEE_CORE_DEBUG=y

Fixes build error when CFG_TEE_CORE_DEBUG=y and CFG_WITH_PAGER=y are set
by adding ing CORE_MMU_PGDIR_SIZE and CORE_MMU_PGDIR_MASK.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Fix potential memory corruptions in elf_load.c when loading TAs

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Suggested-by: Jaso

Fix potential memory corruptions in elf_load.c when loading TAs

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Suggested-by: Jason Lin <Jason.Lin@microsoft.com>
Suggested-by: Paul Swan <Paul.Swan@microsoft.com>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

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Fix wrong comment syntax

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

juno: bug fix initialize TCR_EL1

Prior to this patch TCR_EL1 was incorrectly initialized with bit 32 set
to 0. On Cortex-A57 this bit is RES1 so this bit should always be set to
1, this patch fixes

juno: bug fix initialize TCR_EL1

Prior to this patch TCR_EL1 was incorrectly initialized with bit 32 set
to 0. On Cortex-A57 this bit is RES1 so this bit should always be set to
1, this patch fixes that.

This is related to errata 822227
"Using unsupported 16K translation granules might cause Cortex-A57 to
incorrectly trigger a domain fault"

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Validate the TA signed header's img_size

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Suggested-by: Jason Lin <Jason.Lin@microsoft.com>
Suggested-by: Paul Swan <Paul.Swan@microsoft.com>
S

Validate the TA signed header's img_size

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Suggested-by: Jason Lin <Jason.Lin@microsoft.com>
Suggested-by: Paul Swan <Paul.Swan@microsoft.com>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

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stm,vexpress: increase shared memory size from 1 to 2 MiB

This is needed to run the latest "generic driver" configuration.
When the shared memory pool is 1 MiB, xtest 7633 fails with a TA panic
due

stm,vexpress: increase shared memory size from 1 to 2 MiB

This is needed to run the latest "generic driver" configuration.
When the shared memory pool is 1 MiB, xtest 7633 fails with a TA panic
due to memory allocation error. This commit increases the size of the
shared memory pool so that the test will pass.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

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core: arm: pager: lock shared accesses

Uses the pager spin-lock for all shared accesses to pager resources.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Jerome Forissier <jerome.f

core: arm: pager: lock shared accesses

Uses the pager spin-lock for all shared accesses to pager resources.

Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU FVP)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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optee_msg: add OPTEE_MSG_RPC_CMD_SHM_FREE

Buffers allocated with OPTEE_MSG_RPC_CMD_SHM_ALLOC must be freed
with OPTEE_MSG_RPC_CMD_SHM_FREE to help normal world driver to
route the message correctly.

optee_msg: add OPTEE_MSG_RPC_CMD_SHM_FREE

Buffers allocated with OPTEE_MSG_RPC_CMD_SHM_ALLOC must be freed
with OPTEE_MSG_RPC_CMD_SHM_FREE to help normal world driver to
route the message correctly.

Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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libtomcrypt: mpa_desc.c: check return status of allocations

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal

libtomcrypt: mpa_desc.c: check return status of allocations

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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fs: do not call thread_rpc_free() when allocation fails

When thread_rpc_alloc_payload() fails, the cookie is not valid, so
thread_rpc_free() must not be called. This fixes a crash in xtest
7633 when

fs: do not call thread_rpc_free() when allocation fails

When thread_rpc_alloc_payload() fails, the cookie is not valid, so
thread_rpc_free() must not be called. This fixes a crash in xtest
7633 when shared memory is not large enough.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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hikey: increase shared memory size from 1 to 2 MiB

This is needed to run the latest "generic driver" configuration.
When the shared memory pool is 1 MiB, xtest 7633 fails with a TA panic
due to memo

hikey: increase shared memory size from 1 to 2 MiB

This is needed to run the latest "generic driver" configuration.
When the shared memory pool is 1 MiB, xtest 7633 fails with a TA panic
due to memory allocation error. This commit increases the size of the
shared memory pool so that the test will pass.
Note that UEFI (EDK2) reserves the top 32 MiB of the physical address
space (0x3E000000-0x3FFFFFFF) for OP-TEE, so we still have 14 MiB unused
(0x3E000000-0x3EDFFFFF).

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Pascal Brand <pascal.brand@linaro.org>

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LTC: no definition of LTC_NO_FAST

LTC_NO_FAST resets LTC_FAST if the latter has been set.
Indeed, LTC_FAST is never set on ARM architecture,
so LTC_NO_FAST has no effect

Reviewed-by: Jerome Forissi

LTC: no definition of LTC_NO_FAST

LTC_NO_FAST resets LTC_FAST if the latter has been set.
Indeed, LTC_FAST is never set on ARM architecture,
so LTC_NO_FAST has no effect

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

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CFG_CRYPTO_SIZE_OPTIMIZATION?=y by default

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand <pascal.bra

CFG_CRYPTO_SIZE_OPTIMIZATION?=y by default

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Pascal Brand <pascal.brand@st.com>

show more ...