secure storage: move TEE_FS_MODE_* constants out of tee_fs_defs.h

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: David B

secure storage: move TEE_FS_MODE_* constants out of tee_fs_defs.h

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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Change the access right from w to r in virt_to_phy

Currently we are using the write_ats1cpw to do the
virt_to_phys translation, but when the input address
is readonly, the translation will fail, fix

Change the access right from w to r in virt_to_phy

Currently we are using the write_ats1cpw to do the
virt_to_phys translation, but when the input address
is readonly, the translation will fail, fix it using
write_ats1cpr.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Zeng Tao <prime.zeng@huawei.com>

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drivers: hi16xx_uart: cleanup

- The FIFOs are automatically cleared when FIFO mode is enabled, so
don't use (UART_FCR_RX_FIFO_RST | UART_FCR_TX_FIFO_RST).
- hi16xx_uart_putc() waits for the TX FIFO

drivers: hi16xx_uart: cleanup

- The FIFOs are automatically cleared when FIFO mode is enabled, so
don't use (UART_FCR_RX_FIFO_RST | UART_FCR_TX_FIFO_RST).
- hi16xx_uart_putc() waits for the TX FIFO to be empty before pushing
a new character. It is a good thing to avoid losing several characters
when the control is transferred to another piece of software which may
be resetting the UART (such as the Linux kernel). Therefore, remove the
commented out code which deals with "TX FIFO not full".

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: hi16xx_uart: remove useless dsb()'s

Since we use write32() to operate on device memory, accesses are
necessarily ordered and there is no need for data synchronization
barriers.

Signed-off-

drivers: hi16xx_uart: remove useless dsb()'s

Since we use write32() to operate on device memory, accesses are
necessarily ordered and there is no need for data synchronization
barriers.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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arm32: AES using ARMv8-A cryptographic extensions

Add AES acceleration to LibTomCrypt in 32-bit mode using ARMv8
Cryptographic Extensions. Enabled when CFG_CRYPTO_AES_ARM32_CE=y.

The ARMv8 CE assem

arm32: AES using ARMv8-A cryptographic extensions

Add AES acceleration to LibTomCrypt in 32-bit mode using ARMv8
Cryptographic Extensions. Enabled when CFG_CRYPTO_AES_ARM32_CE=y.

The ARMv8 CE assembler code comes from the Linux kernel's
arch/arm64/crypto/aes-ce-core.S (contributed by Ard Biesheuvel,
Linaro) with minor updates:

- Removed the alignment hints in vld1/vst1 operations, for instance
'vld1.8 {q1}, [r1, :64]!' becomes 'vld1.8 {q1}, [r1]!'. This is
required because the input and output buffers may not be 8-byte
aligned.
- ce_aes_ctr_encrypt(): do not increment the counter on the first block
because the C wrapper already did. Do not increment the counter after
the last block has been processed either, because the C wrapper will do
it before calling ce_aes_ctr_encrypt() again.
- aes_xts_decrypt(): drop the 'first' parameter which is not used (it
would always be set to 1 by the caller).

Tested on HiKey with xtest [1] for functional tests and aes-perf [2] for
speed. In the table below, a mode name followed by a '+' means
accelerated with crypto extensions, while no '+' is with acceleration
disabled (i.e., CFG_CRYPTO_AES_ARM32_CE=n).

Average encryption speed (MiB/s):

Size | Mode
(KiB) | ECB CBC CTR XTS ECB+ CBC+ CTR+ XTS+
------+--------------------------------------------------
1 | 14.9 12.7 12.3 10.9 33.8 32.7 33.3 29.1
2 | 18.2 15.4 14.9 13.3 65.0 60.9 62.6 55.4
4 | 20.8 17.3 16.6 15.0 119.3 106.0 112.6 101.0
8 | 22.4 18.2 17.6 16.0 201.6 166.5 182.3 166.7
16 | 23.3 19.0 18.1 16.6 308.1 232.9 264.3 248.3
32 | 23.8 19.3 18.4 16.9 427.7 295.1 346.4 335.1
64 | 24.0 19.5 18.6 17.1 532.8 341.3 411.0 407.6
128 | 24.2 19.6 18.7 17.2 608.1 371.3 454.9 457.5
256 | 24.2 19.6 18.7 17.1 624.4 382.0 463.5 481.6
512 | 24.0 19.4 18.6 17.1 658.8 389.6 477.3 498.3

[1] https://github.com/OP-TEE/optee_test
[2] https://github.com/linaro-swg/aes-perf.git

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm64: libtomcrypt: rename AES CE files

aes_arm64_ce.c contains wrapper code for the assembly routines that
implement AES using the ARMv8-A cryptographic extensions. It is
currently used only in 64-

arm64: libtomcrypt: rename AES CE files

aes_arm64_ce.c contains wrapper code for the assembly routines that
implement AES using the ARMv8-A cryptographic extensions. It is
currently used only in 64-bit builds, but could be used for 32-bits
as well. So, rename it to aes_armv8a_ce.c to better reflect its content
and prepare for 32-bit support. Also rename the 64-bit assembly file
(aes_modes_arm64_ce_a64.S -> aes_modes_armv8a_ce_a64.S) for
consistency.
Note: this naming scheme (xyz_armv8a_ce.c / xyz_armv8a_ce_a{32,64}.S)
is already used for SHA1 and SHA2.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm64: libtomcrypt: move inline assembly to .S file

In order to be able to re-use aes_arm64_ce.c for arm32, move all the
inline assembly to aes_modes_arm64_ce_a64.S.

Signed-off-by: Jerome Forissier

arm64: libtomcrypt: move inline assembly to .S file

In order to be able to re-use aes_arm64_ce.c for arm32, move all the
inline assembly to aes_modes_arm64_ce_a64.S.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress: configure tzc400 driver if enabled

Configures the tzc400 driver if CFG_TZC400 is y.

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Reviewed-by: David Brown <david.brown@

plat-vexpress: configure tzc400 driver if enabled

Configures the tzc400 driver if CFG_TZC400 is y.

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU, FVP)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add tzc400 driver

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: add ps2mouse driver

Adds a PS/2 mouse driver that uses serial abstract driver for
communication with the mouse.

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Reviewed-by: David

core: add ps2mouse driver

Adds a PS/2 mouse driver that uses serial abstract driver for
communication with the mouse.

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add pl050 (KMI) driver

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: add serial abstraction

Adds an abstraction for a serial device.

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Signed-off-by: Je

core: add serial abstraction

Adds an abstraction for a serial device.

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add display abstraction

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: add pl111 (LCD) driver

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: add generic framebuffer driver

Adds a generic framebuffer driver. Currently only supports framebuffers
configured for 24BPP.

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Review

core: add generic framebuffer driver

Adds a generic framebuffer driver. Currently only supports framebuffers
configured for 24BPP.

Reviewed-by: etienne carriere <etienne.carriere@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-d02: enable hardware RNG

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Reviewed-by: etienne carriere <etienne.carriere@linaro.o

plat-d02: enable hardware RNG

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Reviewed-by: etienne carriere <etienne.carriere@linaro.org>

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drivers: add Hi16xx RNG driver

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Reviewed-by: etienne carriere <etienne.carriere@linaro.

drivers: add Hi16xx RNG driver

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Reviewed-by: etienne carriere <etienne.carriere@linaro.org>

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core: review assert and panic traces

Replace few "{ EMSG(...); panic(); }" with "panic(...);".

Disable file/line/func debug traces in panic() logs when
CFG_TEE_CORE_DEBUG is disable.

Change __asse

core: review assert and panic traces

Replace few "{ EMSG(...); panic(); }" with "panic(...);".

Disable file/line/func debug traces in panic() logs when
CFG_TEE_CORE_DEBUG is disable.

Change __assert_log() uses EMSG_RAW() to no pollute trace with
__assert_log() internals (duplicated file/line/func traces).

Change assert() to use a low/high verbosity mode upon
CFG_TEE_CORE_DEBUG as panic() does.

Change assert() to also trace the C function where assertion failed.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jen.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (QEMU)

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core: panic() macro accepts zero or one string argument.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jen.wiklander@linaro.org>
Reviewed-by: Etienne Car

core: panic() macro accepts zero or one string argument.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jen.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (QEMU)

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core: remove TEE_ASSERT()

TEE_ASSERT() can be confusing regarding assert() as assert() can
be disabled through NDEBUG while TEE_ASSERT() can't.
Instead one should explicitly implement "if (cond) { p

core: remove TEE_ASSERT()

TEE_ASSERT() can be confusing regarding assert() as assert() can
be disabled through NDEBUG while TEE_ASSERT() can't.
Instead one should explicitly implement "if (cond) { panic(); }"

This patch removes several inclusions on tee_common_unpg.h as it
used to define TEE_ASSERT() that has been removed.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jen.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (QEMU)

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assert/panic: fix misuse of assert/panic

Currently implementation of macro assert() does not expand to a
no-op when NDEBUG is defined. This will be done in a later change.
Before that, fix misuses o

assert/panic: fix misuse of assert/panic

Currently implementation of macro assert() does not expand to a
no-op when NDEBUG is defined. This will be done in a later change.
Before that, fix misuses of assert() and TEE_ASSERT():
- Correct misplaced assert() that should panic() whatever NDEBUG.
- Correct misplaced TEE_ASSERT() that should simply assert().

Also cleanup many inclusions of "assert.h" and few calls of assert().

Signed-off-by: Jens Wiklander <jen.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (QEMU)

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Simplify platform testing macros

Update the main Makefile so that PLATFORM_$(PLATFORM) and
PLATFORM_FLAVOR_$(PLATFORM_FLAVOR) are set to 'y', and add these
variables to the export list for the gener

Simplify platform testing macros

Update the main Makefile so that PLATFORM_$(PLATFORM) and
PLATFORM_FLAVOR_$(PLATFORM_FLAVOR) are set to 'y', and add these
variables to the export list for the generation of conf.h.

As a result, the definition of numerical flavor identifiers in the
multiple platform_config.h files is not needed anymore, and we can also
get rid of the PLATFORM_FLAVOR_IS() test macro. Instead, replace all
occurrences of '#if PLATFORM_FLAVOR_IS(foo)' with
'#if defined(PLATFORM_FLAVOR_foo)'.

This makes it possible to test the platform and not only the flavor in
any source file, so drop the manual definition of PLATFORM_hikey.

Finally, remove the definitions of platform_$(PLATFORM) and
platform_flavor_$(PLATFORM_FLAVOR) from core/core.mk since they are not
used.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>

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Fix reversed order of carriage return and line feed..

..in console_putc() function.

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

Add support for Hisilicon D02 (PLATFORM=d02)

D02 is a server-class development board equipped with a Hisilicon
Phosphor V660 processor (also called PV660, P660 or hip05).
The chip has 16 Cortex-A57

Add support for Hisilicon D02 (PLATFORM=d02)

D02 is a server-class development board equipped with a Hisilicon
Phosphor V660 processor (also called PV660, P660 or hip05).
The chip has 16 Cortex-A57 cores @ 2.1 GHz.

Note: '-mcpu=cortex-a57' causes the following warning, which doesn't
seem to have any adverse effect on OP-TEE and is registered as a
compiler bug [1]:

CC out/arm-plat-d02/core/lib/libtomcrypt/src/encauth/ccm/ccm_add_nonce.o
{standard input}: Assembler messages:
{standard input}:634: IT blocks containing 32-bit Thumb instructions are deprecated in ARMv8

[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67591

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>

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Add UART driver for Hisilicon Hi16xx

Applies to SoCs in the Hi16xx family, and to Phosphor V660 a.k.a. hip05
(the CPU on the Hisilicon D02 development board).

Signed-off-by: Jerome Forissier <jerom

Add UART driver for Hisilicon Hi16xx

Applies to SoCs in the Hi16xx family, and to Phosphor V660 a.k.a. hip05
(the CPU on the Hisilicon D02 development board).

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>

show more ...