core: arm: add generic secondary core boot function

Signed-off-by: Yan Yan <yan.yan@windriver.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wikla

core: arm: add generic secondary core boot function

Signed-off-by: Yan Yan <yan.yan@windriver.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: ltc: fix gcc6 warnings

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: encode UUID big endian

When encoding a UUID as a sequence of bytes, the spec
(https://www.ietf.org/rfc/rfc4122.txt) says that the u32, and two u16s
should be represented big endian.

Before th

core: encode UUID big endian

When encoding a UUID as a sequence of bytes, the spec
(https://www.ietf.org/rfc/rfc4122.txt) says that the u32, and two u16s
should be represented big endian.

Before this patch OPTEE always treated them natively. With this patch
UUIDs are always converted to/from big endian when communicating with
normal world.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Fixes: https://github.com/OP-TEE/optee_os/issues/858
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: optee_msg.h include needed .h files

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

mm: drop the forced PL1 RW permissions for user TAs

We have used simple memory access permission model in OP-TEE, if PL1
permission is forced RW, the PL0 permission can only be set to RW or
no acces

mm: drop the forced PL1 RW permissions for user TAs

We have used simple memory access permission model in OP-TEE, if PL1
permission is forced RW, the PL0 permission can only be set to RW or
no access, so the PL0 permission is set to RW in the user TAs which is
not as expected.

Fix it as follow,
1. when TA is in loading process, the PL1 is set to own the RW
permission while the PL0 with no accesss.
2. when the TA is loaded, the PL0 is set to own the required
permissions defined in ta elf program headers and from the access
control model, the PL1 will own the same permissions as the PL0.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>

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core: fix pl310 shared mutex registering

Fix missing virtual/physical address conversion. Before this change
the outercache shared mutex was functional only when optee pager was
disable as in such c

core: fix pl310 shared mutex registering

Fix missing virtual/physical address conversion. Before this change
the outercache shared mutex was functional only when optee pager was
disable as in such case shared mutex lied in a flat-mapped memory area
(va==pa). When optee pager is enable (CFG_WITH_PAGER=y), non_linear
mapping of optee core makes optee providing nonsecure world (through
OPTEE_SMC_L2CC_MUTEX_GET_ADDR) an invalid shared mutex physical address.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
[Rebase on top of master]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: assert that mutexes are used from a normal thread only

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etie

core: assert that mutexes are used from a normal thread only

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260)
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: assert that no spinlock is held when unmasking IRQs or using a mutex

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
R

core: assert that no spinlock is held when unmasking IRQs or using a mutex

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: assert that IRQs are masked when calling spinlock functions

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-b

core: assert that IRQs are masked when calling spinlock functions

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm32: remove .section .text.proc from proc_a32.S

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wi

core: arm32: remove .section .text.proc from proc_a32.S

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: move spinlock functions to their own file

- 64-bit spinlock functions are implemented in their own file. Do
likewise for 32-bit functions. While we're at it:
- Update comments
- Use local

core: move spinlock functions to their own file

- 64-bit spinlock functions are implemented in their own file. Do
likewise for 32-bit functions. While we're at it:
- Update comments
- Use local labels so that the file is closer to the original ARM-TF
file (lib/locks/exclusive/aarch32/spinlock.S).
- Create a new header file: core/arch/arm/include/kernel/spinlock.h.
- Delete core/arch/arm/include/kernel/tz_proc.h, which is not needed
any more.
- Make sure that cpu_mmu_enable() and friends are in the unpaged
section by using KEEP_PAGER. It looks like previously, they were stored
in the correct place by chance, probably because they were in the same
section as the spinlock functions.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: introduce KEEP_PAGER and KEEP_INIT assembler macros

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens

core: introduce KEEP_PAGER and KEEP_INIT assembler macros

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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secure storage: change struct tee_fs_file_info member type

In struct tee_fs_file_info, the member length's origin type is size_t,
when NS user is 64 bits, and secure kernel is 32 bits, the type size

secure storage: change struct tee_fs_file_info member type

In struct tee_fs_file_info, the member length's origin type is size_t,
when NS user is 64 bits, and secure kernel is 32 bits, the type size_t
will have different width, which will cause xtest 20022 case fail.
This commit change the member length's type from size_t to uint64_t,
which can keep a fixed width.

Signed-off-by: Guanchao Liang <liang.guanchao@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)

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core: arm32_macros: sort based on the CRn

Sort based on CRn

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core: arm: add more cp15 register access macros

Add more cp15 register access macros.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core: pager: light refactoring

A light refactoring of the pager to get rid of one ifdef section and
some preparation for coming changes. No changes in behaviour.

Reviewed-by: Jerome Forissier <jero

core: pager: light refactoring

A light refactoring of the pager to get rid of one ifdef section and
some preparation for coming changes. No changes in behaviour.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU pager)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: use wrapper function for locking

Simplifies the code by using a wrapper function for locking instead
of the two-step spinlock procedure.

Reviewed-by: Jerome Forissier <jerome.forissier

core: pager: use wrapper function for locking

Simplifies the code by using a wrapper function for locking instead
of the two-step spinlock procedure.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: rename to tee_pager_set_uta_area_attr()

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <j

core: rename to tee_pager_set_uta_area_attr()

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add core_mmu_get_user_pgdir()

Adds core_mmu_get_user_pgdir() to fill in a struct core_mmu_table_info
describing the page directory used for user TAs.

Reviewed-by: Jerome Forissier <jerome.for

core: add core_mmu_get_user_pgdir()

Adds core_mmu_get_user_pgdir() to fill in a struct core_mmu_table_info
describing the page directory used for user TAs.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pgt_cache: describe pgt_cache_list

Adds a comment describing pgt_cache_list.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro

core: pgt_cache: describe pgt_cache_list

Adds a comment describing pgt_cache_list.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: bugfix core_mmu_get_entry_primitive()

Fixes both implementations of core_mmu_get_entry_primitive() to
correctly report TEE_MATTR_TABLE.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.

core: bugfix core_mmu_get_entry_primitive()

Fixes both implementations of core_mmu_get_entry_primitive() to
correctly report TEE_MATTR_TABLE.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: user_ta_dump_state() prints phys addr

user_ta_dump_state() prints physical addresses in addition to
the already present virtual addresses.

Reviewed-by: Jerome Forissier <jerome.forissier@lina

core: user_ta_dump_state() prints phys addr

user_ta_dump_state() prints physical addresses in addition to
the already present virtual addresses.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: protect tee_pobj functions with mutex

The tee_pobj functions can be called concurrently, add a mutex to
protect the internal state.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

core: protect tee_pobj functions with mutex

The tee_pobj functions can be called concurrently, add a mutex to
protect the internal state.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP Base model)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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pl310: beautify

Use explicit labels instead of comments to make code readable.
Remove useless comments.
Remove few useless instructions.
Indent assembly instructions.

Signed-off-by: Etienne Carrier

pl310: beautify

Use explicit labels instead of comments to make code readable.
Remove useless comments.
Remove few useless instructions.
Indent assembly instructions.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

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pl310: fix 16-way pl310 support

Get number of ways from the PL310 configuration AUX_CTRL[bit#16].
tz_ssvce_def.h require util.h for BIT32().

Signed-off-by: Etienne Carriere <etienne.carriere@linaro

pl310: fix 16-way pl310 support

Get number of ways from the PL310 configuration AUX_CTRL[bit#16].
tz_ssvce_def.h require util.h for BIT32().

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Peng Fan <peng.fan@nxp.com> (i.MX6Q-SDB)
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260)

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