| 1a848923 | 15-May-2017 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: unexport deprecated core_va2pa_helper()
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> |
| 1217af2f | 11-May-2017 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: remove unused CORE_MEM_EXTRAM
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@lin
core: remove unused CORE_MEM_EXTRAM
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU) Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| dd14d0bd | 10-May-2017 |
Jerome Forissier <jerome.forissier@linaro.org> |
core: arm: mm: LPAE: init_xlation_table(): skip dynamic entries properly
When enumerating static_memory_map to setup the translation table, the "dynamic" entries are skipped incorrectly. As a result
core: arm: mm: LPAE: init_xlation_table(): skip dynamic entries properly
When enumerating static_memory_map to setup the translation table, the "dynamic" entries are skipped incorrectly. As a result, if the first entry is MEM_AREA_RES_VASPACE, the function does nothing (because core_mmu_is_dynamic_vaspace(mm) is true and base_va is NULL) and the translation tables are left uninitialized.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Fixes: c6c69797168c ("mm: add new VA region for dynamic shared buffers") Fixes: https://github.com/OP-TEE/optee_os/issues/1511 Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey) Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 05173e9a | 09-May-2017 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: fix map pa to va and vice versa
map_pa2va() and core_va2pa_helper() has an over complex way of calculating the translated address which gives a faulty result if the upper 32-bits are used in a
core: fix map pa to va and vice versa
map_pa2va() and core_va2pa_helper() has an over complex way of calculating the translated address which gives a faulty result if the upper 32-bits are used in a 64-bit address. This patch fixes the error by simplifying the calculation.
Reported-by: Zhizhou Zhang <zhizhouzhang@asrmicro.com> Tested-by: Zhizhou Zhang <zhizhouzhang@asrmicro.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP AArch64) Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU v7 & v8) Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| ee664c19 | 05-May-2017 |
Jerome Forissier <jerome.forissier@linaro.org> |
core: add interface to load user TAs
Some use cases may require custom load and verification methods for user-mode Trusted Applications. Introduce struct user_ta_store_ops with open(), get_size(), r
core: add interface to load user TAs
Some use cases may require custom load and verification methods for user-mode Trusted Applications. Introduce struct user_ta_store_ops with open(), get_size(), read() and close() functions to abstract these tasks from the ELF loader code. Do the communication with tee-supplicant as well as the hashing and signature verification of the TA binary in core/arch/arm/kernel/ree_fs_ta.c, which may be disabled and replaced by a different implementation if need be.
CC: Zeng Tao <prime.zeng@hisilicon.com> Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey, QEMU) Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 762b7d0d | 01-Mar-2017 |
Mathieu Briand <mbriand@witekio.com> |
core: arm: Enable interruptions on i.MX6
Signed-off-by: Mathieu Briand <mbriand@witekio.com> Acked-by: Peng Fan <peng.fan@nxp.com> Acked-by: Yan Yan <yan.yan@windriver.com> |
| 8ac8d930 | 04-May-2017 |
Jerome Forissier <jerome.forissier@linaro.org> |
core: mm: add missing entry in teecore_memtype_name()
teecore_memtype_name() does not handle MEM_AREA_SHM_VASPACE. Add it.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by:
core: mm: add missing entry in teecore_memtype_name()
teecore_memtype_name() does not handle MEM_AREA_SHM_VASPACE. Add it.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 440e2223 | 03-May-2017 |
David Wang <david.wang@arm.com> |
The other bits in GICD_CTLR should not be touched
The gic_init() function enables secure and non-secure group1 interrupts in GICD_CTLR register. But the other bits should not be modified to avoid `U
The other bits in GICD_CTLR should not be touched
The gic_init() function enables secure and non-secure group1 interrupts in GICD_CTLR register. But the other bits should not be modified to avoid `UNPREDICTABLE` behaviours as per ARM GICv3 specification.
Signed-off-by: David Wang <david.wang@arm.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> [jf: minor edits to commit message] Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
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| e040af6c | 20-Apr-2017 |
Andrew F. Davis <afd@ti.com> |
plat-ti: Add secure paging support for DRA7xx/AM57xx
Add definitions for secure SRAM and DRAM space for builds with CFG_WITH_PAGER enabled.
Signed-off-by: Andrew F. Davis <afd@ti.com> Acked-by: Jen
plat-ti: Add secure paging support for DRA7xx/AM57xx
Add definitions for secure SRAM and DRAM space for builds with CFG_WITH_PAGER enabled.
Signed-off-by: Andrew F. Davis <afd@ti.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 2579b45c | 20-Apr-2017 |
Andrew F. Davis <afd@ti.com> |
plat-ti: Remove duplicate SECRAM memory definition
After removing DEVICEx_TYPE/_PA_BASE/_SIZE support the definition for SECRAM was moved to main.c, but we had already made this move, remove the dup
plat-ti: Remove duplicate SECRAM memory definition
After removing DEVICEx_TYPE/_PA_BASE/_SIZE support the definition for SECRAM was moved to main.c, but we had already made this move, remove the duplicate definition.
Signed-off-by: Andrew F. Davis <afd@ti.com> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| e3e468b3 | 20-Dec-2016 |
Volodymyr Babchuk <vlad.babchuk@gmail.com> |
core_mmu: add page map/unmap functions
This function allows to map list of physical pages to specified virtual memory address.
Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com> Reviewed-by:
core_mmu: add page map/unmap functions
This function allows to map list of physical pages to specified virtual memory address.
Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> [jf: remove braces {} around single statement block] Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
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| c6c69797 | 14-Apr-2017 |
Volodymyr Babchuk <vlad.babchuk@gmail.com> |
mm: add new VA region for dynamic shared buffers
This region will be used later to dynamically map shared buffers provided by Normal World.
Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
mm: add new VA region for dynamic shared buffers
This region will be used later to dynamically map shared buffers provided by Normal World.
Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| d246df92 | 28-Apr-2017 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: fix build with DEBUG=y and LOG_LEVEL=0
Fix build issue with CFG_TEE_CORE_DEBUG=y and CFG_TEE_CORE_LOG_LEVEL=0.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Reviewed-by: Jens Wikl
core: fix build with DEBUG=y and LOG_LEVEL=0
Fix build issue with CFG_TEE_CORE_DEBUG=y and CFG_TEE_CORE_LOG_LEVEL=0.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| 4dc31c52 | 02-Mar-2017 |
Jerome Forissier <jerome.forissier@linaro.org> |
core: arm: generic boot: dt: switch console to /secure-chosen/stdout-path
If CFG_DT=y, check the Device Tree's /secure-chosen node and look for the stdout-path property. Adjust the console output ac
core: arm: generic boot: dt: switch console to /secure-chosen/stdout-path
If CFG_DT=y, check the Device Tree's /secure-chosen node and look for the stdout-path property. Adjust the console output accordingly. The DT bindings for this property have been proposed on the LKML [1].
[1] https://www.spinics.net/lists/arm-kernel/msg566034.html
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (QEMU) Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| ddf45954 | 02-Mar-2017 |
Jerome Forissier <jerome.forissier@linaro.org> |
pl011: dt: Add DT support
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro
pl011: dt: Add DT support
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 9e30051e | 02-Mar-2017 |
Jerome Forissier <jerome.forissier@linaro.org> |
dt: Introduce struct serial_driver
Add struct serial_driver which will be useful to UART drivers that want to create devices from a DT node.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro
dt: Introduce struct serial_driver
Add struct serial_driver which will be useful to UART drivers that want to create devices from a DT node.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 7ba16abb | 02-Mar-2017 |
Jerome Forissier <jerome.forissier@linaro.org> |
dt: Add dt_map_dev()
Maps a device into memory from its FDT node.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-
dt: Add dt_map_dev()
Maps a device into memory from its FDT node.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 9fe4c797 | 02-Mar-2017 |
Jerome Forissier <jerome.forissier@linaro.org> |
dt: Add FDT manipulation functions
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wikland
dt: Add FDT manipulation functions
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| a4f139d7 | 04-Mar-2016 |
Jerome Forissier <jerome.forissier@linaro.org> |
core: introduce struct dt_driver
When CFG_DT=y, a linker section is created (.rodata.dtdrv) to hold all the DT-compatible drivers. The table can later be queried at runtime. Some manipulation functi
core: introduce struct dt_driver
When CFG_DT=y, a linker section is created (.rodata.dtdrv) to hold all the DT-compatible drivers. The table can later be queried at runtime. Some manipulation functions are exported in <kernel/dt.h>.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| f4cfdeba | 27-Feb-2017 |
Jerome Forissier <jerome.forissier@linaro.org> |
core: dt: use fdt_address_cells() and fdt_size_cells()
Use the functions provided by libfdt instead of our own.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Ca
core: dt: use fdt_address_cells() and fdt_size_cells()
Use the functions provided by libfdt instead of our own.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 2c39ee19 | 27-Apr-2017 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: fix non-LPAE page mapped static mapping
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> |
| 2dd446e9 | 27-Apr-2017 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: fix test against end address of core virtual memory
Fix the first argument of the ROUNDUP() that should be 'map->va' instead of 'va' which is the lowest virtual address mapped.
'va_max' is re
core: fix test against end address of core virtual memory
Fix the first argument of the ROUNDUP() that should be 'map->va' instead of 'va' which is the lowest virtual address mapped.
'va_max' is renamed 'end' to help code fitting in 80 char lines.
Fixes: aa2ab38be0aa (core: more flexible static memory mapping) Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 455856d4 | 19-Apr-2017 |
Jens Wiklander <jens.wiklander@linaro.org> |
Remove SQL-FS
With recent developments in REE-FS SQL-FS has become redundant. This patch removes SQL-FS.
Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Acked-by: Jerome Forissier <jerome.forissi
Remove SQL-FS
With recent developments in REE-FS SQL-FS has become redundant. This patch removes SQL-FS.
Reviewed-by: Joakim Bech <joakim.bech@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU) Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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| dc9c6dda | 25-Apr-2017 |
Jerome Forissier <jerome.forissier@linaro.org> |
crypto: don't check hash size when the main algorithm is ECDSA
syscall_asymm_verify() (and therefore TEE_AsymmetricVerifyDigest()) incorrectly assumes that the hash algorithm is SHA1 when the main a
crypto: don't check hash size when the main algorithm is ECDSA
syscall_asymm_verify() (and therefore TEE_AsymmetricVerifyDigest()) incorrectly assumes that the hash algorithm is SHA1 when the main algorithm is ECDSA, and will panic the TA if the hash size is not set accordingly. This behavior does not comply with the TEE Internal Core API v1.1, which states:
"Where a hash algorithm is specified in the algorithm, digestLen SHALL be equal to the digest length of this hash algorithm".
For TEE_ALG_ECDSA_P192, TEE_ALG_ECDSA_P224, TEE_ALG_ECDSA_P256, TEE_ALG_ECDSA_P384 and TEE_ALG_ECDSA_P521, no hash algorithm is specified, and so we must not restrict the hash size to any specific value.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reported-by: Henrik Andersson <Henrik.Andersson@se.bosch.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
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| 03b03fae | 24-Apr-2017 |
Jerome Forissier <jerome.forissier@linaro.org> |
plat-imx: use the mov_imm macro instead of movw/movt
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wikla
plat-imx: use the mov_imm macro instead of movw/movt
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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