plat-hikey: enable 64-bit paging

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

plat-vexpress: enable 64-bit paging

Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (Hikey GP)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno AArch64)
Tested-by: Jens Wiklande

plat-vexpress: enable 64-bit paging

Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (Hikey GP)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno AArch64)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP AArch64)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU AArch64)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: increase emulated SRAM

Increases emulated TrustZone protected SRAM to 448 kB to increase
the pager performance especially for 64-bit mode.

Reviewed-by: Etienne Carriere <etienne.carriere

core: arm: increase emulated SRAM

Increases emulated TrustZone protected SRAM to 448 kB to increase
the pager performance especially for 64-bit mode.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: update 64-bit copy_init from 32-bit version

Updates the copy_init part in generic_entry_a64.S from
generic_entry_a32.S

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-b

core: update 64-bit copy_init from 32-bit version

Updates the copy_init part in generic_entry_a64.S from
generic_entry_a32.S

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: 64-bit update release_unused_kernel_stack()

release_unused_kernel_stack() is called when the pager is enabled when
the state of a thread is saved in order to release unused stack pages.

Updat

core: 64-bit update release_unused_kernel_stack()

release_unused_kernel_stack() is called when the pager is enabled when
the state of a thread is saved in order to release unused stack pages.

Update release_unused_kernel_stack() for 64-bit mode.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: bugfix tee_pager_release_phys()

Fixes the case where less than a page is to be released by ignoring the
request.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jen

core: bugfix tee_pager_release_phys()

Fixes the case where less than a page is to be released by ignoring the
request.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: link script: .bss alignment

.bss may need a larger alignment than 8. Instead of trying to guess let
the linker chose it and to avoid having an unaccounted hole before .bss
set __data_end first

core: link script: .bss alignment

.bss may need a larger alignment than 8. Instead of trying to guess let
the linker chose it and to avoid having an unaccounted hole before .bss
set __data_end first thing inside the .bss section. This makes sure that
the data section is properly padded out when assembling a paged tee.bin.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pager: invalidate tlb when clearing entry

When clearing an entry in a translation table corresponding TLB entry
must always be invalidated. With this patch two missing places are
addressed. Th

core: pager: invalidate tlb when clearing entry

When clearing an entry in a translation table corresponding TLB entry
must always be invalidated. With this patch two missing places are
addressed. This fixes problem in xtest regression suite case 1016.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add dsb instructions for tlb invalidation

Adds DSB instructions needed for correct visibility of TLB
invalidations.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by:

core: add dsb instructions for tlb invalidation

Adds DSB instructions needed for correct visibility of TLB
invalidations.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: make 64-bit tlb invalidation inner shareable

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

ltc: fix 64-bit warning

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: REE_FS: avoid deadlock in ree_fs_create()

ree_fs_close() can't be called in ree_fs_create() cleanup as
ree_fs_close() tries to acquire the mutex already acquired in
ree_fs_create(). Copy relev

core: REE_FS: avoid deadlock in ree_fs_create()

ree_fs_close() can't be called in ree_fs_create() cleanup as
ree_fs_close() tries to acquire the mutex already acquired in
ree_fs_create(). Copy relevant content from ree_fs_close() instead.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: assert against recursive mutex locking

Adds an assert to check that the thread holding a mutex tries to lock it
again.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-b

core: assert against recursive mutex locking

Adds an assert to check that the thread holding a mutex tries to lock it
again.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: make alignment check configurable

We occasionally get reports from people stumbling upon data abort
exceptions caused by alignment faults in TAs. The recommended fix is to
change the code

core: arm: make alignment check configurable

We occasionally get reports from people stumbling upon data abort
exceptions caused by alignment faults in TAs. The recommended fix is to
change the code so that the unaligned access won't occur. But it is
sometimes difficult to achieve.

Therefore we provide a compile-time option to disable alignment checks.
For AArch64 it applies to both SEL1 and SEL0.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: tzc380: add tzc380 driver

Add tzc380 driver support.

The usage:
Use tzc_init(vaddr_t base) to get the tzc380 configuration.
Use tzc_configure_region to configure the memory region,
such as

drivers: tzc380: add tzc380 driver

Add tzc380 driver support.

The usage:
Use tzc_init(vaddr_t base) to get the tzc380 configuration.
Use tzc_configure_region to configure the memory region,
such as "tzc_configure_region(5, 0x4e000000,
TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_32M) | TZC_ATTR_REGION_EN_MASK |
TZC_ATTR_SP_S_RW);"

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: fix weakness in shm registration

When core needs to validate content before it is used, core must first
move the data in secure memory, then validate it (or not), then access
validated data fr

core: fix weakness in shm registration

When core needs to validate content before it is used, core must first
move the data in secure memory, then validate it (or not), then access
validated data from secure memory only, not from original shared memory
location.

This change fixes mobj_reg_shm_alloc() so that it checks the validity
of the registered reference after the references are copied into the
secure memory.

This change fixes mobj_mapped_shm_alloc() to use the shm buffer reference
instead of the initial description still located in shared memory.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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Remove buffering for AES CTR

CTR mode of AES algorithm turns block cipher into stream cipher.
It means that input data can has any size independent from block
size. It must be processed and result c

Remove buffering for AES CTR

CTR mode of AES algorithm turns block cipher into stream cipher.
It means that input data can has any size independent from block
size. It must be processed and result ciphertext must be
generated after each TEE_CipherUpdate function call. That is why
it is incorrect to apply for AES CTR the input buffering on
TEE_CipherUpdate call when size is not multiple of block size.

Signed-off-by: Bogdan Liulko <bogdan.liulko@globallogic.com>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)
Tested-by: Bogdan Liulko <bogdan.liulko@globallogic.com> (R-Car)
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix the keepalive condition in close session

According to the The GP Internal Core API v1.1:
The keepalive flag should be ignored when the single instance flag is
not set.

Reviewed-by: Jens W

core: fix the keepalive condition in close session

According to the The GP Internal Core API v1.1:
The keepalive flag should be ignored when the single instance flag is
not set.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>

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mobj: add mobj_reg_shm and mobj_mapped_shm

mobj_reg_shm represents registered shared memory. This is basically
a list of pages provided by normal world. It can be used to pass
memory parameters to T

mobj: add mobj_reg_shm and mobj_mapped_shm

mobj_reg_shm represents registered shared memory. This is basically
a list of pages provided by normal world. It can be used to pass
memory parameters to TAs.

mobj_mapped_shm is built on top of mobj_reg_shm. It is almost
the same thing, but it is mapped to OP-TEE virtual address space,
so OP-TEE kernel can access such buffers.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core_mmu: add non-secure DDR ranges support

This patch adds new macro `register_nsec_ddr` which allows
platform code to register non-secure memory ranges.

Signed-off-by: Volodymyr Babchuk <vlad.bab

core_mmu: add non-secure DDR ranges support

This patch adds new macro `register_nsec_ddr` which allows
platform code to register non-secure memory ranges.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: add linker.h for link script symbols

Moves all core extern declarations of linker script symbols into
<kernel/linker.h>.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off

core: add linker.h for link script symbols

Moves all core extern declarations of linker script symbols into
<kernel/linker.h>.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: imx: use core_mmu_get_va

Use core_mmu_get_va to simplify the code.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jen

core: arm: imx: use core_mmu_get_va

Use core_mmu_get_va to simplify the code.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: mmu: add core_mmu_get_va helper function

Add core_mmu_get_va helper function.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-b

core: mmu: add core_mmu_get_va helper function

Add core_mmu_get_va helper function.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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OP-TEE Benchmark

OP-TEE Benchmark feature provides timestamp data for the roundtrip time
from libteec to OP-TEE OS core.

Benchmark PTA handles registration/unregistration commands of timestamp
buff

OP-TEE Benchmark

OP-TEE Benchmark feature provides timestamp data for the roundtrip time
from libteec to OP-TEE OS core.

Benchmark PTA handles registration/unregistration commands of timestamp
buffer, invoked by optee_benchmark NW application, and performs
registration of timestamp buffer in the linux kernel optee driver via
RPC call.

To enable this feature set CFG_TEE_BENCHMARK compile flag to "y".

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>

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Remove CFG_SMALL_PAGE_USER_TA=n

Removes CFG_SMALL_PAGE_USER_TA and keep the code that was activated by
CFG_SMALL_PAGE_USER_TA=y. This means that CFG_SMALL_PAGE_USER_TA=n which
resulted in TA being m

Remove CFG_SMALL_PAGE_USER_TA=n

Removes CFG_SMALL_PAGE_USER_TA and keep the code that was activated by
CFG_SMALL_PAGE_USER_TA=y. This means that CFG_SMALL_PAGE_USER_TA=n which
resulted in TA being mapped using 1 MiB or 2 MiB granularity is removed.

Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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