core: tee_mmu: avoid resource leak

If calloc fails, need to free the asid bit in g_asid.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core: user_ta: use TEE_MMU_UMAP_STACK_IDX

Use TEE_MMU_UMAP_STACK_IDX to replace the number 0.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

plat-ti: Configure and enable Secure Data Path by default

Enable SDP by default on TI platforms and reserve 4 MiB from the end of
the TZDRAM area that is already reserved for OP-TEE and firewalled.

plat-ti: Configure and enable Secure Data Path by default

Enable SDP by default on TI platforms and reserve 4 MiB from the end of
the TZDRAM area that is already reserved for OP-TEE and firewalled.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-ti: Add Suspend/Resume support for AM43xx

When the non-secure world is attempting to suspend it will call into the
secure side using a platform service call. We implement this here in
OP-TEE by

plat-ti: Add Suspend/Resume support for AM43xx

When the non-secure world is attempting to suspend it will call into the
secure side using a platform service call. We implement this here in
OP-TEE by saving the needed secure side registers.

On resume the ROM will restore the secure side to its original
configuration and OP-TEE will be re-entered from its boot reset vector.
Add a check for the resume case and restore the secure registers if we
are resuming.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: thread: clarify syscalls return and panic

Updates comments describing how syscall_sys_return() and syscall_panic()
manages to return from the TA in order to resume execution in OP-TEE OS.

Ack

core: thread: clarify syscalls return and panic

Updates comments describing how syscall_sys_return() and syscall_panic()
manages to return from the TA in order to resume execution in OP-TEE OS.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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qemu_v8: move SHM region

With the current setup, qemu puts initrd in the midst of reserved
SHM region. This confuses linux kernel, because it forbids self
to access that reserved region.
As there ar

qemu_v8: move SHM region

With the current setup, qemu puts initrd in the midst of reserved
SHM region. This confuses linux kernel, because it forbids self
to access that reserved region.
As there are no easy way tell qemu where to put initrd, it is easier
to move SHM in the optee-os.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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TUI: remove frame buffer

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

TUI: remove ps2mouse

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

TUI: remove clcd pl111

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

TUI: remove PL050

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

plat-ti: Disable TRNG use on AM43xx

On AM43xx family devices the non-secure side may IDLE hardware IP
that are not in use. This will prevent the correct operation of these
IP on the secure side. Unt

plat-ti: Disable TRNG use on AM43xx

On AM43xx family devices the non-secure side may IDLE hardware IP
that are not in use. This will prevent the correct operation of these
IP on the secure side. Until a solution to share management of IPs is
developed, disable the secure driver for this platform.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-mediatek: Use CFG_CORE_CLUSTER_SHIFT to remove get_core_pos_mpidr()

Use the new CFG_CORE_CLUSTER_SHIFT to remove the platform specific
core_pos() helpers.

Signed-off-by: Andrew F. Davis <afd@t

plat-mediatek: Use CFG_CORE_CLUSTER_SHIFT to remove get_core_pos_mpidr()

Use the new CFG_CORE_CLUSTER_SHIFT to remove the platform specific
core_pos() helpers.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: Make core_pos more generic

The function core_pos() assumes 4 cores per cluster, this may not
be true for all platforms. Define CFG_CORE_CLUSTER_SHIFT to be
=log2(cores/cluster) and allow setti

core: Make core_pos more generic

The function core_pos() assumes 4 cores per cluster, this may not
be true for all platforms. Define CFG_CORE_CLUSTER_SHIFT to be
=log2(cores/cluster) and allow setting this from platform config.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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rpmb: mask off RPV/CRC fields in CID to derive rpmb key

PRV (Product revision) [55:48] and CRC field [7:1] in CID would be
changed when doing eMMC FFU.
It is reasonable to mask off PRV and CRC in CI

rpmb: mask off RPV/CRC fields in CID to derive rpmb key

PRV (Product revision) [55:48] and CRC field [7:1] in CID would be
changed when doing eMMC FFU.
It is reasonable to mask off PRV and CRC in CID when using CID to
derive RPMB key.

Signed-off-by: Peifu Jiang <peifu.jiang@amlogic.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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dts: pass PA of reserved region

config_nsmem() used VA of SHM region. This is wrong and it confused
linux kernel. We need to pass physical address.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gm

dts: pass PA of reserved region

config_nsmem() used VA of SHM region. This is wrong and it confused
linux kernel. We need to pass physical address.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: psci: Split PM config from PSCI

Not all platforms need PM when implementing PSCI, also some
platforms may need PM but do not implement PSCI. As PSCI has
no direct dependence on PM, split

core: arm: psci: Split PM config from PSCI

Not all platforms need PM when implementing PSCI, also some
platforms may need PM but do not implement PSCI. As PSCI has
no direct dependence on PM, split these config options.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: fix core_mmu_map_pages()

Adds missing dsb_ishst() at the end of core_mmu_map_pages() needed to
guarantee that changes to translation tables are visible.

Reviewed-by: Etienne Carriere <etienne

core: fix core_mmu_map_pages()

Adds missing dsb_ishst() at the end of core_mmu_map_pages() needed to
guarantee that changes to translation tables are visible.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Stuart Yoder <stuart.yoder@arm.com>
Reported-by: Stuart Yoder <stuart.yoder@arm.com>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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qemu_virt: enable smp boot

Enables SMP boot of the plat-vexpress qemu_virt flavor. This includes
PSCI support and coherent memory shared with bios.

Acked-by: Jerome Forissier <jerome.forissier@lina

qemu_virt: enable smp boot

Enables SMP boot of the plat-vexpress qemu_virt flavor. This includes
PSCI support and coherent memory shared with bios.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: generic boot: update fdt with psci

If configured with device tree and PSCI update the FDT with PSCI nodes
and other information needed by the kernel to start up the secondary
cores.

Acked-by:

core: generic boot: update fdt with psci

If configured with device tree and PSCI update the FDT with PSCI nodes
and other information needed by the kernel to start up the secondary
cores.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: plat-vextpress-qemu_virt: update num cores

Changes number of supported cores for variant qemu_virt to 4.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander

core: plat-vextpress-qemu_virt: update num cores

Changes number of supported cores for variant qemu_virt to 4.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: plat-vexpress: init gic on secondary cores

Initialize GIC on secondary cores if not configured with ARM-TF.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklan

core: plat-vexpress: init gic on secondary cores

Initialize GIC on secondary cores if not configured with ARM-TF.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: make reset_secondary() unpaged

reset_secondary() and dependencies has to be unpaged as most of it is
executed before the core has been properly configured to use the pager.

Acked-by: Jerome F

core: make reset_secondary() unpaged

reset_secondary() and dependencies has to be unpaged as most of it is
executed before the core has been properly configured to use the pager.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: print rwx flags for each MMU region when a user TA aborts

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

core: arm: imx7d: add psci suspend support

Implement i.MX7D suspend/resume support.
When the first time runs into suspend, some initialization work needs
to be done, such as code copy, iram translat

core: arm: imx7d: add psci suspend support

Implement i.MX7D suspend/resume support.
When the first time runs into suspend, some initialization work needs
to be done, such as code copy, iram translation table.

Since we only have 32K on chip RAM for suspend/resume usage, we have
to put code and data together and use section mapping and WXN is set
to false.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: arm: imx7d: remove soc_is_imx7d/s functions

Remove soc_is_imx7d/s functions. Not needed.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-

core: arm: imx7d: remove soc_is_imx7d/s functions

Remove soc_is_imx7d/s functions. Not needed.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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