| 4b6058e4 | 03-Nov-2021 |
Gabriel Fernandez <gabriel.fernandez@foss.st.com> |
clk: fix clk_get_rate() when parent clock rate was changed
clk_get_rate() returns a cached value of the clock rate.
If the rate of the parent clock changed, then the rate is not synchronized. Chan
clk: fix clk_get_rate() when parent clock rate was changed
clk_get_rate() returns a cached value of the clock rate.
If the rate of the parent clock changed, then the rate is not synchronized. Change the function to compute all clock parents' rates and return the synchronized value.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com> Fixes: 2305544b3b9b ("drivers: clk: add generic clock framework")
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| 9b941cd7 | 23-Jan-2025 |
Sungbae Yoo <sungbaey@nvidia.com> |
core: mmu: fix memory regions found from ff-a manifest
Fix the 5th parameter of add_phys_mem() in collect_device_mem_ranges() that has to be the size of memory region and not the end address of the
core: mmu: fix memory regions found from ff-a manifest
Fix the 5th parameter of add_phys_mem() in collect_device_mem_ranges() that has to be the size of memory region and not the end address of the region.
Fixes: b8ef8d0b6ff4 ("core: mm: introduce struct memory_map") Signed-off-by: Sungbae Yoo <sungbaey@nvidia.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 0ed372c6 | 15-Jan-2025 |
Jerome Forissier <jerome.forissier@linaro.org> |
core: pta: device: fix enumeration for PTA_CMD_GET_DEVICES_SUPP
TAs which depend on TEE_STORAGE_PRIVATE do need the TEE supplicant if REE FS is disabled (in which case secure storage can only be RPM
core: pta: device: fix enumeration for PTA_CMD_GET_DEVICES_SUPP
TAs which depend on TEE_STORAGE_PRIVATE do need the TEE supplicant if REE FS is disabled (in which case secure storage can only be RPMB) and RPMB is not routed via the kernel.
Fixes: a96033ca7bee ("core: add flag to enumerate TAs when secure storage is ready") Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 10cc5912 | 21-Jun-2024 |
Runyang Chen <runyang.chen@mediatek.com> |
drivers: gic: Dynamically assign interrupts to non-secure world
Add gic_spi_release_to_ns() API function in GIC driver to release an interrupt to Non secure settings. This functionality is essential
drivers: gic: Dynamically assign interrupts to non-secure world
Add gic_spi_release_to_ns() API function in GIC driver to release an interrupt to Non secure settings. This functionality is essential for scenarios where a specific interrupt needs to be dynamically set to either Group 1 Secure (G1S) or Group 1 Non-Secure (G1NS) at different times.
Signed-off-by: Runyang Chen <runyang.chen@mediatek.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| bef959c8 | 02-Dec-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: arm: ffa: switch to FF-A version 1.2
Update FF-A minor version from 1 to 2. spmc_exchange_version() is updated to take the new version into account when negotiating with a caller.
Configurati
core: arm: ffa: switch to FF-A version 1.2
Update FF-A minor version from 1 to 2. spmc_exchange_version() is updated to take the new version into account when negotiating with a caller.
Configurations with SPMC at EL3 and S-EL2 supplies an SP manifest when booting OP-TEE, read the FF-A version to use from the manifest instead of using the hard coded version.
The configuration with SPMC at S-EL1, part of OP-TEE, keep the FF-A version at version 1.1 when configured with CFG_NS_VIRTUALIZATION=y as workaround to remain compatible with Xen. This workaround will not be needed after the next Xen release and can be removed then.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| ddec5d6b | 04-Dec-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: ffa: update FFA_CONSOLE_LOG_64 for v1.2 SPs
Update FFA_CONSOLE_LOG_64 to handle the ABI extension for FF-A v1.2. The extended ABI is only used for FF-A v1.2 SPs .
Signed-off-by: Jens Wiklande
core: ffa: update FFA_CONSOLE_LOG_64 for v1.2 SPs
Update FFA_CONSOLE_LOG_64 to handle the ABI extension for FF-A v1.2. The extended ABI is only used for FF-A v1.2 SPs .
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 750a54aa | 03-Dec-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: arm: ffa: add FF-A version 1.2 defines
Add defines for SMC IDs introduced with FF-A version 1.2.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.
core: arm: ffa: add FF-A version 1.2 defines
Add defines for SMC IDs introduced with FF-A version 1.2.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| d17db2af | 03-Dec-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: arm: ffa: use SMC Calling Convention 1.2
Add struct thread_smc_1_2_regs as a replacement for struct thread_smc_args when dealing with FF-A SMCs. struct thread_smc_1_2_regs covers the registers
core: arm: ffa: use SMC Calling Convention 1.2
Add struct thread_smc_1_2_regs as a replacement for struct thread_smc_args when dealing with FF-A SMCs. struct thread_smc_1_2_regs covers the registers x0-x17 to support passing arguments and results according to SMC Calling Convention (SMCCC) version 1.2.
The difference is that before this change x8-x17 couldn't be used as argument nor result and the content was preserved. With this patch are x8-x17 returned as zeroes. New FF-A SMCs can take and return values in the full range x0-x17.
64-bit SMCCC version 1.1 and earlier specified x4-x17 as unpredictable or scratch registers. FF-A has specified x0-x7 as argument and result registers, regardless of SMCCC. This has changed with SMCCC version 1.2 where the two standards harmonize on this.
struct thread_smc_1_2_regs is added in a 32-bit version for compatibility, but it only covers r0-r7.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 7d0f479e | 16-Sep-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: arm: mm: dynamic allocation of v7 translation tables
With CFG_DYN_CONFIG enabled allocate translation tables using the boot_mem_*() functions. Static allocation from global variables is still
core: arm: mm: dynamic allocation of v7 translation tables
With CFG_DYN_CONFIG enabled allocate translation tables using the boot_mem_*() functions. Static allocation from global variables is still used with CFG_DYN_CONFIG disabled.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| a28e4a0f | 09-Jul-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: arm: mm: dynamic allocation of LPAE translation tables
With CFG_DYN_CONFIG enabled allocate translation tables using the boot_mem_*() functions. Static allocation from global variables is stil
core: arm: mm: dynamic allocation of LPAE translation tables
With CFG_DYN_CONFIG enabled allocate translation tables using the boot_mem_*() functions. Static allocation from global variables is still used with CFG_DYN_CONFIG disabled.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 18715752 | 09-Jul-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: arm: mm: refactor LPAE translation table handling
Refactor translation table handling to use a more flexible layout of the translation tables in memory. Instead of relying on multidimensional
core: arm: mm: refactor LPAE translation table handling
Refactor translation table handling to use a more flexible layout of the translation tables in memory. Instead of relying on multidimensional array use helper functions to calculate the address of each translation table as needed.
Preparing for future changes, no change in behaviour.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| ef0d00c1 | 10-Jul-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: mm: extend temporary dummy memory map
core_init_mmu_map() uses a temporary dummy memory map for the virt_to_phys() and phys_to_virt() conversions to avoid asserting while setting up translatio
core: mm: extend temporary dummy memory map
core_init_mmu_map() uses a temporary dummy memory map for the virt_to_phys() and phys_to_virt() conversions to avoid asserting while setting up translation tables before the MMU is enabled. CFG_DYN_CONFIG will need a larger range of memory since translation tables might not be allocated from .nozi memory only. So for CFG_DYN_CONFIG extend of end of the unused memory range that the boot_mem_*() functions allocate memory from.
Introduce CFG_DYN_CONFIG, enabled by default if CFG_BOOT_MEM is enabled and CFG_WITH_PAGER disabled. CFG_DYN_CONFIG conflicts with CFG_WITH_PAGER since the pager uses a different mechanism for memory allocation.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 0799b137 | 16-Sep-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: arm: add boot mem paddings to the heap
Add the paddings added due to requested alignment in boot mem allocations to the heap.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-b
core: arm: add boot mem paddings to the heap
Add the paddings added due to requested alignment in boot mem allocations to the heap.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| c62a7972 | 16-Sep-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: boot_mem: keep track of padding
When boot_mem_alloc() allocates memory up to alignment - 1 number of bytes may have be skipped to satisfy the required alignment of the returned pointer. If the
core: boot_mem: keep track of padding
When boot_mem_alloc() allocates memory up to alignment - 1 number of bytes may have be skipped to satisfy the required alignment of the returned pointer. If the skipped bytes, or padding, is large enough, it's recorded in a list of padding. The list of paddings can be processed and consumed with boot_mem_foreach_padding(). This allows sufficiently large paddings to be added to for instance the heap instead of being wasted.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 6b61de6c | 16-Sep-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: boot_mem: allow NULL pointers while relocating
In boot_mem_relocate() when relocating registered pointers, allow the pointer to be NULL. NULL pointers are not relocated.
Signed-off-by: Jens W
core: boot_mem: allow NULL pointers while relocating
In boot_mem_relocate() when relocating registered pointers, allow the pointer to be NULL. NULL pointers are not relocated.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 7c9b8543 | 16-Sep-2024 |
Jens Wiklander <jens.wiklander@linaro.org> |
core: allow partially unmapped MEM_AREA_TEE_RAM_RW
Add special checks in phys_to_virt_tee_ram() to see that a virtual address indeed is mapped before return the address if the memory area is MEM_ARE
core: allow partially unmapped MEM_AREA_TEE_RAM_RW
Add special checks in phys_to_virt_tee_ram() to see that a virtual address indeed is mapped before return the address if the memory area is MEM_AREA_TEE_RAM_RW since the VCORE_FREE may be unmapped.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| a969e99e | 16-Jan-2025 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: mm: zero initialize tee_mm pool structures
Zero initialize tee_mm_pool_t instance when such pool is initialized. This change fixes an issue where phys_mem pool max_allocated field may contain
core: mm: zero initialize tee_mm pool structures
Zero initialize tee_mm_pool_t instance when such pool is initialized. This change fixes an issue where phys_mem pool max_allocated field may contain a fuzzy value because it was not zero-initialized when allocated by the commit referred below.
Fixes: c596d8359eb3 ("core: add phys_mem allocation functions") Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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| b565152e | 16-Jan-2025 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: rpmb: fix mutex in directory populate
Fix mutex unlocking in rpmb_fs_dir_populate() that should protect fat_entry_dir_deinit() execution.
Fixes: 5f68d7848fe8 ("core: RPMB FS: Caching for FAT
core: rpmb: fix mutex in directory populate
Fix mutex unlocking in rpmb_fs_dir_populate() that should protect fat_entry_dir_deinit() execution.
Fixes: 5f68d7848fe8 ("core: RPMB FS: Caching for FAT FS entries") Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| b8a9277e | 03-Jan-2025 |
Ed Tubbs <ectubbs@gmail.com> |
plat-rockchip: rk3588: add TRNG support
Add TRNG support for Rockchip rk3588
Signed-off-by: Ed Tubbs <ectubbs@gmail.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com> Acked-by: Jens Wik
plat-rockchip: rk3588: add TRNG support
Add TRNG support for Rockchip rk3588
Signed-off-by: Ed Tubbs <ectubbs@gmail.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 96e8f740 | 09-Jan-2025 |
Etienne Carriere <etienne.carriere@foss.st.com> |
core: rpmb: handle not-implemented error code on device probing
Consider that non-secure world may report TEE_ERROR_NOT_IMPLEMENTED error code on OPTEE_RPC_CMD_RPMB_PROBE_RESET RPC command when that
core: rpmb: handle not-implemented error code on device probing
Consider that non-secure world may report TEE_ERROR_NOT_IMPLEMENTED error code on OPTEE_RPC_CMD_RPMB_PROBE_RESET RPC command when that RPC command is not supported. This is needed to support U-Boot that provides this return code, at least up to its release tag v2025.01 [1].
Without this change, OP-TEE fails to communicate with U-Boot RPMB RPC service since RPMB probe capability was merged in OP-TEE (Fixes: tag below).
Link: https://source.denx.de/u-boot/u-boot/-/blame/v2025.01/drivers/tee/optee/supplicant.c?ref_type=tags#L96 [1] Reported-by: Gavin Liu <gavin.liu@mediatek.com> Closes: https://github.com/OP-TEE/optee_os/issues/7200 Fixes: 8dfdf3927214 ("core: rpmb: probe for kernel RPMB driver") Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 9145b71b | 07-Jan-2025 |
Tony Han <tony.han@microchip.com> |
drivers: microchip_pit: fix the length used for comparing the clock names
sizeof("syspll") equals to 7 with a character '\0' in count, adjust the length used for the comparison to obtain the expecte
drivers: microchip_pit: fix the length used for comparing the clock names
sizeof("syspll") equals to 7 with a character '\0' in count, adjust the length used for the comparison to obtain the expected result. Move the test of "parent" into the while loop to improve debug convenience.
Fixes: 8796ab4a984f ("drivers: microchip_pit: add driver for sama7g54's pit64b") Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| c1a7c898 | 07-Jan-2025 |
Tony Han <tony.han@microchip.com> |
drivers: microchip_pit: fix the path of "dt_driver.h" included
change "#include <dt_driver.h>" to "#include <kernel/dt_driver.h>" due to "dt_driver.h" is located at "core/include/kernel/" and the pa
drivers: microchip_pit: fix the path of "dt_driver.h" included
change "#include <dt_driver.h>" to "#include <kernel/dt_driver.h>" due to "dt_driver.h" is located at "core/include/kernel/" and the path is not in the include paths which would cause compile errors.
Fixes: 8796ab4a984f ("drivers: microchip_pit: add driver for sama7g54's pit64b") Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| d5749450 | 12-Oct-2024 |
Tony Han <tony.han@microchip.com> |
plat-sam: enable SCMI reset domain management protocol and rstctrl driver
Enable CFG_SCMI_MSG_RESET_DOMAIN and CFG_DRIVERS_RSTCTRL.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Etienn
plat-sam: enable SCMI reset domain management protocol and rstctrl driver
Enable CFG_SCMI_MSG_RESET_DOMAIN and CFG_DRIVERS_RSTCTRL.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 3f788a22 | 12-Oct-2024 |
Tony Han <tony.han@microchip.com> |
plat-sam: scmi_server: use SCMI reset to manage USB reset for sama7g5
Enable "reset domain management protocol", add reset domains to SCMI channel and add functions for SCMI reset domain.
Signed-of
plat-sam: scmi_server: use SCMI reset to manage USB reset for sama7g5
Enable "reset domain management protocol", add reset domains to SCMI channel and add functions for SCMI reset domain.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| 2befa23d | 12-Oct-2024 |
Tony Han <tony.han@microchip.com> |
drivers: atmel_rstc: probe RSTC with reset controller and reset lines
Update the type of RSTC driver to DT_DRIVER_RSTCTRL and probe RSTC with the concept of controller and lines.
Signed-off-by: Ton
drivers: atmel_rstc: probe RSTC with reset controller and reset lines
Update the type of RSTC driver to DT_DRIVER_RSTCTRL and probe RSTC with the concept of controller and lines.
Signed-off-by: Tony Han <tony.han@microchip.com> Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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