core: support for global shared buffers

Add support of allocating SHM shared with non-secure kernel
and exported to a non-secure userspace application.

Reviewed-by: Jens Wiklander <jens.wiklander@l

core: support for global shared buffers

Add support of allocating SHM shared with non-secure kernel
and exported to a non-secure userspace application.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>

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core: tee: update objectSize/keySize for ECDSA/ECDH Objects

objectSize/keySize was not getting updated when an ECDSA/ECDH
object was imported.
Updating the ObjectSize/keySize based on the EC Curve.

core: tee: update objectSize/keySize for ECDSA/ECDH Objects

objectSize/keySize was not getting updated when an ECDSA/ECDH
object was imported.
Updating the ObjectSize/keySize based on the EC Curve.

Fixes: https://github.com/OP-TEE/optee_os/issues/2386
Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: reformat OP-TEE images to stm32 format

OP-TEE core images are reformatted into a STM32 compliant format
expected by the platform flashing tools.

Signed-off-by: Etienne Carriere <etie

plat-stm32mp1: reformat OP-TEE images to stm32 format

OP-TEE core images are reformatted into a STM32 compliant format
expected by the platform flashing tools.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: stm32_uart driver

Used by platform stm32mp1.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <je

core: stm32_uart driver

Used by platform stm32mp1.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-stm32mp1: add initial support

Introduce platform stm32mp1 with board stm32mp1-stm32mp157c-ev1 based
on stm32mp1 SoC family integrating Arm Cortex-A7 technology. In its
default configuration, st

plat-stm32mp1: add initial support

Introduce platform stm32mp1 with board stm32mp1-stm32mp157c-ev1 based
on stm32mp1 SoC family integrating Arm Cortex-A7 technology. In its
default configuration, stm32mp1 OP-TEE core operates in a 256kB secure
RAM with pager support enabled.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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Remove get_rng_array()

Removes get_rng_array() in favor of crypto_rng_read() which always uses
the configured RNG implementation to draw random.

Reviewed-by: Jerome Forissier <jerome.forissier@lina

Remove get_rng_array()

Removes get_rng_array() in favor of crypto_rng_read() which always uses
the configured RNG implementation to draw random.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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libmpa: remove mpa_set_random_generator()

MPA is used in two configurations, either in kernel mode or in user mode.

In kernel mode random is always drawn with crypto_rng_read() and in
user mode ute

libmpa: remove mpa_set_random_generator()

MPA is used in two configurations, either in kernel mode or in user mode.

In kernel mode random is always drawn with crypto_rng_read() and in
user mode utee_cryp_random_number_generate() is used instead.

This patch makes the code easier to follow by replacing the call via a
function pointer to a normal function call instead.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add new RNG implementation

Adds a new cryptographically secure pseudo random number generator known
as Fortuna. The implementation is based on the description in [0]. This
implementation repla

core: add new RNG implementation

Adds a new cryptographically secure pseudo random number generator known
as Fortuna. The implementation is based on the description in [0]. This
implementation replaces the implementation in LTC which was used until
now.

Gathering of entropy has been refined with crypto_rng_add_event() to
better match how entropy is added to Fortuna. A enum crypto_rng_src
identifies the source of the event. The source also controls how the
event is added. There are two options available, queue it in a circular
buffer for later processing or adding it directly to a pool. The former
option is suitable when being called from an interrupt handler or some
other place where RPC to normal world is forbidden.

plat_prng_add_jitter_entropy_norpc() is removed and
plat_prng_add_jitter_entropy() is updated to use this new entropy source
scheme.

The configuration of LTC is simplified by this, now PRNG is always drawn
via prng_mpa_desc.

plat_rng_init() takes care of initializing the PRNG in order to allow
platforms to override or enhance the Fortuna integration.

[0] Link:https://www.schneier.com/academic/paperfiles/fortuna.pdf

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: split tee_pager_init()

Splits tee_pager_init() into tee_pager_set_alias_area() and
tee_pager_generate_authenc_key(). The former function is called where
tee_pager_init() used to be called and

core: split tee_pager_init()

Splits tee_pager_init() into tee_pager_set_alias_area() and
tee_pager_generate_authenc_key(). The former function is called where
tee_pager_init() used to be called and the latter function is called
after the crypto API and RNG has been initialized.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: don't divide by sizeof(*mem) for ddr nsec memory

Since the two addresses are already of type struct core_mmu_phys_mem, do
not divide by sizeof(struct core_mmu_phys_mem). This broke dynamic sha

core: don't divide by sizeof(*mem) for ddr nsec memory

Since the two addresses are already of type struct core_mmu_phys_mem, do
not divide by sizeof(struct core_mmu_phys_mem). This broke dynamic shared
memory on Juno r0, since nelem would be zero for two slots.

Tested on Juno r0.

Fixes: 2f82082fada3 ("core: add ddr overall register")
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Rouven Czerwinski <rouven@czerwinskis.de>

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plat-sunxi: Add plat-sunxi

Initial version support for Allwinner H2+ platform. Specific to Banana Pi
M2 zero board currently.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Je

plat-sunxi: Add plat-sunxi

Initial version support for Allwinner H2+ platform. Specific to Banana Pi
M2 zero board currently.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>

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core: add mdelay() function

checkpatch will check if udelay value is too large. Use udelay() to
implement mdelay() when we want to delay more than 10000 us.

Reviewed-by: Jens Wiklander <jens.wiklan

core: add mdelay() function

checkpatch will check if udelay value is too large. Use udelay() to
implement mdelay() when we want to delay more than 10000 us.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>

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core: drivers: serial8250_uart: Add DT support

Add DT support for serial8250 uart driver. The matchtable currently
supports allwinner H2+ SoC.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org

core: drivers: serial8250_uart: Add DT support

Add DT support for serial8250 uart driver. The matchtable currently
supports allwinner H2+ SoC.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>

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Add new platform for the TI K3 class of SoCs

Add platform 'k3' for the TI K3 family. These are ARMv8 devices
and are quite different from our line of existing ARMv7 OMAP style
SoCs, hence the new pl

Add new platform for the TI K3 class of SoCs

Add platform 'k3' for the TI K3 family. These are ARMv8 devices
and are quite different from our line of existing ARMv7 OMAP style
SoCs, hence the new platform.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: crypto: arm64 ce: update AES CBC routines

Update the Aarch64 Crypto Extension accelerated CBC encryption/decryption
routines to the latest upstream implementation in the Linux kernel
(v4.17-rc

core: crypto: arm64 ce: update AES CBC routines

Update the Aarch64 Crypto Extension accelerated CBC encryption/decryption
routines to the latest upstream implementation in the Linux kernel
(v4.17-rc7).

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey960)
CC: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Fixes: https://github.com/OP-TEE/optee_os/issues/2355
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix syscall_cryp_obj_get_attr() with null buffer

Prior to this patch when syscall_cryp_obj_get_attr() is called with a
NULL buffer to query buffer size the function returns
TEE_ERROR_ACCESS_DE

core: fix syscall_cryp_obj_get_attr() with null buffer

Prior to this patch when syscall_cryp_obj_get_attr() is called with a
NULL buffer to query buffer size the function returns
TEE_ERROR_ACCESS_DENIED while TEE_ERROR_SHORT_BUFFER is expected. This
patch fixes syscall_cryp_obj_get_attr() to return TEE_ERROR_SHORT_BUFFER
if supplied buffer parameter is NULL.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: crypto: cleanup and fix CE accelerated AES CTR

There is a problem with how the counter is incremented in our Aarch32
implementation of ce_aes_ctr_encrypt(). When 3 or more 16-byte blocks of
da

core: crypto: cleanup and fix CE accelerated AES CTR

There is a problem with how the counter is incremented in our Aarch32
implementation of ce_aes_ctr_encrypt(). When 3 or more 16-byte blocks of
data are processed, the counter is incremented one time too many and
invalid data is produced as a result [1].

More generally, the way the counter is handled is quite convoluted. It is
incremented:
- In the generic LibTomCrypt code in ctr_encrypt_sub(),
- In the Crypto Extension glue layer in aes_ctr_encrypt_nblocks(),
- In the CE accelerated assembly code in ce_aes_ctr_encrypt().
We can easily get rid of the second one. We can also avoid always calling
the non-accelerated function on the first block of data.

This commit simplifies the C code to reflect the following rules:
- The core encryption functions (accelerated or not) should use the
counter value as is to process the first block of data,
- They should increment it for each block that is processed and return it
as an output parameter

The AArch32 and AArch64 CE assembler implementations are updated to the
latest available in the upstream Linux kernel (v4.17-rc7), thus
incorporating further improvements/simplifications by Ard Biesheuvel.
These functions handle the counter as described above so they fit our use
case perfectly.

Fixes: [1] https://github.com/OP-TEE/optee_os/issues/2305
CC: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey960, 32/64, CE/no CE)
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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tee_ta_manager: remove unused function tee_ta_get_client_id()

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

plat-*/conf.mk: use $(call force, ...) to set CFG_TEE_CORE_NB_CORE

Except for very special cases (such as virtualization), the number of CPU
cores that can enter OP-TEE is a fixed number that depend

plat-*/conf.mk: use $(call force, ...) to set CFG_TEE_CORE_NB_CORE

Except for very special cases (such as virtualization), the number of CPU
cores that can enter OP-TEE is a fixed number that depends on the hardware
configuration and should not be configurable at build time.
Therefore, use $(call force,CFG_TEE_CORE_NB_CORE,<value>) to set the
value.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: introduce configuration flags for debug info and optimization

Introduces CFG_CC_OPTIMIZE_FOR_SIZE (default y) which selects the C
compiler flag -Os and -O0 otherwise, and CFG_DEBUG_INFO (defau

core: introduce configuration flags for debug info and optimization

Introduces CFG_CC_OPTIMIZE_FOR_SIZE (default y) which selects the C
compiler flag -Os and -O0 otherwise, and CFG_DEBUG_INFO (default y)
which selects the C compiler flag -g3 and assembler flag -g.

DEBUG=1 is kept for compatibility.

Being able to compile without -g is useful to get much better performance
from ccache thanks to its 'unify' option [1].

Link: https://github.com/ccache/ccache/blob/v3.4.2/doc/MANUAL.adoc#configuration-settings
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-imx: generic RAM layout for IMX7

PLATFORM=imx-mx7dsabresd

Name Before After
TEE_RAM_START be000000 be000000
TEE_RAM_VA_SIZE 00100000

plat-imx: generic RAM layout for IMX7

PLATFORM=imx-mx7dsabresd

Name Before After
TEE_RAM_START be000000 be000000
TEE_RAM_VA_SIZE 00100000 00100000
TEE_RAM_PH_SIZE 00100000 00100000
TA_RAM_START be100000 be100000
TA_RAM_SIZE 01d00000 01d00000
TEE_SHMEM_START bfe00000 bfe00000
TEE_SHMEM_SIZE 00200000 00200000
TZDRAM_BASE be000000 be000000
TZDRAM_SIZE 01e00000 01e00000
TZSRAM_BASE 00000000 00000000
TZSRAM_SIZE 00000000 00000000
TEE_LOAD_ADDR be000000 be000000
TEE_RAM_VA_SIZE 00100000 00100000

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>

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plat-imx: generic RAM layout for MX6SX

PLATFORM=imx-mx6sxsabreauto

Name Before After
TEE_RAM_START fe000000 fe000000
TEE_RAM_VA_SIZE 00100000 0

plat-imx: generic RAM layout for MX6SX

PLATFORM=imx-mx6sxsabreauto

Name Before After
TEE_RAM_START fe000000 fe000000
TEE_RAM_VA_SIZE 00100000 00100000
TEE_RAM_PH_SIZE 00100000 00100000
TA_RAM_START fe100000 fe100000
TA_RAM_SIZE 01d00000 01d00000
TEE_SHMEM_START ffe00000 ffe00000
TEE_SHMEM_SIZE 00200000 00200000
TZDRAM_BASE fe000000 fe000000
TZDRAM_SIZE 01e00000 01e00000
TZSRAM_BASE 00000000 00000000
TZSRAM_SIZE 00000000 00000000
TEE_LOAD_ADDR fe000000 fe000000
TEE_RAM_VA_SIZE 00100000 00100000

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>

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plat-imx: generic RAM layout for MX6UL and MX6ULL

PLATFORM=imx-mx6ulevk

Name Before After
TEE_RAM_START 9e000000 9e000000
TEE_RAM_VA_SIZE 00100000

plat-imx: generic RAM layout for MX6UL and MX6ULL

PLATFORM=imx-mx6ulevk

Name Before After
TEE_RAM_START 9e000000 9e000000
TEE_RAM_VA_SIZE 00100000 00100000
TEE_RAM_PH_SIZE 00100000 00100000
TA_RAM_START 9e100000 9e100000
TA_RAM_SIZE 01d00000 01d00000
TEE_SHMEM_START 9fe00000 9fe00000
TEE_SHMEM_SIZE 00200000 00200000
TZDRAM_BASE 9e000000 9e000000
TZDRAM_SIZE 01e00000 01e00000
TZSRAM_BASE 00000000 00000000
TZSRAM_SIZE 00000000 00000000
TEE_LOAD_ADDR 9e000000 9e000000
TEE_RAM_VA_SIZE 00100000 00100000

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>

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plat-imx: generic RAM layout for MX6Q, MX6D, MX6DL, MX6S

The 'after' values are computed with the fix to TA_RAM_SIZE.

PLATFORM=imx-mx6qsabresd CFG_WITH_PAGER=n

Name Before

plat-imx: generic RAM layout for MX6Q, MX6D, MX6DL, MX6S

The 'after' values are computed with the fix to TA_RAM_SIZE.

PLATFORM=imx-mx6qsabresd CFG_WITH_PAGER=n

Name Before After
TEE_RAM_START 4e000000 4e000000
TEE_RAM_VA_SIZE 00100000 00100000
TEE_RAM_PH_SIZE 00100000 00100000
TA_RAM_START 4e100000 4e100000
TA_RAM_SIZE 01e00000 01e00000
TEE_SHMEM_START 4ff00000 4ff00000
TEE_SHMEM_SIZE 00100000 00100000
TZDRAM_BASE 4e000000 4e000000
TZDRAM_SIZE 01f00000 01f00000
TZSRAM_BASE 00000000 00000000
TZSRAM_SIZE 00000000 00000000
TEE_LOAD_ADDR 4e000000 4e000000
TEE_RAM_VA_SIZE 00100000 00100000

PLATFORM=imx-mx6qsabresd CFG_WITH_PAGER=y

Name Before After
TEE_RAM_START 4e000000 4e000000
TEE_RAM_VA_SIZE 00100000 00100000
TEE_RAM_PH_SIZE 00100000 00100000
TA_RAM_START 4e100000 4e100000
TA_RAM_SIZE 01e00000 01e00000
TEE_SHMEM_START 4ff00000 4ff00000
TEE_SHMEM_SIZE 00100000 00100000
TZDRAM_BASE 4e000000 4e000000
TZDRAM_SIZE 01f00000 01f00000
TZSRAM_BASE 00000000 00000000
TZSRAM_SIZE 00000000 00000000
TEE_LOAD_ADDR 4e000000 4e000000
TEE_RAM_VA_SIZE 00100000 00100000

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>

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core: prevent user_ta resource to be unpaged

Function is_user_ta_ctx() is used by unpaged code. Prior this change,
the whole user_ta_ops structure fell into unpaged sections. This change
decreases t

core: prevent user_ta resource to be unpaged

Function is_user_ta_ctx() is used by unpaged code. Prior this change,
the whole user_ta_ops structure fell into unpaged sections. This change
decreases the unpaged size by few tenths of kBytes.

Below are extracts from mem_usage.py output on qemu_armv8 with
CFG_WITH_PAGER=y and CFG_TEE_CORE_DEBUG=n. Check the size of sections
.text and .rodata.

- Before the change:
RAM Usage 0E100000 - 0E166000 size 00066000 408 KiB 102 pages
.text 0E100000 - 0E1151E8 size 000151E8 84 KiB
.rodata 0E1151E8 - 0E117BD8 size 000029F0 10 KiB
*hole* 0E117BD8 - 0E118000 size 00000428 1 KiB
.data 0E118000 - 0E11A280 size 00002280 8 KiB
.bss 0E11A280 - 0E11CBD8 size 00002958 10 KiB
.heap1 0E11CBD8 - 0E120000 size 00003428 13 KiB
.nozi 0E120000 - 0E12D300 size 0000D300 52 KiB
.heap2 0E12D300 - 0E13A000 size 0000CD00 51 KiB
.text_init 0E13A000 - 0E13EEE0 size 00004EE0 19 KiB
.rodata_init 0E13EEE0 - 0E13FD10 size 00000E30 3 KiB
.rodata_pageable 0E13FD10 - 0E144080 size 00004370 16 KiB
.text_pageable 0E144080 - 0E166000 size 00021F80 135 KiB

- After the change:
RAM Usage 0E100000 - 0E167000 size 00067000 412 KiB 103 pages
.text 0E100000 - 0E108E48 size 00008E48 35 KiB
.rodata 0E108E48 - 0E10A3F0 size 000015A8 5 KiB
*hole* 0E10A3F0 - 0E10B000 size 00000C10 3 KiB
.data 0E10B000 - 0E10D278 size 00002278 8 KiB
*hole* 0E10D278 - 0E10D280 size 00000008 0 KiB
.bss 0E10D280 - 0E10FBE8 size 00002968 10 KiB
.heap1 0E10FBE8 - 0E110000 size 00000418 1 KiB
.nozi 0E110000 - 0E11D300 size 0000D300 52 KiB
.heap2 0E11D300 - 0E12D000 size 0000FD00 63 KiB
.text_init 0E12D000 - 0E133460 size 00006460 25 KiB
.rodata_init 0E133460 - 0E1342D0 size 00000E70 3 KiB
.rodata_pageable 0E1342D0 - 0E139A50 size 00005780 21 KiB
.text_pageable 0E139A50 - 0E167000 size 0002D5B0 181 KiB

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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