tee_ta_manager: remove unused function tee_ta_get_client_id()

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

plat-*/conf.mk: use $(call force, ...) to set CFG_TEE_CORE_NB_CORE

Except for very special cases (such as virtualization), the number of CPU
cores that can enter OP-TEE is a fixed number that depend

plat-*/conf.mk: use $(call force, ...) to set CFG_TEE_CORE_NB_CORE

Except for very special cases (such as virtualization), the number of CPU
cores that can enter OP-TEE is a fixed number that depends on the hardware
configuration and should not be configurable at build time.
Therefore, use $(call force,CFG_TEE_CORE_NB_CORE,<value>) to set the
value.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: introduce configuration flags for debug info and optimization

Introduces CFG_CC_OPTIMIZE_FOR_SIZE (default y) which selects the C
compiler flag -Os and -O0 otherwise, and CFG_DEBUG_INFO (defau

core: introduce configuration flags for debug info and optimization

Introduces CFG_CC_OPTIMIZE_FOR_SIZE (default y) which selects the C
compiler flag -Os and -O0 otherwise, and CFG_DEBUG_INFO (default y)
which selects the C compiler flag -g3 and assembler flag -g.

DEBUG=1 is kept for compatibility.

Being able to compile without -g is useful to get much better performance
from ccache thanks to its 'unify' option [1].

Link: https://github.com/ccache/ccache/blob/v3.4.2/doc/MANUAL.adoc#configuration-settings
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-imx: generic RAM layout for IMX7

PLATFORM=imx-mx7dsabresd

Name Before After
TEE_RAM_START be000000 be000000
TEE_RAM_VA_SIZE 00100000

plat-imx: generic RAM layout for IMX7

PLATFORM=imx-mx7dsabresd

Name Before After
TEE_RAM_START be000000 be000000
TEE_RAM_VA_SIZE 00100000 00100000
TEE_RAM_PH_SIZE 00100000 00100000
TA_RAM_START be100000 be100000
TA_RAM_SIZE 01d00000 01d00000
TEE_SHMEM_START bfe00000 bfe00000
TEE_SHMEM_SIZE 00200000 00200000
TZDRAM_BASE be000000 be000000
TZDRAM_SIZE 01e00000 01e00000
TZSRAM_BASE 00000000 00000000
TZSRAM_SIZE 00000000 00000000
TEE_LOAD_ADDR be000000 be000000
TEE_RAM_VA_SIZE 00100000 00100000

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>

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plat-imx: generic RAM layout for MX6SX

PLATFORM=imx-mx6sxsabreauto

Name Before After
TEE_RAM_START fe000000 fe000000
TEE_RAM_VA_SIZE 00100000 0

plat-imx: generic RAM layout for MX6SX

PLATFORM=imx-mx6sxsabreauto

Name Before After
TEE_RAM_START fe000000 fe000000
TEE_RAM_VA_SIZE 00100000 00100000
TEE_RAM_PH_SIZE 00100000 00100000
TA_RAM_START fe100000 fe100000
TA_RAM_SIZE 01d00000 01d00000
TEE_SHMEM_START ffe00000 ffe00000
TEE_SHMEM_SIZE 00200000 00200000
TZDRAM_BASE fe000000 fe000000
TZDRAM_SIZE 01e00000 01e00000
TZSRAM_BASE 00000000 00000000
TZSRAM_SIZE 00000000 00000000
TEE_LOAD_ADDR fe000000 fe000000
TEE_RAM_VA_SIZE 00100000 00100000

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>

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plat-imx: generic RAM layout for MX6UL and MX6ULL

PLATFORM=imx-mx6ulevk

Name Before After
TEE_RAM_START 9e000000 9e000000
TEE_RAM_VA_SIZE 00100000

plat-imx: generic RAM layout for MX6UL and MX6ULL

PLATFORM=imx-mx6ulevk

Name Before After
TEE_RAM_START 9e000000 9e000000
TEE_RAM_VA_SIZE 00100000 00100000
TEE_RAM_PH_SIZE 00100000 00100000
TA_RAM_START 9e100000 9e100000
TA_RAM_SIZE 01d00000 01d00000
TEE_SHMEM_START 9fe00000 9fe00000
TEE_SHMEM_SIZE 00200000 00200000
TZDRAM_BASE 9e000000 9e000000
TZDRAM_SIZE 01e00000 01e00000
TZSRAM_BASE 00000000 00000000
TZSRAM_SIZE 00000000 00000000
TEE_LOAD_ADDR 9e000000 9e000000
TEE_RAM_VA_SIZE 00100000 00100000

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>

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plat-imx: generic RAM layout for MX6Q, MX6D, MX6DL, MX6S

The 'after' values are computed with the fix to TA_RAM_SIZE.

PLATFORM=imx-mx6qsabresd CFG_WITH_PAGER=n

Name Before

plat-imx: generic RAM layout for MX6Q, MX6D, MX6DL, MX6S

The 'after' values are computed with the fix to TA_RAM_SIZE.

PLATFORM=imx-mx6qsabresd CFG_WITH_PAGER=n

Name Before After
TEE_RAM_START 4e000000 4e000000
TEE_RAM_VA_SIZE 00100000 00100000
TEE_RAM_PH_SIZE 00100000 00100000
TA_RAM_START 4e100000 4e100000
TA_RAM_SIZE 01e00000 01e00000
TEE_SHMEM_START 4ff00000 4ff00000
TEE_SHMEM_SIZE 00100000 00100000
TZDRAM_BASE 4e000000 4e000000
TZDRAM_SIZE 01f00000 01f00000
TZSRAM_BASE 00000000 00000000
TZSRAM_SIZE 00000000 00000000
TEE_LOAD_ADDR 4e000000 4e000000
TEE_RAM_VA_SIZE 00100000 00100000

PLATFORM=imx-mx6qsabresd CFG_WITH_PAGER=y

Name Before After
TEE_RAM_START 4e000000 4e000000
TEE_RAM_VA_SIZE 00100000 00100000
TEE_RAM_PH_SIZE 00100000 00100000
TA_RAM_START 4e100000 4e100000
TA_RAM_SIZE 01e00000 01e00000
TEE_SHMEM_START 4ff00000 4ff00000
TEE_SHMEM_SIZE 00100000 00100000
TZDRAM_BASE 4e000000 4e000000
TZDRAM_SIZE 01f00000 01f00000
TZSRAM_BASE 00000000 00000000
TZSRAM_SIZE 00000000 00000000
TEE_LOAD_ADDR 4e000000 4e000000
TEE_RAM_VA_SIZE 00100000 00100000

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Jordan Rhee <jordanrh@microsoft.com>
Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>

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core: prevent user_ta resource to be unpaged

Function is_user_ta_ctx() is used by unpaged code. Prior this change,
the whole user_ta_ops structure fell into unpaged sections. This change
decreases t

core: prevent user_ta resource to be unpaged

Function is_user_ta_ctx() is used by unpaged code. Prior this change,
the whole user_ta_ops structure fell into unpaged sections. This change
decreases the unpaged size by few tenths of kBytes.

Below are extracts from mem_usage.py output on qemu_armv8 with
CFG_WITH_PAGER=y and CFG_TEE_CORE_DEBUG=n. Check the size of sections
.text and .rodata.

- Before the change:
RAM Usage 0E100000 - 0E166000 size 00066000 408 KiB 102 pages
.text 0E100000 - 0E1151E8 size 000151E8 84 KiB
.rodata 0E1151E8 - 0E117BD8 size 000029F0 10 KiB
*hole* 0E117BD8 - 0E118000 size 00000428 1 KiB
.data 0E118000 - 0E11A280 size 00002280 8 KiB
.bss 0E11A280 - 0E11CBD8 size 00002958 10 KiB
.heap1 0E11CBD8 - 0E120000 size 00003428 13 KiB
.nozi 0E120000 - 0E12D300 size 0000D300 52 KiB
.heap2 0E12D300 - 0E13A000 size 0000CD00 51 KiB
.text_init 0E13A000 - 0E13EEE0 size 00004EE0 19 KiB
.rodata_init 0E13EEE0 - 0E13FD10 size 00000E30 3 KiB
.rodata_pageable 0E13FD10 - 0E144080 size 00004370 16 KiB
.text_pageable 0E144080 - 0E166000 size 00021F80 135 KiB

- After the change:
RAM Usage 0E100000 - 0E167000 size 00067000 412 KiB 103 pages
.text 0E100000 - 0E108E48 size 00008E48 35 KiB
.rodata 0E108E48 - 0E10A3F0 size 000015A8 5 KiB
*hole* 0E10A3F0 - 0E10B000 size 00000C10 3 KiB
.data 0E10B000 - 0E10D278 size 00002278 8 KiB
*hole* 0E10D278 - 0E10D280 size 00000008 0 KiB
.bss 0E10D280 - 0E10FBE8 size 00002968 10 KiB
.heap1 0E10FBE8 - 0E110000 size 00000418 1 KiB
.nozi 0E110000 - 0E11D300 size 0000D300 52 KiB
.heap2 0E11D300 - 0E12D000 size 0000FD00 63 KiB
.text_init 0E12D000 - 0E133460 size 00006460 25 KiB
.rodata_init 0E133460 - 0E1342D0 size 00000E70 3 KiB
.rodata_pageable 0E1342D0 - 0E139A50 size 00005780 21 KiB
.text_pageable 0E139A50 - 0E167000 size 0002D5B0 181 KiB

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm: support relocation type R_ARM_REL32

I have encounterd the relocation type R_ARM_REL32 in a shared library,
so implement it.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

core: arm: support relocation type R_ARM_REL32

I have encounterd the relocation type R_ARM_REL32 in a shared library,
so implement it.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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pta: add system pTA

Add system pTA, which provides misc. auxiliary services, extending
existing GlobalPlatform Core API.
Add a call for seeding entropy to the default RNG pool.

Reviewed-by: Jens Wi

pta: add system pTA

Add system pTA, which provides misc. auxiliary services, extending
existing GlobalPlatform Core API.
Add a call for seeding entropy to the default RNG pool.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>

show more ...

synquacer: Add DeveloperBox platform support

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

core: fix TA_RAM_SIZE in generic RAM layout

TA_RAM_SIZE subtracts TEE_RAM_VA_SIZE twice, resulting in
a gap in the memory map. This restores the memory map to what
it was before the generic layout c

core: fix TA_RAM_SIZE in generic RAM layout

TA_RAM_SIZE subtracts TEE_RAM_VA_SIZE twice, resulting in
a gap in the memory map. This restores the memory map to what
it was before the generic layout change.

PLATFORM=stm-b2260

Macro Pre-Generic-Layout Post-Generic-Layout With-This-Fix
TZDRAM_BASE 7e000000 7e000000 7e000000
TZDRAM_SIZE 01c00000 01c00000 01c00000
TEE_RAM_VA_SIZE 00100000 00100000 00100000
TA_RAM_START 7e100000 7e100000 7e100000
RA_RAM_SIZE 01b00000 *01a00000* 01b00000
TEE_SHMEM_START 7fc00000 7fc00000 7fc00000

Signed-off-by: Jordan Rhee <jordanrh@microsoft.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

show more ...

core: arm64: add support for dynamically linked TAs

Adds the missing bits to be able to load 64-bit dynamically linked TAs.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by:

core: arm64: add support for dynamically linked TAs

Adds the missing bits to be able to load 64-bit dynamically linked TAs.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (QEMUv8)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey960 32/64)
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: elf_load_dyn.c: prepare for arm64 support

Use generic structures (elf_shdr, elf_dyn and elf_sym) rather than
ELF32-specific ones (Elf32_Shdr, Elf32_Dyn and Elf32_Sym) to process
dependencies a

core: elf_load_dyn.c: prepare for arm64 support

Use generic structures (elf_shdr, elf_dyn and elf_sym) rather than
ELF32-specific ones (Elf32_Shdr, Elf32_Dyn and Elf32_Sym) to process
dependencies and symbol resolution. This is a first step towards 64-bit
support.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-marvell: support generic RAM layout

Move default secure and non-secure OP-TEE memory locations from
platform_config.h to conf.mk using the generic_ram_layout.

Marvell platforms memory location

plat-marvell: support generic RAM layout

Move default secure and non-secure OP-TEE memory locations from
platform_config.h to conf.mk using the generic_ram_layout.

Marvell platforms memory location and cores number are not configurable.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Kevin Peng <kevinp@marvell.com>

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plat-vexpress: qemu v8: increase default core count

Increase CFG_TEE_CORE_NB_CORE to 4 for qemu_armv8a. This is to allow
more extensive tests of multithreading.

Signed-off-by: Volodymyr Babchuk <vl

plat-vexpress: qemu v8: increase default core count

Increase CFG_TEE_CORE_NB_CORE to 4 for qemu_armv8a. This is to allow
more extensive tests of multithreading.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Tested-by: Volodymyr Babchuk <vlad.babchuk@gmail.com> (QEMU ARM v8)
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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tee_ree_fs: avoid race condition between fh usage/closing

It is possible that one core will call ree_fs_close_primitive()
while another is calling ree_fs_read_primitive(). This patch
prevents this b

tee_ree_fs: avoid race condition between fh usage/closing

It is possible that one core will call ree_fs_close_primitive()
while another is calling ree_fs_read_primitive(). This patch
prevents this by putting ree_fs_close_primitive under mutex.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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mpa_desc.c: rename rand() to mpa_rand()

In mpa_desc.c rename rand() to mpa_rand() to avoid conflict with the C99
function rand().

Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Etienne

mpa_desc.c: rename rand() to mpa_rand()

In mpa_desc.c rename rand() to mpa_rand() to avoid conflict with the C99
function rand().

Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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user_ta: add helper function free_utc() for unified cleanup

Add helper function free_utc(). This function will be called both from
error path in tee_ta_init_user_ta_session() and from user_ta_ctx_de

user_ta: add helper function free_utc() for unified cleanup

Add helper function free_utc(). This function will be called both from
error path in tee_ta_init_user_ta_session() and from user_ta_ctx_destroy().

Suggested-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey)

show more ...

user_ta: tee_ta_init_user_ta_session(): return if calloc fails

There is no sense to do cleanup if user TA context can't be
allocated. Return error immediately.

Signed-off-by: Volodymyr Babchuk <vla

user_ta: tee_ta_init_user_ta_session(): return if calloc fails

There is no sense to do cleanup if user TA context can't be
allocated. Return error immediately.

Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

user_ta: tee_ta_init_user_ta_session(): free mobj_exidx in error path

Fixes: b072193efb70 ("arm32: stack unwinding for dynamically linked TAs")

Suggested-by: Jerome Forissier <jerome.forissier@lina

user_ta: tee_ta_init_user_ta_session(): free mobj_exidx in error path

Fixes: b072193efb70 ("arm32: stack unwinding for dynamically linked TAs")

Suggested-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

user_ta: tee_ta_init_user_ta_session(): missing free_elfs() in error path

Fixes: c27907e1bc5a ("core: arm32: add support for dynamically linked TAs")

Suggested-by: Jerome Forissier <jerome.forissie

user_ta: tee_ta_init_user_ta_session(): missing free_elfs() in error path

Fixes: c27907e1bc5a ("core: arm32: add support for dynamically linked TAs")

Suggested-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Volodymyr Babchuk <vlad.babchuk@gmail.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

show more ...

plat-vexpress: qemu_*: no need to register non-secure DDR

Qemus force CFG_DT to y resulting in DTB to provide the REE system memory
range(s). No need to register REE memory for dynamic SHM support.

plat-vexpress: qemu_*: no need to register non-secure DDR

Qemus force CFG_DT to y resulting in DTB to provide the REE system memory
range(s). No need to register REE memory for dynamic SHM support.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-vexpress: move to generic RAM layout

FVP:
- Secure RAM [0600.0000 0800.0000[ configurable.
- Static SHM [8300.0000 8320.0000[ configurable.

Juno:
- Secure RAM [ff00.0000 ffff.8000[ configurabl

plat-vexpress: move to generic RAM layout

FVP:
- Secure RAM [0600.0000 0800.0000[ configurable.
- Static SHM [8300.0000 8320.0000[ configurable.

Juno:
- Secure RAM [ff00.0000 ffff.8000[ configurable.
Note trailing 32kByte reserved by SCP for DDR retraining.
- Static SHM [fee0.0000 ff00.0000[ configurable.

qemu_virt:
- Secure RAM [0e10.0000 0f00.0000[ configurable.
- Static SHM [7fe0.0000 8000.0000[ configurable.

qemu_armv8:
- Secure RAM [0.0e10.0000 0.0f00.0000[ configurable.
- Static SHM [0.ffe0.0000 1.0000.0000[ configurable.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

show more ...

plat-vexpress: qemu_virt: align DRAM0 end with qemu_armv8

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>