drivers: bnxt: Update TEMP_MEM region that was overlapped

Update TEMP_MEM region that was overlapped with BNXT_CRASH_SEC_MEM

Signed-off-by: Tony Poon <tony.poon@broadcom.com>
Signed-off-by: Sheetal

drivers: bnxt: Update TEMP_MEM region that was overlapped

Update TEMP_MEM region that was overlapped with BNXT_CRASH_SEC_MEM

Signed-off-by: Tony Poon <tony.poon@broadcom.com>
Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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pta: bcm: Add HW RNG PTA

Add PTA for hardware random number generator.
PTA Reads the random number from the RNG FIFO and passes to
user application.

Signed-off-by: Bharat Kumar Reddy Gooty <bharat.

pta: bcm: Add HW RNG PTA

Add PTA for hardware random number generator.
PTA Reads the random number from the RNG FIFO and passes to
user application.

Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>
Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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core: link.mk: deprecate tee{,-pager,-pageable}.bin

Deprecates the generated files tee.bin, tee-pager.bin and tee-pageable.bin.
The files can still be generated by supplying the complete output path

core: link.mk: deprecate tee{,-pager,-pageable}.bin

Deprecates the generated files tee.bin, tee-pager.bin and tee-pageable.bin.
The files can still be generated by supplying the complete output path as a
target to make.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: link.mk: use gen_tee_bin.py

Uses gen_tee_bin.py instead of objcopy and gen_hashed_bin.py.

Tested-by: Jerome Forissier <jerome@forissier.org> (HiKey960)
Reviewed-by: Jerome Forissier <jerome@f

core: link.mk: use gen_tee_bin.py

Uses gen_tee_bin.py instead of objcopy and gen_hashed_bin.py.

Tested-by: Jerome Forissier <jerome@forissier.org> (HiKey960)
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: bcm_sotp: No ECC bits for Section 0 to Section 3

- Hardware does not support ECC bits for SOTP section_0 to
section_3, i.e ROWS_0 to ROWS_20.
- Remove magic number and use platform provid

drivers: bcm_sotp: No ECC bits for Section 0 to Section 3

- Hardware does not support ECC bits for SOTP section_0 to
section_3, i.e ROWS_0 to ROWS_20.
- Remove magic number and use platform provided
SOTP_NO_ECC_ROWS macro.

Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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pta: bcm: Add PTA for secure watchdog

Add PTA for secure watchdog.
A userspace application uses this PTA to carry out
below operations:
- Initialize and configure secure watchdog
- Set timeout val

pta: bcm: Add PTA for secure watchdog

Add PTA for secure watchdog.
A userspace application uses this PTA to carry out
below operations:
- Initialize and configure secure watchdog
- Set timeout value
- Start and
- Stop watchdog

Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>
Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-bcm: Add Broadcom platform specific err log support

Add Broadcom platform specific err logging support

Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
Acked-by: Jerome Forissie

plat-bcm: Add Broadcom platform specific err log support

Add Broadcom platform specific err logging support

Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
Acked-by: Jerome Forissier <jerome@forissier.org>

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trace: Add weak platform tracer function

Add weak platform tracer function
This would allow each platform to carry out
plat specific logging, possibly to some media
for post-mortem analysis

Signed-

trace: Add weak platform tracer function

Add weak platform tracer function
This would allow each platform to carry out
plat specific logging, possibly to some media
for post-mortem analysis

Signed-off-by: Sheetal Tigadoli <sheetal.tigadoli@broadcom.com>
Reviewed-by: Jerome Forissier <jerome@forissier.org>

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core: imx: fix CFG_DRAM_BASE for i.MX7ulp

Change CFG_DRAM_BASE to 0x60000000 for i.MX7ulp

Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.c

core: imx: fix CFG_DRAM_BASE for i.MX7ulp

Change CFG_DRAM_BASE to 0x60000000 for i.MX7ulp

Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: imx: disable CAAM driver for i.MX6SL

CAAM is not available on i.MX6SL.

Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by:

core: imx: disable CAAM driver for i.MX6SL

CAAM is not available on i.MX6SL.

Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: imx: rename register files

Remove _regs from register header files. It is redundant since header
files are already in /registers folder.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
A

core: imx: rename register files

Remove _regs from register header files. It is redundant since header
files are already in /registers folder.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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imx: change imx8 prefixe to mx8

For consistency, change all imx8 prefixe to mx8.
This change affects:
* CFG_IMX8*
* platform flavors

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by:

imx: change imx8 prefixe to mx8

For consistency, change all imx8 prefixe to mx8.
This change affects:
* CFG_IMX8*
* platform flavors

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>

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core: fix check_mem_map() vs MEM_AREA_IDENTITY_MAP_RX

This patch updates check_mem_map() to recognize MEM_AREA_IDENTITY_MAP_RX
as part of secure only memory.

This fix is only needed with CFG_CORE_A

core: fix check_mem_map() vs MEM_AREA_IDENTITY_MAP_RX

This patch updates check_mem_map() to recognize MEM_AREA_IDENTITY_MAP_RX
as part of secure only memory.

This fix is only needed with CFG_CORE_ASLR=y and prevents an error like:
E/TC:0 0 check_mem_map:1166 Uhandled memtype 8
E/TC:0 0 Panic at core/arch/arm/mm/core_mmu.c:1167 <check_mem_map>

Fixes: 1385854b72c9 ("core: Add core memory type MEM_AREA_IDENTITY_MAP_RX")
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Tested-by: Jerome Forissier <jerome@forissier.org> (QEMU)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add support for CFG_CORE_ASLR

Adds support for CFG_CORE_ASLR to load TEE Core at a random address.
ASLR makes the exploitation of memory corruption vulnerabilities more
difficult.

Paging is c

core: add support for CFG_CORE_ASLR

Adds support for CFG_CORE_ASLR to load TEE Core at a random address.
ASLR makes the exploitation of memory corruption vulnerabilities more
difficult.

Paging is currently not supported with CFG_CORE_ASLR=y.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm grow MAX_XLAT_TABLES with ASLR

If CFG_CORE_ASLR=y increase MAX_XLAT_TABLES to cater for the added
identity region and also less optimal alignment of mappings.

Acked-by: Jerome Forissier <

core: arm grow MAX_XLAT_TABLES with ASLR

If CFG_CORE_ASLR=y increase MAX_XLAT_TABLES to cater for the added
identity region and also less optimal alignment of mappings.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: kern.ld.S: make ctors/dtors contiguous with other relro sections

Fixes error when linking with clang:
ld.lld: error: section: .ctors is not contiguous with other relro sections
ld.lld: error:

core: kern.ld.S: make ctors/dtors contiguous with other relro sections

Fixes error when linking with clang:
ld.lld: error: section: .ctors is not contiguous with other relro sections
ld.lld: error: section: .dtors is not contiguous with other relro sections

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: kern.ld.S: make .got RO after relocation

Moves .got section to after .rodata section.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro

core: kern.ld.S: make .got RO after relocation

Moves .got section to after .rodata section.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: kern.ld.S: provide start/end of relocations

- Adds __rel_start and __rel_end for Rel type of relocations used by
ARM32.
- Adds __rela_end and __rela_start for Rela type of relocations used b

core: kern.ld.S: provide start/end of relocations

- Adds __rel_start and __rel_end for Rel type of relocations used by
ARM32.
- Adds __rela_end and __rela_start for Rela type of relocations used by
ARM64.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: Add core memory type MEM_AREA_IDENTITY_MAP_RX

Adds another memory type, MEM_AREA_IDENTITY_MAP_RX, to enum
teecore_memtypes. MEM_AREA_IDENTITY_MAP_RX is used to represent memory
which is addit

core: Add core memory type MEM_AREA_IDENTITY_MAP_RX

Adds another memory type, MEM_AREA_IDENTITY_MAP_RX, to enum
teecore_memtypes. MEM_AREA_IDENTITY_MAP_RX is used to represent memory
which is additionally identity mapped while OP-TEE is mapped at a
non-identity mapped location. This is needed to support CFG_CORE_ASLR=y.

The link script is updated to collect functions and read-only data in
between __identity_map_init_start and __identity_map_init_end.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: generic_entry: add enable_mmu()

Adds the assembly function enable_mmu() which as the name suggests enables
MMU. The function writes configuration which has previously been prepared
by core_ini

core: generic_entry: add enable_mmu()

Adds the assembly function enable_mmu() which as the name suggests enables
MMU. The function writes configuration which has previously been prepared
by core_init_mmu_regs().

The now obsolete assembly functions cpu_mmu_enable(),
cpu_mmu_enable_icache() and cpu_mmu_enable_dcache() are removed since
they are fully covered by enable_mmu().

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add relocatable VCORE_START_VA

Adds VCORE_START_VA which is relocated to the new virtual address of the
start of the OP-TEE memory in case ASLR is configured. This define
should be used instea

core: add relocatable VCORE_START_VA

Adds VCORE_START_VA which is relocated to the new virtual address of the
start of the OP-TEE memory in case ASLR is configured. This define
should be used instead of TEE_RAM_START after the initial translation
tables has been created.

thread_get_user_kcode() and thread_get_user_kdata() are updated
accordingly.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add get_aslr_seed()

Adds get_aslr_seed() which reads "kaslr-seed" from "/secure-chosen" in
FDT. The seed is intended to use as input to ASLR, also known as,
randomized address space layout.

O

core: add get_aslr_seed()

Adds get_aslr_seed() which reads "kaslr-seed" from "/secure-chosen" in
FDT. The seed is intended to use as input to ASLR, also known as,
randomized address space layout.

Once successfully read the seed is zeroed out in the FDT to minimize the
risk of leaking the seed.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: refactor core_init_mmu_map() and helpers

Breaks up core_init_mmu_map() and some of its helper functions in
multiple smaller functions to make it easier to follow and later extend
the code.

Th

core: refactor core_init_mmu_map() and helpers

Breaks up core_init_mmu_map() and some of its helper functions in
multiple smaller functions to make it easier to follow and later extend
the code.

There are no changes in behaviour with the exception of how the memory
map is sorted at different stages.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: core_mmu.h: make page size and friends unsigned

Redefines mask and size for small pages (SMALL_PAGE_*),
CORE_MMU_USER_CODE_* and CORE_MMU_USER_PARAM_* to be of an unsigned
type in order to be

core: core_mmu.h: make page size and friends unsigned

Redefines mask and size for small pages (SMALL_PAGE_*),
CORE_MMU_USER_CODE_* and CORE_MMU_USER_PARAM_* to be of an unsigned
type in order to be compatible with vaddr_t and paddr_t.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: bugfix v7 core_mmu_entry_to_finer_grained()

The short descriptor table implementation of
core_mmu_entry_to_finer_grained() incorrectly assumes that allocated
translation tables are identity ma

core: bugfix v7 core_mmu_entry_to_finer_grained()

The short descriptor table implementation of
core_mmu_entry_to_finer_grained() incorrectly assumes that allocated
translation tables are identity mapped. That is fixed with this patch by
adding a missing virt_to_phys() on a newly allocated translation table.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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