hikey960: fix support for 4G & 6G boards

Since commit 4518cdc1ff64 ("core: arm64: introduce CFG_CORE_ARM64_PA_BITS")
platforms are required to define CFG_CORE_ARM64_PA_BITS if their physical
address

hikey960: fix support for 4G & 6G boards

Since commit 4518cdc1ff64 ("core: arm64: introduce CFG_CORE_ARM64_PA_BITS")
platforms are required to define CFG_CORE_ARM64_PA_BITS if their physical
address space extends beyond 4G. This was missing for HiKey960 4G & 6G
versions, which indeed have addresses beyond 4G.

Signed-off-by: Henrik Uhrenfeldt <henrik.uhrenfeldt@huawei.com>

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core: driver: Fix CAAM Hash - User Buffers

Fix the CAAM Hash driver when input/output buffers are User buffers
allocated on multiple Small Pages.

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com

core: driver: Fix CAAM Hash - User Buffers

Fix the CAAM Hash driver when input/output buffers are User buffers
allocated on multiple Small Pages.

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: CAAM driver User Buffer SGT create

CAAM Driver can operate directly with the User Buffer and in this
case, the buffer can be on non-contiguous physical page.

CAAM is using a DMA to load/st

drivers: CAAM driver User Buffer SGT create

CAAM Driver can operate directly with the User Buffer and in this
case, the buffer can be on non-contiguous physical page.

CAAM is using a DMA to load/store data from memory. The DMA is working
with physical address. In case of the User Buffer, if the buffer is
crossing multiple Small Page, a CAAM Scatter Gather Table needs to
be created to rebuild the physical memory chunks used by the User virtual
buffer.

Add a function to check if a buffer is a User buffer crossing mutliple
small page.
Add a function to create a SGT Table of the User buffer.

Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-amlogic: Add initial support for Amlogic platforms

This is the initial support for the Amlogic platforms.

Tested 64-bin mode on A113D (AXG) board using upstream TF-A BL31.

* xtest results (-l

plat-amlogic: Add initial support for Amlogic platforms

This is the initial support for the Amlogic platforms.

Tested 64-bin mode on A113D (AXG) board using upstream TF-A BL31.

* xtest results (-l 15):
| 44074 subtests of which 0 failed
| 96 test cases of which 0 failed
| 0 test cases were skipped
| TEE test application done!

* Compiled with:
| make PLATFORM=amlogic

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>

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core_mmu: fix warnings when CFG_CORE_DYN_SHM=n && CFG_SECURE_DATA_PATH=n

Static function pbuf_is_special_mem() is used only when dynamic shared
memory or secure data path are enabled. Add the proper

core_mmu: fix warnings when CFG_CORE_DYN_SHM=n && CFG_SECURE_DATA_PATH=n

Static function pbuf_is_special_mem() is used only when dynamic shared
memory or secure data path are enabled. Add the proper #ifdefs to fix
the following warning:

$ make -s CFG_CORE_DYN_SHM=n CFG_SECURE_DATA_PATH=n
core/arch/arm/mm/core_mmu.c:260:13: warning: ‘pbuf_is_special_mem’ defined but not used [-Wunused-function]
260 | static bool pbuf_is_special_mem(paddr_t pbuf, size_t len,
| ^~~~~~~~~~~~~~~~~~~

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: entry_fast.c: fix warning when CFG_CORE_DYN_SHM=n

When CFG_CORE_DYN_SHM=n and CFG_TEE_CORE_LOG_LEVEL<3 we have:

$ make -s CFG_CORE_DYN_SHM=n CFG_TEE_CORE_LOG_LEVEL=2
core/arch/arm/tee/entry

core: entry_fast.c: fix warning when CFG_CORE_DYN_SHM=n

When CFG_CORE_DYN_SHM=n and CFG_TEE_CORE_LOG_LEVEL<3 we have:

$ make -s CFG_CORE_DYN_SHM=n CFG_TEE_CORE_LOG_LEVEL=2
core/arch/arm/tee/entry_fast.c: In function ‘tee_entry_exchange_capabilities’:
core/arch/arm/tee/entry_fast.c:65:7: warning: unused variable ‘dyn_shm_en’ [-Wunused-variable]
65 | bool dyn_shm_en = false;
| ^~~~~~~~~~

Add __maybe_unused to get rid of the warning.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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libfdt: move to version v1.5.1

Imports upstream libfdt version v1.5.1 [1]. Things worthy of note:

- SPDX license identifiers were added upstream in commit 94f87cd5b7c5
("libfdt: Add dual GPL/BSD

libfdt: move to version v1.5.1

Imports upstream libfdt version v1.5.1 [1]. Things worthy of note:

- SPDX license identifiers were added upstream in commit 94f87cd5b7c5
("libfdt: Add dual GPL/BSD SPDX tags to files missing license text").
They conflict with those we have added locally in commit 1bb929836182
("Add SPDX license identifiers"). We added "BSD-2-Clause" while
upstream added "GPL-2.0-or-later OR BSD-2-Clause". This commit keeps
the upstream tags.

- At this stage we carry no local modification except for two minor
things enabling C99 compliance:
1. Zero sized arrays at the end of structs fdt_node_header and
fdt_property are changed from "[0]" to "[]",
2. An extra semicolon is removed after the static function
overlay_fixup_one_phandle().
These changes were in the initial import already, commit b908c67504cd
("Import libfdt v1.4.1").

Link: [1] https://github.com/dgibson/dtc/tree/v1.5.1/libfdt
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-imx: Add SA settings for i.MX6UL

The Secure Access register configures the access mode for non-TrustZone
aware DMA masters. To ensure that no DMA master can read the secure
memory for OP-TEE, w

plat-imx: Add SA settings for i.MX6UL

The Secure Access register configures the access mode for non-TrustZone
aware DMA masters. To ensure that no DMA master can read the secure
memory for OP-TEE, we set access for all masters except the
processor (Cortex-A7) to non-secure only and lock the settings
afterwards.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Reviewed-by: Clement Faure <clement.faure@nxp.com>

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plat-imx: add CSU SA register for i.MX6/7

CSU_SA is at the same offset for both i.MX6 and i.MX7, add it to both
register files.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Review

plat-imx: add CSU SA register for i.MX6/7

CSU_SA is at the same offset for both i.MX6 and i.MX7, add it to both
register files.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Reviewed-by: Clement Faure <clement.faure@nxp.com>

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Move core/include/config.h to lib/libutils/ext/include

In order to be able to use the IS_ENABLED() macro in user space
libraries, move config.h from core to libutils.

Signed-off-by: Jerome Forissie

Move core/include/config.h to lib/libutils/ext/include

In order to be able to use the IS_ENABLED() macro in user space
libraries, move config.h from core to libutils.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: arm64.h: add read_mpidr() macro

Adds the macro read_mpidr() to arm64.h to avoid ifdefs in code.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklan

core: arm64.h: add read_mpidr() macro

Adds the macro read_mpidr() to arm64.h to avoid ifdefs in code.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: read thread_vector_table from assembly

Reads and returns thread_vector_table directly from assembly instead of
saving the return value from generic_boot_init_primary(). With this
generic_boot_

core: read thread_vector_table from assembly

Reads and returns thread_vector_table directly from assembly instead of
saving the return value from generic_boot_init_primary(). With this
generic_boot_init_primary() is declared in the same way when configured
with or without TF-A.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: pseudo_ta: check size of mapped mobj

Add a check in copy_in_param() to see that the mobj is large enough
to hold the mapped parameter.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Sig

core: pseudo_ta: check size of mapped mobj

Add a check in copy_in_param() to see that the mobj is large enough
to hold the mapped parameter.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mobj_phys_get_va(): check offset is in range

Checks that the supplied offset is still within the range of the mobj.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wi

core: mobj_phys_get_va(): check offset is in range

Checks that the supplied offset is still within the range of the mobj.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mobj_reg_shm_get_va(): check offset is in range

Checks that the supplied offset is still within the range of the mobj.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens

core: mobj_reg_shm_get_va(): check offset is in range

Checks that the supplied offset is still within the range of the mobj.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: remove num_pages from struct mobj_reg_shm

Removes the redundant element num_pages from struct mobj_reg_shm.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander

core: remove num_pages from struct mobj_reg_shm

Removes the redundant element num_pages from struct mobj_reg_shm.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Remove TEE_OPERATION_EXTENSION

Commit 6a2e0a9fe2b9 ("utee: support prehashed RSA sign/ver without
ASN.1") has introduced TEE_OPERATION_EXTENSION in tee_api_defines.h with
value 0xF. This poses a cou

Remove TEE_OPERATION_EXTENSION

Commit 6a2e0a9fe2b9 ("utee: support prehashed RSA sign/ver without
ASN.1") has introduced TEE_OPERATION_EXTENSION in tee_api_defines.h with
value 0xF. This poses a couple of minor issues:

1. Values 0x00000009-0x7FFFFFFF are "Reserved for future use" according
to the TEE Internal Core API specification v1.2.1 (Table 5-6),

2. The meaning of this #define is not clear: "extension" is not a
kind of operation like "cipher", "MAC", "asymmetric signature" etc.
The algorithm added by the above commit is TEE_ALG_RSASSA_PKCS1_V1_5
which is an asymmetric signature and should therefore be associated with
TEE_OPERATION_ASYMMETRIC_SIGNATURE.

I suppose the operation value was added in a attempt to keep the
structure of algorithm identifiers as defined in the GP v1.1
specification, where some particular bits indicate some attributes of
the algorithm. This scheme has since been abandoned by GlobalPlatform so
there is no reason to keep it.

Therefore, this commit removes the TEE_OPERATION_EXTENSION macro and
makes a special case in the TEE_GET_CLASS() macro so that algorithm
TEE_ALG_RSASSA_PKCS1_V1_5 is associated with
TEE_OPERATION_ASYMMETRIC_SIGNATURE.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Gabor Szekely <szvgabor@gmail.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix assigned size of struct mobj_reg_shm

Prior to this patch a struct mobj_reg_shm was initialized with num_pages
* SMALL_PAGE_SIZE without taking page_offset into account. This patch
fixes th

core: fix assigned size of struct mobj_reg_shm

Prior to this patch a struct mobj_reg_shm was initialized with num_pages
* SMALL_PAGE_SIZE without taking page_offset into account. This patch
fixes that by subtracting the result of the multiplication above with
page_offset.

Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: calculate size/address cells with overlay

In case an external device tree overlay is configured within OP-TEE,
fdt_{size,address}_cells will return the defaults from the device tree
specificat

core: calculate size/address cells with overlay

In case an external device tree overlay is configured within OP-TEE,
fdt_{size,address}_cells will return the defaults from the device tree
specification. These will be wrong for 32-bit ARM platforms, instead
calculate them from the paddr_t size instead.

Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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virt: core_mmu: use nexus memory area for temporary map

If CFG_VIRTUALIZATION is enabled, page allocator code will
try to allocate pages from nexus sections, which were not
mapped by default.

Signe

virt: core_mmu: use nexus memory area for temporary map

If CFG_VIRTUALIZATION is enabled, page allocator code will
try to allocate pages from nexus sections, which were not
mapped by default.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: fix typo error in nsec ddr discovery

In core_mmu_set_discovered_nsec_ddr(), core_mmap_is_end_of_table
always returns false and the loop body cannot be executed, which
is unexpected.

Reviewed-

core: fix typo error in nsec ddr discovery

In core_mmu_set_discovered_nsec_ddr(), core_mmap_is_end_of_table
always returns false and the loop body cannot be executed, which
is unexpected.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Fangsuo Wu <fangsuowu@asrmicro.com>

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core: introduce a new memory type for external dtb image

When CFG_DT=y, the external dtb image is mapped as
IO_NSEC memory type in init_external_dt function,
which may conflicts with dynamic shared

core: introduce a new memory type for external dtb image

When CFG_DT=y, the external dtb image is mapped as
IO_NSEC memory type in init_external_dt function,
which may conflicts with dynamic shared memory check.
Below is the panic log with qemu boot:

E/TC:0 0 check_phys_mem_is_outside:333 Non-sec mem (0x40000000:0x3fe00000) overlaps map (type 13 0x40000000:0x100000)
E/TC:0 0 Panic at core/arch/arm/mm/core_mmu.c:334 <check_phys_mem_is_outside>
E/TC:0 0 TEE load address @ 0x1bd0f000

This patch introduces a new memory type MEM_AREA_EXT_DT
which is used to map external dtb image. This memory type
will be skipped over in core_mmu_set_discovered_nsec_ddr()
in order to avoid the above panic.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Fangsuo Wu <fangsuowu@asrmicro.com>

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core: fix compiling error if reserved SHM not used

Fix compiling error when only use dynamic shared memory
(i.e: CFG_CORE_DYN_SHM=y && CFG_CORE_RESERVED_SHM=n) with
CFG_SHMEM_START and CFG_SHMEM_SIZ

core: fix compiling error if reserved SHM not used

Fix compiling error when only use dynamic shared memory
(i.e: CFG_CORE_DYN_SHM=y && CFG_CORE_RESERVED_SHM=n) with
CFG_SHMEM_START and CFG_SHMEM_SIZE not defined.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Fangsuo Wu <fangsuowu@asrmicro.com>

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core: adjust nsec ddr memory size correctly

In carve_out_phys_mem(), when pa has the same address
with m[n].addr, the m[n].size should also be adjusted.

Reviewed-by: Jens Wiklander <jens.wiklander@

core: adjust nsec ddr memory size correctly

In carve_out_phys_mem(), when pa has the same address
with m[n].addr, the m[n].size should also be adjusted.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Fangsuo Wu <fangsuowu@asrmicro.com>

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core: ltc: sm2: add missing status check

crypto_acipher_sm2_pke_decrypt() fails to check a return status from
LibTomCrypt. Add the missing check.

Fixes: f9a78287dd12 ("core: ltc: add support for SM

core: ltc: sm2: add missing status check

crypto_acipher_sm2_pke_decrypt() fails to check a return status from
LibTomCrypt. Add the missing check.

Fixes: f9a78287dd12 ("core: ltc: add support for SM2 PKE")
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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