| cf23e962 | 09-Nov-2021 |
Jerome Forissier <jerome@forissier.org> |
crypto: build aes-gcm*.c files only when both AES and GCM are enabled
crypto/aes-gcm*.c need building only when both CFG_CRYPTO_AES and
CFG_AES_GCM are enabled.
Signed-off-by: Jerome Forissier <jer
crypto: build aes-gcm*.c files only when both AES and GCM are enabled
crypto/aes-gcm*.c need building only when both CFG_CRYPTO_AES and
CFG_AES_GCM are enabled.
Signed-off-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| b17cf5c8 | 21-Nov-2021 |
Etienne Carriere <etienne.carriere@linaro.org> |
core: dt_driver: debug trace if property not found
Adds a debug level trace message in dt_driver_device_from_node_idx_prop()
when unexpectedly not finding provider expected property in target node.
core: dt_driver: debug trace if property not found
Adds a debug level trace message in dt_driver_device_from_node_idx_prop()
when unexpectedly not finding provider expected property in target node.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 33b9b4b9 | 19-Nov-2021 |
Julien Masson <jmasson@baylibre.com> |
plat-mediatek: set SHMEM base address after TZDRAM
In order to avoid hole between TZDRAM and SHMEM memory, the Non-secure
static shared memory physical base address is set by default just
after the
plat-mediatek: set SHMEM base address after TZDRAM
In order to avoid hole between TZDRAM and SHMEM memory, the Non-secure
static shared memory physical base address is set by default just
after the secure RAM (TZDRAM):
SHMEM_START = TZDRAM_START + TZDRAM_SIZE
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Julien Masson <jmasson@baylibre.com>
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| 292b3186 | 19-Nov-2021 |
Julien Masson <jmasson@baylibre.com> |
plat-mediatek: define memory range
This patch registers the non-secure memory to support dynamic shm
registering.
The default RAM size has been set to 1 GiB and default RAM base
address set to 0x40
plat-mediatek: define memory range
This patch registers the non-secure memory to support dynamic shm
registering.
The default RAM size has been set to 1 GiB and default RAM base
address set to 0x40000000.
These values can be changed at compilation via CFG_DRAM_SIZE and
CFG_DRAM_BASE.
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Julien Masson <jmasson@baylibre.com>
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| 9e42008d | 22-Nov-2021 |
Joakim Bech <joakim.bech@linaro.org> |
config: add flag CFG_WARN_INSECURE
OP-TEE is a reference implementation for developers and device
manufacturers, which implies that there always is a need to fill in
missing pieces that cannot be do
config: add flag CFG_WARN_INSECURE
OP-TEE is a reference implementation for developers and device
manufacturers, which implies that there always is a need to fill in
missing pieces that cannot be done generically. The chipmakers often
have additional security configurations those needs to be configured
according to the chipmakers security guidelines and security
specifications.
To reduce the likelihood of running a vanilla configured OP-TEE we
introduce the flag CFG_WARN_INSECURE that will give warning messages in
the boot saying that the OP-TEE runs a configuration that might be
insecure. The intention is that the device manufacturer making the end
products should change the flag to "n" after implementing stubbed
functionality in OP-TEE and configuring their device according to the
chipmakers security guidelines and security specifications.
Signed-off-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Acked-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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|
| 5411b322 | 11-Nov-2021 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
crypto: se050: rename huk driver to die_id
The current HUK driver is not providing the platform Hardware Unique
Key but the DIE_ID.
This can logically be a source of confusion (and bugs) for many u
crypto: se050: rename huk driver to die_id
The current HUK driver is not providing the platform Hardware Unique
Key but the DIE_ID.
This can logically be a source of confusion (and bugs) for many users
not enabling this option.
This commit renames the huk.c file to die_id.c and replaces the
previous configuration option with another one that is semantically
accurate.
CFG_NXP_SE05X_HUK_DRV --> CFG_NXP_SE05X_DIEID_DRV
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
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| add5ac80 | 20-Oct-2021 |
Jorge Ramirez-Ortiz <jorge@foundries.io> |
crypto: se050: Foundries Plug-and-Trust release 0.0.4
Notice that rebasing the Plug-and-Trust stack to pick up the NXP
Plug-and-Trust 3.03.00 release broke backwards compatibility with
previous OP-T
crypto: se050: Foundries Plug-and-Trust release 0.0.4
Notice that rebasing the Plug-and-Trust stack to pick up the NXP
Plug-and-Trust 3.03.00 release broke backwards compatibility with
previous OP-TEE versions. This is why this commit includes the
necessary update to adaptors/apdu.c
https://github.com/foundriesio/plug-and-trust/releases/tag/v0.0.3
Also the v.0.0.4 release includes support for APDU raw frame
transmission to the secure element (a new interface).
The OP-TEE PTA that makes use of that functionality shall be merged
after this commit.
https://github.com/foundriesio/plug-and-trust/releases/tag/v0.0.4
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 58db16aa | 29-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
plat-sam: enable clock framework support
Enable clock framework support to be able to build sama5d2 clock tree.
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Clément Léger <cleme
plat-sam: enable clock framework support
Enable clock framework support to be able to build sama5d2 clock tree.
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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| 7f857cd6 | 18-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
drivers: add sub.mk for sam
Add sub.mk to for sam directory build.
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com> |
| 16521289 | 18-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
drivers: sam: add sama5d2 clock description
Add complete sama5d2 clock tree description which uses all the
previously described clocks.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acke
drivers: sam: add sama5d2 clock description
Add complete sama5d2 clock tree description which uses all the
previously described clocks.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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| 538f5068 | 18-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
drivers: sam: add at91 clock interface
Add interface to all clocks that are needed to describe sama5d2 clock
tree.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <
drivers: sam: add at91 clock interface
Add interface to all clocks that are needed to describe sama5d2 clock
tree.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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| 5558f7fc | 18-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
drivers: sam: add pmc clock registering
Add all functions that will be used for PMC clocks registration.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.fe
drivers: sam: add pmc clock registering
Add all functions that will be used for PMC clocks registration.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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| 5ee2fe59 | 18-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
drivers: sam: add at91_system clock driver
Add driver for system clock.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Bori
drivers: sam: add at91_system clock driver
Add driver for system clock.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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| 82444cc2 | 18-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
drivers: sam: add at91_utmi clock driver
Add driver for UTMI clock.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Br
drivers: sam: add at91_utmi clock driver
Add driver for UTMI clock.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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| 7bf8a43b | 18-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
drivers: sam: add at91_usb clock driver
Add driver for USB clocks.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Bre
drivers: sam: add at91_usb clock driver
Add driver for USB clocks.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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| 98226f4a | 18-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
drivers: sam: add at91_sckc clock driver
Add driver for slow clock controller.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-b
drivers: sam: add at91_sckc clock driver
Add driver for slow clock controller.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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| 162917ff | 18-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
drivers: sam: add at91_programmable clock driver
Add driver for programmable clocks.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
A
drivers: sam: add at91_programmable clock driver
Add driver for programmable clocks.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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| e48dcdad | 18-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
drivers: sam: add at91_plldiv clock driver
Add driver for PLLDIV.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Brez
drivers: sam: add at91_plldiv clock driver
Add driver for PLLDIV.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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| dd6be631 | 18-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
drivers: sam: add at91_pll clock driver
Add driver for PLL.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Brezillon
drivers: sam: add at91_pll clock driver
Add driver for PLL.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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| 1d665639 | 18-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
drivers: sam: add at91_peripheral clock driver
Add driver for periheral clocks.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-
drivers: sam: add at91_peripheral clock driver
Add driver for periheral clocks.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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| 6ea4e740 | 18-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
drivers: sam: add at91_master clock driver
Add driver for master clock.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Bori
drivers: sam: add at91_master clock driver
Add driver for master clock.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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| 2798ddd3 | 18-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
drivers: sam: add at91_main clock driver
Add driver for main clock.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Br
drivers: sam: add at91_main clock driver
Add driver for main clock.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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| b2d86a70 | 18-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
drivers: sam: add at91_i2s_mux clock driver
Add driver for I2S mux clock.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-b
drivers: sam: add at91_i2s_mux clock driver
Add driver for I2S mux clock.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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| 447e3228 | 18-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
drivers: sam: add at91_h32mx clock driver
Add driver for h32mx clock.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: C
drivers: sam: add at91_h32mx clock driver
Add driver for h32mx clock.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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| 1eb03c37 | 18-Jun-2021 |
Clément Léger <clement.leger@bootlin.com> |
drivers: sam: add at91_generated clock driver
Add driver for generated clocks.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-
drivers: sam: add at91_generated clock driver
Add driver for generated clocks.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
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