core: ffa: add thread_spmc_register_secondary_ep()

Adds thread_spmc_register_secondary_ep() which replaces the previous
platforms specific functions ffa_secondary_cpu_ep_register() in
plat-vexpress

core: ffa: add thread_spmc_register_secondary_ep()

Adds thread_spmc_register_secondary_ep() which replaces the previous
platforms specific functions ffa_secondary_cpu_ep_register() in
plat-vexpress and plat-totalcompute.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: imx: Calculate CFG_TZDRAM_START and CFG_NSEC_DDR_0_SIZE

Move assignement in order to calculate the value instead of
hardcoded.

0x2000000 is the sum of 0x01e00000 and 0x00200000

Signed-off-by

core: imx: Calculate CFG_TZDRAM_START and CFG_NSEC_DDR_0_SIZE

Move assignement in order to calculate the value instead of
hardcoded.

0x2000000 is the sum of 0x01e00000 and 0x00200000

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Clement Faure <clement.faure@nxp.com>

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crypto: drivers: se050: remove implicit dependency

The SE05X device is platform independent and therefore does not need
the iMX I2C driver but the actual driver for the particular platform
is connec

crypto: drivers: se050: remove implicit dependency

The SE05X device is platform independent and therefore does not need
the iMX I2C driver but the actual driver for the particular platform
is connected into.

Implementing these changes required a fix in the Plug-and-Trust tree
(the addition of a missing dependency), therefore we will also bump
the Plug-and-Trust version used in the Azure pipeline.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Acked-by: Jerome Forissier <jerome@forissier.org>

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plat-sam: add support for SAIC init

Initialize SAIC in main_init_gic() and add itr_core_handler() function
which calls atmel_saic_it_handle() to handle interrupts.

Acked-by: Jens Wiklander <jens.wi

plat-sam: add support for SAIC init

Initialize SAIC in main_init_gic() and add itr_core_handler() function
which calls atmel_saic_it_handle() to handle interrupts.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: atmel_saic: add SAIC driver

Add a driver to handle interrupt that are targeting the secure
interrupt controller. This driver will be used to handle watchdog and
matrix interrupts.

Acked-by

drivers: atmel_saic: add SAIC driver

Add a driver to handle interrupt that are targeting the secure
interrupt controller. This driver will be used to handle watchdog and
matrix interrupts.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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core: Add property to check feature PAUTH in TEE property set

Add an entry in TEE_PROPSET_TEE_IMPLEMENTATION for a boolean
property org.trustedfirmware.optee.cpu.feat_pauth_implemented.
The property

core: Add property to check feature PAUTH in TEE property set

Add an entry in TEE_PROPSET_TEE_IMPLEMENTATION for a boolean
property org.trustedfirmware.optee.cpu.feat_pauth_implemented.
The property is set true only if CFG_TA_PAUTH is configured and
the underlying CPU supports FEAT_PAuth/FEAT_PAuth2.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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Add basic pointer authentication support for TA's

APIAKey is used for usespace TA's where these keys are generated
for every TA at load time. The TEE core maintains the key value
for each TA is resp

Add basic pointer authentication support for TA's

APIAKey is used for usespace TA's where these keys are generated
for every TA at load time. The TEE core maintains the key value
for each TA is responsible for storing/restorign them during
switch to EL0 and back.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm64: Add registers and bits for pointer authentication support

The ARMv8.3 PAuth (pointer authentication) extension adds:

- Fields in register ID_AA64ISAR1 to report the presence of pointer
aut

arm64: Add registers and bits for pointer authentication support

The ARMv8.3 PAuth (pointer authentication) extension adds:

- Fields in register ID_AA64ISAR1 to report the presence of pointer
authentication functionality.
- Control bits in SCTLR_ELx to enable this functionality.
- New registers to hold the keys necessary for this
functionality.
- New ESR_ELx.EC codes used when the new instructions are affected by
configurable traps

These will be used in later patches as support for pointer
authentication is added.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-sam: psci: add support for suspend and idle.

Based on the previous work to add suspend on sama5d2 platform, add
the PSCI glue to call suspend function. psci_cpu_suspend() is used to
put the pla

plat-sam: psci: add support for suspend and idle.

Based on the previous work to add suspend on sama5d2 platform, add
the PSCI glue to call suspend function. psci_cpu_suspend() is used to
put the platform in light suspend mode (STANDBY) whereas
psci_system_suspend() puts the system into the suspend mode selected by
CFG_ATMEL_PM_SUSPEND_MODE at compile time.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: atmel_shdwc: add call to suspend init

Since there is no "suspend" controller per se and that the general
controller used for suspend is the shutdown controller, call suspend
init from shdwc

drivers: atmel_shdwc: add call to suspend init

Since there is no "suspend" controller per se and that the general
controller used for suspend is the shutdown controller, call suspend
init from shdwc driver.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: pm: sam: add suspend support

Add suspend support for sama5d2 platform. This support allows to use
all the available modes of suspend present on the sama5d2 platform:
- STANDBY
- ULP0
- ULP0

drivers: pm: sam: add suspend support

Add suspend support for sama5d2 platform. This support allows to use
all the available modes of suspend present on the sama5d2 platform:
- STANDBY
- ULP0
- ULP0 Fast
- ULP1
- BACKUP

By default, STANDBY mode is used as default suspend mode.
This support is meant to be used by PSCI.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: clk: sam: add suspend support

PMC register contents needs to be restored after resuming. Add support
for this using PM callbacks.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
A

drivers: clk: sam: add suspend support

PMC register contents needs to be restored after resuming. Add support
for this using PM callbacks.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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plat-sam: matrix: add suspend support

Matrix registers needs to be restored after resume. Add support for
suspend using PM callbacks.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-

plat-sam: matrix: add suspend support

Matrix registers needs to be restored after resume. Add support for
suspend using PM callbacks.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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plat-sam: set sram0 as secure

We are going to use the first 64K of SRAM0 to put the suspend code.
This is mandatory because SDRAM will be put in self refresh mode and
thus won't be accessible. at91b

plat-sam: set sram0 as secure

We are going to use the first 64K of SRAM0 to put the suspend code.
This is mandatory because SDRAM will be put in self refresh mode and
thus won't be accessible. at91bootstrap already sets this zone as
secure but we better enforce it to avoid anybody reading or writing
it.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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plat-sam: use more mmap regions

With upcoming suspend support, the default number of mmap regions is
too small to map all the needed regions. Increment this value to 24
to be a bit more comfortable.

plat-sam: use more mmap regions

With upcoming suspend support, the default number of mmap regions is
too small to map all the needed regions. Increment this value to 24
to be a bit more comfortable.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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arm32: add suspend/resume support for cortex-A5

Cortex-A5 has the same set of registers to be saved than cortex-A7. Use the
same code to save them and restore them.

Reviewed-by: Etienne Carriere <e

arm32: add suspend/resume support for cortex-A5

Cortex-A5 has the same set of registers to be saved than cortex-A7. Use the
same code to save them and restore them.

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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core: pm: add documentation for callback name parameter

Fixed missing documentation for name parameter.

Fixes: 502e23ad523 ("core: pm: add a name to registered pm_callback_handle")
Reviewed-by: Eti

core: pm: add documentation for callback name parameter

Fixed missing documentation for name parameter.

Fixes: 502e23ad523 ("core: pm: add a name to registered pm_callback_handle")
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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core: panic at unexpected smc return

Certain smc's are not expected to return. Prior to this patch in order
to guard against unexpected return a "b ." instruction was added after
each such smc to at

core: panic at unexpected smc return

Certain smc's are not expected to return. Prior to this patch in order
to guard against unexpected return a "b ." instruction was added after
each such smc to at least capture the cpu. With the introduction of FF-A
TF-A may in case there's a mismatch between OP-TEE and TF-A
configuration return some error code when an unrecognized smc is
encountered. The result is typically that the boot hangs after the print:
I/TC: Primary CPU switching to normal world boot

To help diagnosing such errors a call to panic is added after
each smc which isn't expected to return. The result becomes instead:
I/TC: Primary CPU switching to normal world boot
E/TC:0 Panic at core/arch/arm/kernel/boot.c:122 <__panic_at_smc_return>
E/TC:0 TEE load address @ 0xe100000
E/TC:0 Call stack:
E/TC:0 0x0e10d23c
E/TC:0 0x0e124848
E/TC:0 0x0e10be60

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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zynqmp: zcu102: Fix DDR memory size to 4 GiB

Xilinx ZCU102 board has 4 GiB of DDR memory and size must be configured
properly in order for dynamic shared memory feature to work.

Without it followin

zynqmp: zcu102: Fix DDR memory size to 4 GiB

Xilinx ZCU102 board has 4 GiB of DDR memory and size must be configured
properly in order for dynamic shared memory feature to work.

Without it following error might be present during kernel startup:

E/TC:0 0 std_smc_entry:183 Bad arg address 0x803989000

When compiling for 32 bits only first 2 GiB is available.

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Ricardo Salveti <ricardo@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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zynqmp: platform: make it possible to configure DDR size more flexible

Default DDR size comes from platform selection.

If only DDR size is different it is possible to override it with
setting CFG_D

zynqmp: platform: make it possible to configure DDR size more flexible

Default DDR size comes from platform selection.

If only DDR size is different it is possible to override it with
setting CFG_DDR_SIZE.

Automatic configuration of DDR memory mappings can also be done by device
tree (CFG_DT=y) and by overriding if necessary memory address for device
tree (CFG_DT_ADDR).

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Ricardo Salveti <ricardo@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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zynqmp: platform: configure default device tree address

Xilinx has selected 0x100000 as default memory address for device tree.

Configure it by default and make it possible to override it (CFG_DT_A

zynqmp: platform: configure default device tree address

Xilinx has selected 0x100000 as default memory address for device tree.

Configure it by default and make it possible to override it (CFG_DT_ADDR).

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Ricardo Salveti <ricardo@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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zynqmp: platform: configure physical address space size

ZynqMP has several operation modes for physical address mapping:
32 bit mode, 36 bits and 40 bits

When compiling for 64 bits use full 40 bits

zynqmp: platform: configure physical address space size

ZynqMP has several operation modes for physical address mapping:
32 bit mode, 36 bits and 40 bits

When compiling for 64 bits use full 40 bits mode as default to support all
features of the chip.

Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Ricardo Salveti <ricardo@foundries.io>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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arm: Add Aspeed AST2600 platform support

Aspeed AST2600 is a dual-core SoC with ARM Cortex-A7 CPU.
This patch adds the platform support for AST2600 to execute
32-bits OP-TEE on top of TrustZone feat

arm: Add Aspeed AST2600 platform support

Aspeed AST2600 is a dual-core SoC with ARM Cortex-A7 CPU.
This patch adds the platform support for AST2600 to execute
32-bits OP-TEE on top of TrustZone features.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: use generic clock API in SCMI server

Replaces use of ST specific stm32mp_clk_xxx() clocks functions in
favor to OP-TEE generic clock API functions clk_xxx() using
struct clk * as cloc

plat-stm32mp1: use generic clock API in SCMI server

Replaces use of ST specific stm32mp_clk_xxx() clocks functions in
favor to OP-TEE generic clock API functions clk_xxx() using
struct clk * as clock references. Updates STM32MP1 SCMI server.

Reviewed-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stm32_rng: use generic clock API

Replaces use of ST specific stm32mp_clk_xxx() clocks functions in
favor to OP-TEE generic clock API functions clk_xxx() using
struct clk * as clock referenc

drivers: stm32_rng: use generic clock API

Replaces use of ST specific stm32mp_clk_xxx() clocks functions in
favor to OP-TEE generic clock API functions clk_xxx() using
struct clk * as clock references. Updates STM32 RNG driver.

Reviewed-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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