| 876826f3 | 15-Feb-2021 |
Gabriel Fernandez <gabriel.fernandez@foss.st.com> |
core: dt: add kernel DT API to retrieved device information from DT
Add _fdt_read_uint32_array(), _fdt_read_uint32(), _fdt_read_uint32_default(), _fdt_check_node() functions.
Acked-by: Etienne Carr
core: dt: add kernel DT API to retrieved device information from DT
Add _fdt_read_uint32_array(), _fdt_read_uint32(), _fdt_read_uint32_default(), _fdt_check_node() functions.
Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
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| 0f8347dc | 14-Mar-2022 |
Clement Faure <clement.faure@nxp.com> |
core: imx: generate uImage for imx6 and imx7 platforms
In the standard NXP BSP boot-flow, for imx6 and imx7 platforms (ARMv7), optee-os is booted by U-Boot as a uImage file. The generation of this u
core: imx: generate uImage for imx6 and imx7 platforms
In the standard NXP BSP boot-flow, for imx6 and imx7 platforms (ARMv7), optee-os is booted by U-Boot as a uImage file. The generation of this uImage requires: - optee-os load address. This address is fetched in the tee.elf file with readelf. - mkimage u-boot-tools. This tool takes the load address and the tee-raw.bin as an input to generate the uImage uTee.
Signed-off-by: Clement Faure <clement.faure@nxp.com> Acked-by: Jerome Forissier <jerome@forissier.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 7e8d05e4 | 23-Feb-2022 |
Jelle Sels <jelle.sels@arm.com> |
core: sp: Pass manifest fdt to SP
Pass the SP manifest fdt to the SP inside the info struct. To be able to pass the manifest we allocate and map a new page to the SP and copy the fdt inside this pag
core: sp: Pass manifest fdt to SP
Pass the SP manifest fdt to the SP inside the info struct. To be able to pass the manifest we allocate and map a new page to the SP and copy the fdt inside this page. This is done to make sure that no other data in the same page as the original fdt is leaked to the SP. After the SP is done initializing we free the page from the SP.
Signed-off-by: Jelle Sels <jelle.sels@arm.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 68f03d28 | 22-Feb-2022 |
Jelle Sels <jelle.sels@arm.com> |
core: sp: Add magic value into info parameter
The info parameter passed to a SP at initialization should have the magic value set to "FF-A".
Signed-off-by: Jelle Sels <jelle.sels@arm.com> Acked-by:
core: sp: Add magic value into info parameter
The info parameter passed to a SP at initialization should have the magic value set to "FF-A".
Signed-off-by: Jelle Sels <jelle.sels@arm.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 28710257 | 21-Feb-2022 |
Jelle Sels <jelle.sels@arm.com> |
core: sp: check manifest fdt
Check the SPs manifest fdt file to make sure that the correct manifest is loaded for the SP.
Signed-off-by: Jelle Sels <jelle.sels@arm.com> Acked-by: Jens Wiklander <je
core: sp: check manifest fdt
Check the SPs manifest fdt file to make sure that the correct manifest is loaded for the SP.
Signed-off-by: Jelle Sels <jelle.sels@arm.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| e23cd783 | 31-Jan-2022 |
Jelle Sels <jelle.sels@arm.com> |
core: sp: Append fdt manifest to SP image
Sp use a manifest file that define information about the SP. A device tree (fdt) will be used as a manifest file. This is in line with the Hafnium SPMC mani
core: sp: Append fdt manifest to SP image
Sp use a manifest file that define information about the SP. A device tree (fdt) will be used as a manifest file. This is in line with the Hafnium SPMC manifest format.
The fdt will be appended to the SP image by adding a --manifest flag to the scripts/ts_bin_to_c.py script.
Link: https://trustedfirmware-a.readthedocs.io/en/latest/components/ffa-manifest-binding.html Signed-off-by: Jelle Sels <jelle.sels@arm.com> Acked-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 3176f4d1 | 09-Mar-2022 |
Jerome Forissier <jerome@forissier.org> |
core: crypto: fix key generation for SM2 DSA and SM2 PKE
TEE_GenerateKey() returns TEE_ERROR_BAD_FORMAT when the object type is TEE_TYPE_SM2_DSA_KEYPAIR or TEE_TYPE_SM2_KEP_KEYPAIR. Only TEE_TYPE_SM
core: crypto: fix key generation for SM2 DSA and SM2 PKE
TEE_GenerateKey() returns TEE_ERROR_BAD_FORMAT when the object type is TEE_TYPE_SM2_DSA_KEYPAIR or TEE_TYPE_SM2_KEP_KEYPAIR. Only TEE_TYPE_SM2_PKE_KEYPAIR is accepted, which is clearly wrong as per the GlobalPlatform specification. Fix that by adding the missing entries to syscall_obj_generate_key().
Signed-off-by: Jerome Forissier <jerome@forissier.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| c2e89f8d | 09-Mar-2022 |
Jerome Forissier <jerome@forissier.org> |
core: crypto: sm2: remove TEE_ATTR_ECC_CURVE attribute from SM2 keys
SM2 key objects should not have a TEE_ATTR_ECC_CURVE attribute. For example, the GP specification states that TEE_GenerateKey() c
core: crypto: sm2: remove TEE_ATTR_ECC_CURVE attribute from SM2 keys
SM2 key objects should not have a TEE_ATTR_ECC_CURVE attribute. For example, the GP specification states that TEE_GenerateKey() can be called with no attribute for the various SM2 algorithms. The current implementation uses the same attribute templates than generic ECC algorithms, which is wrong. Define specific variants for SM2 so that TEE_ATTR_ECC_CURVE is not required when generating or populating SM2 keys and is not output either by TEE_GetObjectBufferAttribute().
Signed-off-by: Jerome Forissier <jerome@forissier.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| ecf9194d | 09-Mar-2022 |
Jerome Forissier <jerome@forissier.org> |
core: ltc: sm2: use proper curve during key generation
TEE_GenerateKey() generates an invalid key pair for SM2: the point is not on the curve, it is on the NIST P256 curve instead. Fix this by looki
core: ltc: sm2: use proper curve during key generation
TEE_GenerateKey() generates an invalid key pair for SM2: the point is not on the curve, it is on the NIST P256 curve instead. Fix this by looking up the proper curve name before key generation.
Link: https://github.com/OP-TEE/optee_os/issues/5211 Signed-off-by: Jerome Forissier <jerome@forissier.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| 3002cbb0 | 09-Mar-2022 |
Jerome Forissier <jerome@forissier.org> |
core: ltc: sm2: set curve by default when key type is SM2
crypto_asym_alloc_ecc_keypair() and crypto_asym_alloc_ecc_public_key() should set the curve field of the ecc_key structure to TEE_ECC_CURVE_
core: ltc: sm2: set curve by default when key type is SM2
crypto_asym_alloc_ecc_keypair() and crypto_asym_alloc_ecc_public_key() should set the curve field of the ecc_key structure to TEE_ECC_CURVE_SM2 when the key type is one of TEE_TYPE_SM2_{DSA,KEP,PKE}_KEYPAIR because the user is not supposed to provide any TEE_ATTR_ECC_CURVE attribute, contrary to other ECC algorithms.
Signed-off-by: Jerome Forissier <jerome@forissier.org> Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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| e31a75b3 | 15-Mar-2022 |
Lejia Zhang <zhanlej@gmail.com> |
core: mm: fix mobj_shm_ops support .get_cattr()
ftrace use static shared memory returns an object of type mobj_shm_ops. But the get_cattr function is not implemented in mobj_shm_ops.This will cause
core: mm: fix mobj_shm_ops support .get_cattr()
ftrace use static shared memory returns an object of type mobj_shm_ops. But the get_cattr function is not implemented in mobj_shm_ops.This will cause ftrace to not work properly.
Signed-off-by: Lejia Zhang <zhanlej@gmail.com> Suggested-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 7e05ec25 | 27-Oct-2021 |
Jerome Forissier <jerome@forissier.org> |
core: pta: add remote attestation PTA
Add a PTA to perform remote attestation of user space TAs and TEE core memory. Enabled with CFG_ATTESTATION_PTA=y. Four commands are defined:
- PTA_ATTESTATION
core: pta: add remote attestation PTA
Add a PTA to perform remote attestation of user space TAs and TEE core memory. Enabled with CFG_ATTESTATION_PTA=y. Four commands are defined:
- PTA_ATTESTATION_GET_PUBKEY
Returns the public RSA key used to sign the measurements generated by the other commands. The key pair is generated on first call (any command) and saved to secure storage. It is therefore device-specific.
- PTA_ATTESTATION_GET_TA_SHDR_DIGEST
Returns the digest found in the secure header (struct shdr) of a TA or trusted shared library given its UUID.
- PTA_ATTESTATION_HASH_TA_MEMORY
This command must be called by a user space TA (not a CA). It computes a hash of the memory pages that belong to the caller and contain code or read-only data. This hash is therefore a runtime measurement of the TA execution environment, including shared libraries (if any). It can be used to remotely attest that the device is running untampered TA code.
- PTA_ATTESTATION_HASH_TEE_MEMORY
Returns a hash of the TEE OS core (.text and .rodata sections, less the small part of .text that may be modified at boot). Similar to PTA_ATTESTATION_HASH_TA_MEMORY, the hash is computed each time the command is called, so that the result reflects the actual memory content.
Signed-off-by: Jerome Forissier <jerome@forissier.org> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 1aae2c8e | 19-Jan-2022 |
Jerome Forissier <jerome@forissier.org> |
core: pager: export __{text,rodata}_{init,pageable}_{start,end}
Add symbols __text_pageable_start, __text_pageable_end, __rodata_pageable_start and __rodata_pageable_end. They will later be used by
core: pager: export __{text,rodata}_{init,pageable}_{start,end}
Add symbols __text_pageable_start, __text_pageable_end, __rodata_pageable_start and __rodata_pageable_end. They will later be used by the attestation PTA.
Signed-off-by: Jerome Forissier <jerome@forissier.org> Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| f1fee325 | 04-Jan-2022 |
Jerome Forissier <jerome@forissier.org> |
core: arm64: aslr: pass '-z text' linker option
On arm64, all the relocations in read-only segments have been fixed in previous commits, pass the '-z text' linker option to detect if some unexpected
core: arm64: aslr: pass '-z text' linker option
On arm64, all the relocations in read-only segments have been fixed in previous commits, pass the '-z text' linker option to detect if some unexpected relocations are introduced by mistake.
Signed-off-by: Jerome Forissier <jerome@forissier.org> Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 39e8c200 | 01-Feb-2022 |
Jerome Forissier <jerome@forissier.org> |
core: tag ops structures with __relrodata_unpaged
Global structures currently tagged with __rodata_unpaged need to use __relrodata_unpaged instead because they contain pointers which are subject to
core: tag ops structures with __relrodata_unpaged
Global structures currently tagged with __rodata_unpaged need to use __relrodata_unpaged instead because they contain pointers which are subject to relocation when CFG_CORE_ASLR=y. Doing so moves them out of .rodata which will now stay unmodified even with ASLR turned on.
Signed-off-by: Jerome Forissier <jerome@forissier.org> Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 487f8cd2 | 01-Feb-2022 |
Jerome Forissier <jerome@forissier.org> |
core: compiler.h: introduce __relrodata_unpaged(x)
Introduce macro __relrodata_unpaged(x) to mark data that need to be unpaged and are essentially read-only but may contain relocations when ASLR is
core: compiler.h: introduce __relrodata_unpaged(x)
Introduce macro __relrodata_unpaged(x) to mark data that need to be unpaged and are essentially read-only but may contain relocations when ASLR is enabled, hence "relocatable read-only". When ASLR is turned off, the macro is identical to __rodata_unpaged(x). When ASLR is on however, the data is emitted in section .data.rel.ro.__unpaged.x which is later gathered by the linker file into the output section .data.rel.ro which is mapped read only at runtime (after relocations are processed) and is also unpaged (when pager is enabled).
Signed-off-by: Jerome Forissier <jerome@forissier.org> Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| c0af48e6 | 03-Jan-2022 |
Jerome Forissier <jerome@forissier.org> |
core: kern.ld.S: move .scattered_array* into .data.rel.ro
Moves the symbols tagged with .scattered_array* from the .rodata output section into a new output section: .data.rel.ro, which is also writ
core: kern.ld.S: move .scattered_array* into .data.rel.ro
Moves the symbols tagged with .scattered_array* from the .rodata output section into a new output section: .data.rel.ro, which is also writeable (hence the suppression of __SECTION_FLAGS_RODATA in scattered_array.h) but placed in tee.elf to be mapped read-only after relocations are applied. The new section is created only when core ASLR is enabled, otherwise no relocation can occur and we can keep the previous code.
Signed-off-by: Jerome Forissier <jerome@forissier.org> Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 9aec76b6 | 14-Dec-2021 |
Jerome Forissier <jerome@forissier.org> |
core: arm64: move boot_mmu_config and cached_mem_end to .identity_map.data
boot_mmu_config and cached_mem_end need to be reachable from the identity map, hence contained in .text, but they are not s
core: arm64: move boot_mmu_config and cached_mem_end to .identity_map.data
boot_mmu_config and cached_mem_end need to be reachable from the identity map, hence contained in .text, but they are not strictly read-only. Therefore move them to .identity_map.data.
Signed-off-by: Jerome Forissier <jerome@forissier.org> Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 889fb568 | 14-Dec-2021 |
Jerome Forissier <jerome@forissier.org> |
core: add delimited area in .text to store data
A few variables such as boot_mmu_config are stored within the .text section of tee.elf, because they need to be reachable from the identity mapping wh
core: add delimited area in .text to store data
A few variables such as boot_mmu_config are stored within the .text section of tee.elf, because they need to be reachable from the identity mapping which covers a subset of .text. Having them here however is a problem when one wants to measure (hash) the .text section because the runtime content may be different from the content in the tee.elf. In order to workaround this issue, allocate an area in the .text section to gather the data that are modified at boot time. Symbols tagged with .identity_map.data will be stored there. Two delimiters are introduced: __text_data_start and __text_data_end.
Signed-off-by: Jerome Forissier <jerome@forissier.org> Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| d3a996cf | 01-Dec-2021 |
Jerome Forissier <jerome@forissier.org> |
kernel/linker.h: export __text_end
Add __text_end to <kernel/linker.h>. Can be used for example to compute a hash of the TEE executable code in a remote attestation scenario.
Signed-off-by: Jerome
kernel/linker.h: export __text_end
Add __text_end to <kernel/linker.h>. Can be used for example to compute a hash of the TEE executable code in a remote attestation scenario.
Signed-off-by: Jerome Forissier <jerome@forissier.org> Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 131547c7 | 05-Jan-2022 |
Jerome Forissier <jerome@forissier.org> |
plat-rcar: suppress text relocations in romapi_call.S
Replace address loads from the literal pool (ldr xN, =sym), which are subject to relocations, with a PC-relative address loads (adr_l xN, sym) t
plat-rcar: suppress text relocations in romapi_call.S
Replace address loads from the literal pool (ldr xN, =sym), which are subject to relocations, with a PC-relative address loads (adr_l xN, sym) to which the TEE load offset is added. The adr_l macro is used because the symbols may be far away.
Signed-off-by: Jerome Forissier <jerome@forissier.org> Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 28f6da21 | 11-Jan-2022 |
Jerome Forissier <jerome@forissier.org> |
core: arm64: suppress text relocations caused by restore_mapping macro
Suppress the text relocations caused by 'ldr x0, =1f' in macro restore_mapping when CFG_CORE_UNMAP_CORE_AT_EL0=y. Since this oc
core: arm64: suppress text relocations caused by restore_mapping macro
Suppress the text relocations caused by 'ldr x0, =1f' in macro restore_mapping when CFG_CORE_UNMAP_CORE_AT_EL0=y. Since this occurs when switching from the reduced kernel mapping to the full mapping, the code offset needs to be loaded from somewhere readily accessible at that point, that is the stack.
Signed-off-by: Jerome Forissier <jerome@forissier.org> Suggested-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 7611c8ee | 07-Jan-2022 |
Jerome Forissier <jerome@forissier.org> |
core: arm64: suppress text relocations in icache_inv_user_range()
When CFG_CORE_UNMAP_CORE_AT_EL0=y (default), icache_inv_user_range() uses addresses from the literal pool (ldr xN, =label) to jump t
core: arm64: suppress text relocations in icache_inv_user_range()
When CFG_CORE_UNMAP_CORE_AT_EL0=y (default), icache_inv_user_range() uses addresses from the literal pool (ldr xN, =label) to jump to/from the reduced mapping. Use adr and apply the code offset instead to eliminate the relocations when ASLR is turned on.
Signed-off-by: Jerome Forissier <jerome@forissier.org> Suggested-by: Jens Wiklander <jens.wiklander@linaro.org> Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 09608235 | 03-Dec-2021 |
Jerome Forissier <jerome@forissier.org> |
core: arm64: suppress some text relocations in thread_a64.S
A couple of locations in thread_a64.S use 'ldr xN, =symbol' to load the address of 'symbol'. Doing so creates an entry in the literal pool
core: arm64: suppress some text relocations in thread_a64.S
A couple of locations in thread_a64.S use 'ldr xN, =symbol' to load the address of 'symbol'. Doing so creates an entry in the literal pool which is subject to relocaton. In these cases, it is unnecessary because the code is already running in the relocated VA space, so the PC-relative macro 'adr_l xN, symbol' would load the proper address. Use this syntax instead.
Signed-off-by: Jerome Forissier <jerome@forissier.org> Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| 6ded7852 | 03-Dec-2021 |
Jerome Forissier <jerome@forissier.org> |
core: arm64: suppress text relocations in thread_optee_smc_a64.S
The readjust_pc macro in thread_optee_smc_a64.S relies on loading the address of a local label (1111f:) from the literal pool, knowin
core: arm64: suppress text relocations in thread_optee_smc_a64.S
The readjust_pc macro in thread_optee_smc_a64.S relies on loading the address of a local label (1111f:) from the literal pool, knowing that this address is modified when relocations are applied. It is a way of converting PC addresses from the identity map to the "normal" VA space, i.e. the one to which ASLR has been applied. However, this approach creates a relocation inside the .text section (TEXTREL) which is generally undesirable.
Replace the mechanism with a load using the 'adr' instruction, which obtains an address in the identity map, then add the ASLR offset found in the boot_mmu_config structure. This gets rid of 8 text relocations.
Signed-off-by: Jerome Forissier <jerome@forissier.org> Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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