drivers/tpm2: Add basic TPM2 support in OP-TEE

TPM2 driver introduced in this commit is based on TPM TCG
specification [1] & [2].

The APIs exposed allows to send commands and receive response
from

drivers/tpm2: Add basic TPM2 support in OP-TEE

TPM2 driver introduced in this commit is based on TPM TCG
specification [1] & [2].

The APIs exposed allows to send commands and receive response
from a TPM2 chip.

[1] TCG PC Client Platform TPM Profile Specification for TPM 2.0
Vesrion 1.0.5 Revision 14
[2] TCG PC Client Device Driver Design Principles for TPM 2.0
Version 1.1 Revision 0.04

Co-developed-by: Victor Chong <victor.chong@linaro.org>
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: io: add {get/put}_unaligned_be{16/32/64}()

Add 16, 32 and 64 bits put/get functions for big endian
unaligned access

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Reviewed-by: Jens W

core: io: add {get/put}_unaligned_be{16/32/64}()

Add 16, 32 and 64 bits put/get functions for big endian
unaligned access

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: mm: fix core virtual address range constraint in lpae

Changes strategy to set core virtual memory addresses in case pager
is enabled (CFG_WITH_PAGER=y) with LPAE (CFG_WITH_LPAE=y). In this
con

core: mm: fix core virtual address range constraint in lpae

Changes strategy to set core virtual memory addresses in case pager
is enabled (CFG_WITH_PAGER=y) with LPAE (CFG_WITH_LPAE=y). In this
configuration the virtual memory addresses are expected to fit in a
single base translation table in order to save 4kB translation pages.
This change makes core to fallback to the generic layout, possibly
spreading virtual addresses over several base translation tables if
the virtual memory addresses do not fit in the optimized address
range preferred for that configuration.

Fixes: https://github.com/OP-TEE/optee_os/issues/5201
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-vexpress: embed dt_driver test in qemu_virt and qemu_armv8a

Default embeds DT_DRIVER probing test with companion DTS file in
vexpress qemu_virt and qemu_armv8a. These platforms do not embed
any

plat-vexpress: embed dt_driver test in qemu_virt and qemu_armv8a

Default embeds DT_DRIVER probing test with companion DTS file in
vexpress qemu_virt and qemu_armv8a. These platforms do not embed
any DTB so we can set straight CFG_EMBED_DTB_SOURCE_FILE.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: dt_driver: drivers to test probe deferral

Implements driver providers for some emulated resource (clocks and reset
controllers), consumer drivers and a embedded test DTSI file to
test the DT_D

core: dt_driver: drivers to test probe deferral

Implements driver providers for some emulated resource (clocks and reset
controllers), consumer drivers and a embedded test DTSI file to
test the DT_DRIVER probe sequence.

The driver consumer run few tests and logs results locally. The
result participates in core self test result reported by the
PTA test interface.

One can test with vexpress platform flavor qemu_virt and qemu_v8 using,
for example, the build instruction below:
make PLATFORM=vexpress-qemu_virt \
CFG_DT_DRIVER_EMBEDDED_TEST=y \
CFG_EMBED_DTB_SOURCE_FILE=embedded_dtb_test.dts

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: clk: add CFG_DRIVERS_CLK_EARLY_PROBE

Adds configuration switch to allow clocks to be probed as any driver,
possibly deferring initialization. This is needed when a clock driver
has dependen

drivers: clk: add CFG_DRIVERS_CLK_EARLY_PROBE

Adds configuration switch to allow clocks to be probed as any driver,
possibly deferring initialization. This is needed when a clock driver
has dependencies on another resource.

The configuration is default enabled (CFG_DRIVERS_CLK_EARLY_PROBE=y)
that is probing clock drivers before other drivers using the early_init
initcall level as done prior this change.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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arm: aspeed: fix kernel panic while getting gicd & gicc va

commit 60801696667d ("plat: arm: refactor GIC initialization") unifies
GIC initialization flow into common gic code and get GIC distributor

arm: aspeed: fix kernel panic while getting gicd & gicc va

commit 60801696667d ("plat: arm: refactor GIC initialization") unifies
GIC initialization flow into common gic code and get GIC distributor/CPU
interface virtual addresses with 64KB granularity.

However, Aspeed SoC hardware design only used 4KB granularity for
each of them. Revise register GICD/GICC physical memory size to meet
gic init requirement. (from 4KB to 64KB)
This commit would result in memory map overlaps warning.

Signed-off-by: Neal Liu <neal_liu@aspeedtech.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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dts: stm32mp1: add IWDG1/2 watchdogs support

Add the IWDG1 and IWDG2 watchdog support in stm32mp15 SoCs and define
the watchdog timeout configuration.

On ED1/EV1/DK1/DK2 boards, IWDG1 is default di

dts: stm32mp1: add IWDG1/2 watchdogs support

Add the IWDG1 and IWDG2 watchdog support in stm32mp15 SoCs and define
the watchdog timeout configuration.

On ED1/EV1/DK1/DK2 boards, IWDG1 is default disabled while IWDG2 is
enabled and assigned to non-secure world. Despite IWDG2 is assigned
to non-secure world, TEE may need to kick the watchdog during
transitions when non-secure is not able to do so as some power
management transitions.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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plat-stm32mp1: conf: enable watchdog support

Add the watchdog enable by default on STM32MP1 platform.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Lionel Debieve <lionel.debi

plat-stm32mp1: conf: enable watchdog support

Add the watchdog enable by default on STM32MP1 platform.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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plat-stm32mp1: add watchdog platform functions

Add the platform function to retrieve the watchdog OTP
configuration. Register the debug function to dump
register in case of watchdog detected event.

plat-stm32mp1: add watchdog platform functions

Add the platform function to retrieve the watchdog OTP
configuration. Register the debug function to dump
register in case of watchdog detected event.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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drivers: stm32_iwdg: implementation of independent watchdog

Implements independent watchdog (IWDG) driver to help detecting
malfunctions due to software or hardware failures. IWDG instances
are cloc

drivers: stm32_iwdg: implementation of independent watchdog

Implements independent watchdog (IWDG) driver to help detecting
malfunctions due to software or hardware failures. IWDG instances
are clocked by an independent clock and stays active if the main
clock fails.

The driver mandates IWDG instances configuration from an embedded DTB.

For the list of features, refer to the reference manuals at:
https://wiki.st.com/stm32mpu/wiki/STM32MP15_resources

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

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core: sp: map device regions from SP manifest

Map the device regions defined in the SP manifest file into the SP's
context. In the manifest fdt the device's PA is overwritten with the VA
after mappi

core: sp: map device regions from SP manifest

Map the device regions defined in the SP manifest file into the SP's
context. In the manifest fdt the device's PA is overwritten with the VA
after mapping. This fdt is passed to the SP on boot and can be used by
the SP to determine the VA of the device.

The content of the SP manifest is defined in the FF-A specification.
The devicetree binding for the SP manifest is defined at the link below.

Link: https://trustedfirmware-a.readthedocs.io/en/latest/components/ffa-manifest-binding.html
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Signed-off-by: Jelle Sels <jelle.sels@arm.com>

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core: sp_mem: add security attribute

Currently sp_mem only supports non-secure memory. This patch enables
using it for secure memory too.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed

core: sp_mem: add security attribute

Currently sp_mem only supports non-secure memory. This patch enables
using it for secure memory too.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Signed-off-by: Jelle Sels <jelle.sels@arm.com>

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core: sp_mem: add memory type attribute

Currently sp_mem only supports TEE_MATTR_MEM_TYPE_CACHE memory type.
This patch adds support for using it with any type so it can be used
for device memory to

core: sp_mem: add memory type attribute

Currently sp_mem only supports TEE_MATTR_MEM_TYPE_CACHE memory type.
This patch adds support for using it with any type so it can be used
for device memory too.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Signed-off-by: Jelle Sels <jelle.sels@arm.com>

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plat-stm32mp1: define backup register secure accesses

Implements access permissions for stm32mp1 backup registers accesses.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: E

plat-stm32mp1: define backup register secure accesses

Implements access permissions for stm32mp1 backup registers accesses.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-stm32mp1: default embed stm32_tamp driver

Default enable CFG_STM32_TAMP in stm32mp1 platform configuration
with there is an embedded DTB.

Acked-by: Jerome Forissier <jerome.forissier@linaro.or

plat-stm32mp1: default embed stm32_tamp driver

Default enable CFG_STM32_TAMP in stm32mp1 platform configuration
with there is an embedded DTB.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: add stm32 tamper domain driver

Adds stm32_tamp driver for stm32mp1 TAMP sub-system. The implementation
only covers probing of the driver upon embedded DTB content and enabling
some secure c

drivers: add stm32 tamper domain driver

Adds stm32_tamp driver for stm32mp1 TAMP sub-system. The implementation
only covers probing of the driver upon embedded DTB content and enabling
some secure configuration.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: crypto: stm32_cryp: fix coding style issues

Removes spurious space characters in stm32_cryp driver implementation
to conform with optee_os coding style.

Reviewed-by: Jerome Forissier <jero

drivers: crypto: stm32_cryp: fix coding style issues

Removes spurious space characters in stm32_cryp driver implementation
to conform with optee_os coding style.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: crypto: stm32_cryp: probe as a dt_driver

Changes stm32_cryp driver to register as a DT driver and support
probe deferral on clock and reset controller resources.

Acked-by: Jerome Forissier

drivers: crypto: stm32_cryp: probe as a dt_driver

Changes stm32_cryp driver to register as a DT driver and support
probe deferral on clock and reset controller resources.

Acked-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: imx: add UART4 base address for iMX8QM/QP

Some iMX8QM boards use the UART4.

Acked-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Clément Péron <peron.clem@gmail.com>

plat-stm32mp1: add STM32MP13 platform support

Add specific platform code for STM32MP13 initialization.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Gabriel Fernandez <gab

plat-stm32mp1: add STM32MP13 platform support

Add specific platform code for STM32MP13 initialization.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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clk: stm32mp13: add all clocks for STM32MP13

Registers all STM32PM13 clock with the clock framework.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Gabriel Fernandez <gabri

clk: stm32mp13: add all clocks for STM32MP13

Registers all STM32PM13 clock with the clock framework.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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clk: stm32mp13: Introduce STM32MP13 clocks platform

This driver uses a clk-stm32-core API to manage STM32 gates, dividers
and muxes.
The goal of this first patch is to parse the device tree and init

clk: stm32mp13: Introduce STM32MP13 clocks platform

This driver uses a clk-stm32-core API to manage STM32 gates, dividers
and muxes.
The goal of this first patch is to parse the device tree and initialize
a platform data to configure the clock tree.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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dt-bindings: stm32: add stm32mp13 clock and reset bindings

Add new clocks and reset binding files to manage STM32MP13 RCC.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Ga

dt-bindings: stm32: add stm32mp13 clock and reset bindings

Add new clocks and reset binding files to manage STM32MP13 RCC.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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plat-stm32mp1: add stub for clock parents registering for stm32mp13

No need to register secure clock parents for STM32MP13 platform.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-

plat-stm32mp1: add stub for clock parents registering for stm32mp13

No need to register secure clock parents for STM32MP13 platform.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

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