core: lpae: check return value of core_mmu_xlat_table_entry_pa2va()

Since core_mmu_xlat_table_entry_pa2va() can return a NULL pointer, check
its return value before the memcpy().

Fixes: 8bdbbf2f5 (

core: lpae: check return value of core_mmu_xlat_table_entry_pa2va()

Since core_mmu_xlat_table_entry_pa2va() can return a NULL pointer, check
its return value before the memcpy().

Fixes: 8bdbbf2f5 ("core: lpae: add internal core_mmu_entry_copy()")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: remove unnecessary header

Remove the following header:
* utee_defines.h

Fixes: f5a70e3e ("drivers: crypto: generic resources for crypto device driver - RSA")
Signed-off-by: Clement

drivers: crypto: remove unnecessary header

Remove the following header:
* utee_defines.h

Fixes: f5a70e3e ("drivers: crypto: generic resources for crypto device driver - RSA")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: crypto: remove unnecessary header

Remove the following header:
* utee_defines.h

Fixes: e43ab7a8 ("core: driver: generic resources for crypto cipher driver")
Signed-off-by: Clement Faure <

drivers: crypto: remove unnecessary header

Remove the following header:
* utee_defines.h

Fixes: e43ab7a8 ("core: driver: generic resources for crypto cipher driver")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: remove unnecessary header

Remove the following header:
* caam_utils_mem.h

Fixes: 2d7a8964 ("driver: implement CAAM driver")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acke

drivers: caam: remove unnecessary header

Remove the following header:
* caam_utils_mem.h

Fixes: 2d7a8964 ("driver: implement CAAM driver")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: fix potential memory leak

Free CAAM buffer pabufs before exiting the function in case of an error.

Fixes: 38923d487 ("drivers: caam: implement CAAM DMA Object")
Signed-off-by: Clemen

drivers: caam: fix potential memory leak

Free CAAM buffer pabufs before exiting the function in case of an error.

Fixes: 38923d487 ("drivers: caam: implement CAAM DMA Object")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: caam: avoid arithmetic operation for pointer assignment

To parse the pointer array priv->sgtdata[], use this syntax array[idx]
instead of array + idx.
The new syntax is easier to read and l

drivers: caam: avoid arithmetic operation for pointer assignment

To parse the pointer array priv->sgtdata[], use this syntax array[idx]
instead of array + idx.
The new syntax is easier to read and less prone to errors.

Fixes: 38923d48 ("drivers: caam: implement CAAM DMA Object")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-aspeed: ast2600: control HACE into Secure World

1. Prohibit non-secure access to HACE controller
2. Grant TEE secure memory access to HACE.

Signed-off-by: Neal Liu <neal_liu@aspeedtech.com>
Ac

plat-aspeed: ast2600: control HACE into Secure World

1. Prohibit non-secure access to HACE controller
2. Grant TEE secure memory access to HACE.

Signed-off-by: Neal Liu <neal_liu@aspeedtech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: crypto: aspeed: hace: fix digest incorrect problem

1. The processing status variable is not set to TEE_SUCCESS if
everything works fine.
2. DMA memory needs physically contiguous memory. Al

drivers: crypto: aspeed: hace: fix digest incorrect problem

1. The processing status variable is not set to TEE_SUCCESS if
everything works fine.
2. DMA memory needs physically contiguous memory. Allocate aligned
DMA memory and copy data from/to DMA memory to make sure consistency
of data.

Signed-off-by: Neal Liu <neal_liu@aspeedtech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: crypto: aspeed: hace: resolve build issues

Resolve various build and typo issues.

Fixes: commit e752c173aa0f ("crypto/aspeed: ast2600: Add HACE HW hash support")
Signed-off-by: Neal Liu <n

drivers: crypto: aspeed: hace: resolve build issues

Resolve various build and typo issues.

Fixes: commit e752c173aa0f ("crypto/aspeed: ast2600: Add HACE HW hash support")
Signed-off-by: Neal Liu <neal_liu@aspeedtech.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: Fix compile warning in RPMB storage initialization

Fix the below warning when GCC 10.2.0 toolchain is used:

core/tee/tee_rpmb_fs.c:1137:3: warning: ‘dev_info’ may be used uninitialized in thi

core: Fix compile warning in RPMB storage initialization

Fix the below warning when GCC 10.2.0 toolchain is used:

core/tee/tee_rpmb_fs.c:1137:3: warning: ‘dev_info’ may be used uninitialized in this function [-Wmaybe-uninitialized]
memcpy(rpmb_ctx->cid, dev_info.cid, RPMB_EMMC_CID_SIZE);

Signed-off-by: Sadiq Hussain <sadiq.muchumarri@intel.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-rockchip: rk3399: define GICC_BASE

Commit 60801696667d ("plat: arm: refactor GIC initialization") has
introduced a build regression for Rockchip:

$ make -s PLATFORM=rockchip-rk3399
core/arch

plat-rockchip: rk3399: define GICC_BASE

Commit 60801696667d ("plat: arm: refactor GIC initialization") has
introduced a build regression for Rockchip:

$ make -s PLATFORM=rockchip-rk3399
core/arch/arm/plat-rockchip/main.c: In function ‘main_init_gic’:
core/arch/arm/plat-rockchip/main.c:29:29: error: ‘GICC_BASE’ undeclared (first use in this function); did you mean ‘GIC_BASE’?
29 | gic_init(&gic_data, GICC_BASE, GICD_BASE);
| ^~~~~~~~~
| GIC_BASE

Fix it by defining GICC_BASE unconditionally as most platforms do.
The value is taken from the DTS file from the Linux kernel [1].

Fixes: 60801696667d ("plat: arm: refactor GIC initialization")
Link: [1] https://github.com/torvalds/linux/blob/v5.17/arch/arm64/boot/dts/rockchip/rk3399.dtsi#L542
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat: arm: fix refactor GIC initialization

Commit 60801696667d ("plat: arm: refactor GIC initialization") converts
functions gic_init_base_addr() and gic_init() to take physical addresses
instead of

plat: arm: fix refactor GIC initialization

Commit 60801696667d ("plat: arm: refactor GIC initialization") converts
functions gic_init_base_addr() and gic_init() to take physical addresses
instead of virtual, but only converts half the platforms. This causes
boot failure on all the others.

Convert the rest here.

Fixes: 60801696667d ("plat: arm: refactor GIC initialization")
Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
[jf: wrap lines >80 characters; cite commit using commonly used format]
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: caam: add JR interrupt only if CFG_CAAM_ITR=y

Adding the JR interrupt in the OPTEE CAAM driver, even if not used in
OPTEE, prevents the Linux CAAM driver from using the JR interrupt on
plat

drivers: caam: add JR interrupt only if CFG_CAAM_ITR=y

Adding the JR interrupt in the OPTEE CAAM driver, even if not used in
OPTEE, prevents the Linux CAAM driver from using the JR interrupt on
platforms sharing the same line of interruption for all job rings.

To dequeue job from the job ring, the Linux CAAM driver would pull the
number of jobs done from the output ring slot full register.

The fix is to add the JR interrupt only if CFG_CAAM_ITR=y. This
allows the Linux CAAM driver to dequeue jobs faster than polling from
a register.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: caam: fix function definition when CFG_CAAM_NO_ITR=y

There is a bug in the CAAM JR interruption enablement logic. When
CFG_CAAM_NO_ITR=y, the JR interruptions are used and when
CFG_CAAM_NO_

drivers: caam: fix function definition when CFG_CAAM_NO_ITR=y

There is a bug in the CAAM JR interruption enablement logic. When
CFG_CAAM_NO_ITR=y, the JR interruptions are used and when
CFG_CAAM_NO_ITR=n, the JR interruptions are not used.

Even with this wrong logic, the CAAM is still able to enqueue jobs.
When no JR interruptions are received, the CAAM will manually dequeue
jobs from the jobring by checking the number of jobs done in the output
ring slots full register.

CAAM JR interruptions are not mandatory for the CAAM to work properly
but it makes the dequeuing faster than polling the output ring slot full
register.

To avoid confusion, replace CFG_CAAM_NO_ITR with CFG_CAAM_ITR. The
CFG_CAAM_ITR is enabled by default and platforms not using the JR
interruptions would have this flag disabled instead.

Fixes: 3f45afc31 ("drivers: caam: disable the use of interrupts for some platforms")
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: clk: Fix check for assigned-clock-rates index

Index should actually be strictly less than rate_len. Fix this which
might happen with the following description:

assigned-clock = <foo>, <bar

drivers: clk: Fix check for assigned-clock-rates index

Index should actually be strictly less than rate_len. Fix this which
might happen with the following description:

assigned-clock = <foo>, <bar>;
assigned-clock-parents = <foo_parent>, <bar_parent>;
assigned-clock-rates = <1000>;

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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core: dt_driver: allow parsing of phandle == 0

In Linux, it is allowed to specify a null phandle which means it should
be skipped. Add support for this specific case by simply skipping over
it. This

core: dt_driver: allow parsing of phandle == 0

In Linux, it is allowed to specify a null phandle which means it should
be skipped. Add support for this specific case by simply skipping over
it. This is needed to parse assigned-clock-parents which can use such
syntax. This is specified in the clock bindings [1] which says the
following:

To skip setting parent or rate of a clock its corresponding entry
should be set to 0, or can be omitted if it is not followed by any
non-zero entry

For example this is a valid device-tree description:

assigned-clocks = <foo>, <bar>;
assigned-clock-parents = <0> <bar_parent>;
assigned-clock-rates = <1000>;

Link: [1] https://www.kernel.org/doc/Documentation/devicetree/bindings/clock/clock-bindings.txt
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Clément Léger <clement.leger@bootlin.com>

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drivers: imx: dump TZASC state after lockdown

Call the TZASC configuration dump after the region lockdown.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.fo

drivers: imx: dump TZASC state after lockdown

Call the TZASC configuration dump after the region lockdown.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: imx: tzc380: register TZC380 memory registers

Register TZASC memory registers for TZASC and eventually TZASC2.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissi

drivers: imx: tzc380: register TZC380 memory registers

Register TZASC memory registers for TZASC and eventually TZASC2.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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drivers: tzc380: fix the lockdown range register value

This register controls the range of regions that are locked down.
The number of regions to lockdown are defined in [1]:
lockdown_range[3:0] and

drivers: tzc380: fix the lockdown range register value

This register controls the range of regions that are locked down.
The number of regions to lockdown are defined in [1]:
lockdown_range[3:0] and its value goes from b0000 to b1111.

If the goal of tzc_regions_lockdown() is to lock all regions supported
by the platforms, then the value of lockdown_range[3:0] should be equal
to no_of_regions[3:0] of the configuration register [2].

Currently, tzc.num_regions is used to defined the lockdown range which
is incorrect because it has been incremented during initialization.
Fix the issue by decrementing tzc.num_regions before the configuration
of lockdown_range[3:0].

Link: [1] https://developer.arm.com/documentation/ddi0431/c/programmers-model/register-descriptions/lockdown-range-register
Link: [2] https://developer.arm.com/documentation/ddi0431/c/programmers-model/register-descriptions/configuration-register
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: imx: add TZASC_SIZE for imx6, imx7 and imx8m

Add TZASC_SIZE value for all i.MX platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@lin

core: imx: add TZASC_SIZE for imx6, imx7 and imx8m

Add TZASC_SIZE value for all i.MX platforms.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: fix use after free in tee_ta_open_session()

Fixes a use after free where the session pointer 's' was used after
tee_ta_close_session() while recovering from an error.

Fixes: 82061b8d7b34 ("co

core: fix use after free in tee_ta_open_session()

Fixes a use after free where the session pointer 's' was used after
tee_ta_close_session() while recovering from an error.

Fixes: 82061b8d7b34 ("core: store TA params in session struct")
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-versal: add support for Xilinx's Versal ACAP platform

Initial support for the Versal ACAP validated on the AI Core Series VKC190
Evaluation Kit.

The following BIF file is used by bootgen to ge

plat-versal: add support for Xilinx's Versal ACAP platform

Initial support for the Versal ACAP validated on the AI Core Series VKC190
Evaluation Kit.

The following BIF file is used by bootgen to generate the Versal boot.bin
image.

the_ROM_image:
{
image {
{ type=bootimage, file=vpl_gen_fixed.pdi }
{ type=bootloader, file=plm.elf }
{ core=psm, file=psmfw.elf }
}

image {
id = 0x1c000000, name=apu_subsystem
{ type=raw, load=0x00001000, file=system.dtb }
{ core=a72-0, exception_level=el-3, trustzone, file=bl31.elf }
{ core=a72-0, exception_level=el-2, file=u-boot.elf }
{ core=a72-0, exception_level=el-1, trustzone, file=tee.elf }
}
}

$ ./bootgen -arch versal -image boot.bif -o BOOT.BIN

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: John Linn <linnj@xilinx.com>
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>

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plat-stm32mp1: scmi: export some STPMIC1 regulators as voltage domains

Exposes STPMIC1 regulators through agent channel SCMI for platform
stm32mp1.

Acked-by: Jens Wiklander <jens.wiklander@linaro.o

plat-stm32mp1: scmi: export some STPMIC1 regulators as voltage domains

Exposes STPMIC1 regulators through agent channel SCMI for platform
stm32mp1.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: dt-bindings: stm32mp1: add IDs for STPMIC1 SCMI voltage regulators

Define the SCMI voltage domain IDs exposed by OP-TEE SCMI server on
stm32mp1.

Acked-by: Jens Wiklander <jens.wiklander@linar

core: dt-bindings: stm32mp1: add IDs for STPMIC1 SCMI voltage regulators

Define the SCMI voltage domain IDs exposed by OP-TEE SCMI server on
stm32mp1.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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drivers: stpmic1: export regulators API in a specific header file

Split stpmic1.h in 2 parts, one specifically for STPMIC1 regulator
interface.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

drivers: stpmic1: export regulators API in a specific header file

Split stpmic1.h in 2 parts, one specifically for STPMIC1 regulator
interface.

Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

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