drivers: stm32_omm: add OSPI Memory Manager driver

This patch adds OSPI Memory Manager driver.
It handles:
- IOM configuration
- OSPIs address mapping
- IOM sub-system firewall configuration

Signed

drivers: stm32_omm: add OSPI Memory Manager driver

This patch adds OSPI Memory Manager driver.
It handles:
- IOM configuration
- OSPIs address mapping
- IOM sub-system firewall configuration

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Co-developed-by: Christophe Kerello <christophe.kerello@foss.st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp2: sysconfig: add OSPIs address mapping

This patch adds an API to handle OSPIs address mapping.
The different configurations are:
- OSPI1(256 MBytes), OSPI2(unmapped)
- OSPI1(192 MByte

plat-stm32mp2: sysconfig: add OSPIs address mapping

This patch adds an API to handle OSPIs address mapping.
The different configurations are:
- OSPI1(256 MBytes), OSPI2(unmapped)
- OSPI1(192 MBytes), OSPI2(64 MBytes)
- OSPI1(128 MBytes), OSPI2(128 MBytes)
- OSPI1(64 MBytes), OSPI2(192 MBytes)
- OSPI1(unmapped), OSPI2(256 MBytes).

Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dts: stm32: add the SYSCFG node in stm32mp251.dtsi

Add the SYSCFG node in the stm32mp251.dtsi file. This allows some devices
to access global system configuration registers.

Signed-off-by: Gatien C

dts: stm32: add the SYSCFG node in stm32mp251.dtsi

Add the SYSCFG node in the stm32mp251.dtsi file. This allows some devices
to access global system configuration registers.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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dt-bindings: update LTDC layer numbers on stm32mp2x platforms

On stm32mp2x platforms, according to the reference manual, the LTDC
layers are named L1/2/3, not L0/1/2.

Signed-off-by: Gatien Chevalli

dt-bindings: update LTDC layer numbers on stm32mp2x platforms

On stm32mp2x platforms, according to the reference manual, the LTDC
layers are named L1/2/3, not L0/1/2.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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riscv: mm: Fix VA base for canonical addresses

RISC-V defines the following virtual address rules:
- For Sv39 (39-bit VA), bits 63–39 all equal to bit 38 of VA
- For Sv48 (48-bit VA), bits 63–48 all

riscv: mm: Fix VA base for canonical addresses

RISC-V defines the following virtual address rules:
- For Sv39 (39-bit VA), bits 63–39 all equal to bit 38 of VA
- For Sv48 (48-bit VA), bits 63–48 all equal to bit 47 of VA
- For Sv57 (57-bit VA), bits 63–57 all equal to bit 56 of VA

In other words, the most-significant bits of VA base must be all one if
the highest SvXX address bit of VA is one.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mm: fix va to index calculation for RV64

On RV64, shifting va is not enough when top bits are
present in the virtual address, e.g. for Sv48, bits
63-48 must be set when bit 47 is set to form a

core: mm: fix va to index calculation for RV64

On RV64, shifting va is not enough when top bits are
present in the virtual address, e.g. for Sv48, bits
63-48 must be set when bit 47 is set to form a valid
virtual address.

In this case, we need to mask the base-level virtual
addresses to clear any extended bits before calculating
the index.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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core: riscv: mm: add per-mapping VA range validation

Replace single maximum VA check with individual VA
range validation for each memory map entry during MMU
initialization, providing earlier detect

core: riscv: mm: add per-mapping VA range validation

Replace single maximum VA check with individual VA
range validation for each memory map entry during MMU
initialization, providing earlier detection of invalid
mappings.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mm: factor out virtual address range validation to arch code

Move virtual address range validation into architecture-specific
code since different architectures have different constraints on
v

core: mm: factor out virtual address range validation to arch code

Move virtual address range validation into architecture-specific
code since different architectures have different constraints on
valid VA ranges:

- For ARM, addresses must be within the VA width supported by the MMU
- For RISC-V, additional checks are needed on RV64 to ensure addresses
are canonically valid

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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riscv: mm: fix map_offset data type

Fix the data type of map_offset to allow storing 64-bit
offset on RV64.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alving

riscv: mm: fix map_offset data type

Fix the data type of map_offset to allow storing 64-bit
offset on RV64.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: mm: refactor ASLR mapping for architecture support

To allow adding RISC-V ASLR support, add arch_aslr_base_addr()
which will be used to apply architecture specific ASLR base
calculation.

Sign

core: mm: refactor ASLR mapping for architecture support

To allow adding RISC-V ASLR support, add arch_aslr_base_addr()
which will be used to apply architecture specific ASLR base
calculation.

Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Alvin Chang <alvinga@andestech.com>

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spmc: fix FF-A manifest boot-order handling

According to the official manifest binding documentation [1], all
integer properties must be defined as 32-bit wide DTB properties.
However, the OP-TEE SP

spmc: fix FF-A manifest boot-order handling

According to the official manifest binding documentation [1], all
integer properties must be defined as 32-bit wide DTB properties.
However, the OP-TEE SPMC previously implemented the boot-order property
as a 16-bit value. This patch corrects that inconsistency by adding
support for the correct 32 bit representation while keeping backwards
compatibility.

Recent changes in TF-A’s build tooling have broken support for manifest
files using the "/bits/" width specifier. This update restores
compatibility by eliminating the need to use them.

[1] FF-A Manifest Binding
Link: https://trustedfirmware-a.readthedocs.io/en/v2.12.0/components/ffa-manifest-binding.html

Signed-off-by: Gyorgy Szing <gyorgy.szing@arm.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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drivers: stm32_rifsc: fix RIMU configuration parsing

The RIF configuration of the first RIMU was incorrectly parsed over and
over again for each RIMU. Fix this by using the index that represents
the

drivers: stm32_rifsc: fix RIMU configuration parsing

The RIF configuration of the first RIMU was incorrectly parsed over and
over again for each RIMU. Fix this by using the index that represents
the RIMU ID.

Fixes: cd187630b280 ("drivers: add stm32 RIFSC support")
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rifsc: remove redundant and incorrect parsing of RIMU conf

In case we're not TDCID, we cannot configure RIMUs. Plus, the call was
redundant with the lines above.

Fixes: 471cec144fa3

drivers: stm32_rifsc: remove redundant and incorrect parsing of RIMU conf

In case we're not TDCID, we cannot configure RIMUs. Plus, the call was
redundant with the lines above.

Fixes: 471cec144fa3 ("drivers: stm32_rifsc: update RIFSC as a firewall controller")
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_hpdma: implement transient CID0 on AHB errata for HPDMAs

On stm32mp2x SoCs, when an AHB busy signal is inserted during a
transaction, a ghost CID0 is generated on the bus. If the comp

drivers: stm32_hpdma: implement transient CID0 on AHB errata for HPDMAs

On stm32mp2x SoCs, when an AHB busy signal is inserted during a
transaction, a ghost CID0 is generated on the bus. If the compartment
filtering is enabled on RISAB3/4/5, this transient CID0 is interpreted
as a fault access by RISAB3/4/5 which aborts current access and returns
an IAC. Described in section 2.3.21 of errata sheet available here: [1].
Therefore, when CID filtering is enabled on RISAB, we must ban CID0 as
a possible CID value configured for any initiator on the bus.
This avoids a conflict between an initiator holding CID0 and the
transient CID0.

When "st,errata-ahbrisab" is set in the device tree, HPDMA channels cannot
hold the CID0 value on the bus.

Link: https://www.st.com/resource/en/errata_sheet/es0598-stm32mp23xx25xx-device-errata-stmicroelectronics.pdf [1]
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_rifsc: implement transient CID0 on AHB errata for RIMUs

On stm32mp2x SoCs, when an AHB busy signal is inserted during a
transaction, a ghost CID0 is generated on the bus. If the compa

drivers: stm32_rifsc: implement transient CID0 on AHB errata for RIMUs

On stm32mp2x SoCs, when an AHB busy signal is inserted during a
transaction, a ghost CID0 is generated on the bus. If the compartment
filtering is enabled on RISAB3/4/5, this transient CID0 is interpreted
as a fault access by RISAB3/4/5 which aborts current access and returns
an IAC. Described in section 2.3.21 of errata sheet available here: [1].
Therefore, when CID filtering is enabled on RISAB, we must ban CID0 as
a possible CID value configured for any initiator on the bus.
This avoids a conflict between an initiator holding CID0 and the
transient CID0.

When "st,errata-ahbrisab" is set in the device tree, RIMUs cannot hold
the CID0 value on the bus.

Link: https://www.st.com/resource/en/errata_sheet/es0598-stm32mp23xx25xx-device-errata-stmicroelectronics.pdf [1]
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_risab: implement transient CID0 on AHB errata for RISAB

On stm32mp2x SoCs, when an AHB busy signal is inserted during a
transaction, a ghost CID0 is generated on the bus. If the compa

drivers: stm32_risab: implement transient CID0 on AHB errata for RISAB

On stm32mp2x SoCs, when an AHB busy signal is inserted during a
transaction, a ghost CID0 is generated on the bus. If the compartment
filtering is enabled on RISAB3/4/5, this transient CID0 is interpreted
as a fault access by RISAB3/4/5 which aborts current access and returns
an IAC. Described in section 2.3.21 of errata sheet available here: [1].
Therefore, when CID filtering is enabled on RISAB, we must ban CID0 as
a possible CID value configured for any initiator on the bus.
This avoids a conflict between an initiator holding CID0 and the
transient CID0.

Force authorize CID0 access on RISAB so that it can always access
memories protected by RISABs when the "st,errata-ahbrisab" property is
set in the device tree.

Link: https://www.st.com/resource/en/errata_sheet/es0598-stm32mp23xx25xx-device-errata-stmicroelectronics.pdf [1]
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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caam: fix compilation when CFG_NXP_CAAM_AE_* are disabled

Similarly to other CAAM modules, define empty function if CAAM AE is
not used, to avoid undefined reference to caam_ae_init().

Signed-off-b

caam: fix compilation when CFG_NXP_CAAM_AE_* are disabled

Similarly to other CAAM modules, define empty function if CAAM AE is
not used, to avoid undefined reference to caam_ae_init().

Signed-off-by: Pavel Löbl <pavel@loebl.cz>
Acked-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-k3: drivers: ti-sci: Add support for setting KEYREV

Add support for the TI-SCI OTP message TI_SCI_MSG_WRITE_KEYREV. This
allows for incrementing the key revision counter.

Signed-off-by: Andrew

plat-k3: drivers: ti-sci: Add support for setting KEYREV

Add support for the TI-SCI OTP message TI_SCI_MSG_WRITE_KEYREV. This
allows for incrementing the key revision counter.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-k3: drivers: ti-sci: Add support for setting SWREV

Add support for the TI-SCI OTP message TI_SCI_MSG_WRITE_SWREV. This
allows for incrementing the software revision counter.

Signed-off-by: And

plat-k3: drivers: ti-sci: Add support for setting SWREV

Add support for the TI-SCI OTP message TI_SCI_MSG_WRITE_SWREV. This
allows for incrementing the software revision counter.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-k3: drivers: ti-sci: Fix struct name in comments for OTP functions

A couple of the documented names for the OTP functions do not match
the struct names being documented. Fix this.

Signed-off-b

plat-k3: drivers: ti-sci: Fix struct name in comments for OTP functions

A couple of the documented names for the OTP functions do not match
the struct names being documented. Fix this.

Signed-off-by: Andrew Davis <afd@ti.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

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drivers: stm32_iwdg: check for error on clk_enable during probe

Check for the error returned by clk_enable() during the driver's
probe.
While there, if watchdog is started but we cannot control it,

drivers: stm32_iwdg: check for error on clk_enable during probe

Check for the error returned by clk_enable() during the driver's
probe.
While there, if watchdog is started but we cannot control it,
trigger panic instead of return error. This also avoids adding
useless clk_disable() in the error exit path.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_iwdg: add get_timeleft watchdog handler

Implement .get_timeleft() watchdog operation handler for non-secure
world to query the watchdog device state. System time is logged at each
wat

drivers: stm32_iwdg: add get_timeleft watchdog handler

Implement .get_timeleft() watchdog operation handler for non-secure
world to query the watchdog device state. System time is logged at each
watchdog refresh to estimate time remaining before the watchdog elapses.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: wdt: add implementation of SMCWD_GET_TIMELEFT

Implement watchdog SMC service SMCWD_GET_TIMELEFT that is optional
and allows non-secure world to get information on watchdog state.
The servic

drivers: wdt: add implementation of SMCWD_GET_TIMELEFT

Implement watchdog SMC service SMCWD_GET_TIMELEFT that is optional
and allows non-secure world to get information on watchdog state.
The service is supported by new watchdog driver operation handler
get_timeleft.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_iwdg: remove OTP access in driver

Now we know if the watchdog is running by reading the hardware,
there is no need to read the OTP fuses related to the watchdog.
This allows removing

drivers: stm32_iwdg: remove OTP access in driver

Now we know if the watchdog is running by reading the hardware,
there is no need to read the OTP fuses related to the watchdog.
This allows removing platform function stm32_get_iwdg_otp_config()
and consequently stm32_iwdg.h header file.

Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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drivers: stm32_iwdg: probe if watchdog is running

Read from the hardware whether watchdog is already running when
core initializes. Relax timeout from 1 to 10ms to let the
watchdog warm-up when enab

drivers: stm32_iwdg: probe if watchdog is running

Read from the hardware whether watchdog is already running when
core initializes. Relax timeout from 1 to 10ms to let the
watchdog warm-up when enabled.

Signed-off-by: Antonio Borneo <antonio.borneo@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Gatien Chevallier <gatien.chevallier@foss.st.com>

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